CN112018174A - Semiconductor device, manufacturing method thereof and household appliance - Google Patents

Abstract

The present application discloses a semiconductor device, a manufacturing method thereof, and a household appliance. The semiconductor device includes an N+-type emitter region, a P-type base region, an N-type drift region, an N-type buffer region and a P+-type collector region, and a penetrating N+ Type emitter region, P-type base region and part of the first gate and second gate of the N-type drift region, and N+-type collector region penetrating the P+-type collector region. Further, through the periodic structure of the N+-type collector region and the P+-type collector region, to reduce the density of holes near the collector region, the carrier concentration inside the semiconductor device can be balanced.

Description

A kind of semiconductor device and its manufacturing method, household appliance

technical field

The present application relates to the technical field of semiconductor devices, and in particular, to a semiconductor device, a manufacturing method thereof, and a household appliance.

Background technique

IEGT (Injection Enhanced Gate Bipolar Transistor, gate injection enhanced bipolar transistor) is based on the IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) structure, by increasing the width of the trench gate, or designing a dummy element. It limits the hole injection capability of the IEGT collector, thereby increasing the proportion of electron current to the total current, and achieving a more balanced carrier concentration distribution inside the device in the on state.

However, the above measures are only a preliminary balance of the carrier concentration inside the IEGT. Since the large on-resistance near the gate of the IEGT is still one of the bottlenecks of the device impedance, the carrier density near the gate and the concentration of The carrier density near the electrode is still relatively low, therefore, how to further improve the equilibrium distribution of carrier concentration inside the device has become an urgent problem to be solved.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present application provides a semiconductor device, a manufacturing method thereof, and a household appliance, which can balance the carrier concentration inside the semiconductor device.

In order to solve the above-mentioned technical problem, a technical solution adopted in the present application is to provide a semiconductor device, the semiconductor device includes: an N+ type emitter region, a P type base region, an N type drift region, an N type buffer region and P+-type collector region; the first gate and the second gate, the first gate and the second gate penetrate the N+-type emitter region, the P-type base region and part of the N-type drift region; wherein, the P+-type collector region An N+-type collector region which penetrates through the P+-type collector region and is connected with the N-type buffer region is arranged in the middle.

The N+-type collector region includes: a first N+-type collector region; a second N+-type collector region; wherein the first N+-type collector region and the second N+-type collector region are in the P+-type collector region, and arranged at horizontal intervals.

Wherein, the first N+-type collector region and the second N+-type collector region are respectively disposed at both ends of the P+-type collector region along the lateral direction, and correspond to the first gate and the second gate respectively.

The number of N+-type collector regions is multiple, and the multiple N+-type collector regions divide the P+-type collector regions into multiple pieces, so that multiple N+-type collector regions and multiple P+-type collector regions are alternately arranged .

Wherein, the N+-type emitter region includes: a first N+-type emitter region; a second N+-type emitter region; wherein, the first N+-type emitter region and the second N+-type emitter region are arranged at intervals along the lateral direction, and the first grid The electrode runs through the first N+ type emitter region, and the second gate runs through the second N+ type emitter region.

Wherein, the first N+ type emitter region and the second N+ type emitter region are arranged at a lateral interval, the first gate passes through the first N+ type emitter region, and the second gate passes through the second N+ type emitter region.

The first N+ type emitter region is disposed on the side of the first gate close to the second gate, and the second N+ type emitter region is disposed on the side of the second gate close to the first gate.

Wherein, the depth of the first gate and the second gate is greater than 1/3 of the overall depth of the semiconductor device, and less than 1/2 of the overall depth of the semiconductor device.

Wherein, the N+-type collector region penetrates the P+-type collector region and at least part of the N-type buffer region.

The first gate and the second gate are trench gates, and an oxide layer is disposed between each gate and the corresponding trench.

Among them, the N-type drift region and the N-type buffer region are also provided with an N+-type blocking region.

The semiconductor device further includes a first metal layer, an insulating layer and a second metal layer; wherein the first metal layer is arranged on the side of the N+ type emitter region away from the P+ type collector region, and the second metal layer is arranged on the P+ type The collector region is away from the side of the N+ type emitter region, and the insulating layer is disposed between the first gate electrode and the first metal layer, and between the second gate electrode and the first metal layer.

In order to solve the above technical problem, another technical solution adopted in the present application is to provide a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate; fabricating a gate on the semiconductor substrate; fabricating a P-type base region respectively and N+-type emitter region; make N-type drift region and N-type buffer region respectively on the side of P-type base region away from N+-type emitter region; make P+-type collector on the side of N-type buffer region away from N-type drift region Electrode region and N+-type collector region; wherein, the N+-type collector region penetrates the P+-type collector region and is connected to the N-type buffer region, and the gate penetrates the N+-type emitter region, the P-type base region and part of the N-type drift region. .

Among them, forming a P+-type collector region and an N+-type collector region on the side of the N-type buffer away from the N-type drift region, including: alternately injecting P+-type ions and N+-type ions, so as to be far away from the N-type buffer in the N-type buffer. One side of the drift region is formed with P+-type collector regions and N+-type collector regions alternately arranged laterally.

In order to solve the above-mentioned technical problem, another technical solution adopted in the present application is to provide a household appliance, which includes the above-mentioned semiconductor device, or includes the above-mentioned semiconductor device manufacturing method.

The beneficial effects of the embodiments of the present application are: different from the prior art, in the semiconductor device provided by the present application, by arranging an N+ type collector region running through the P+ type collector region in the P+ type collector region of the semiconductor device, using N+ The periodic structure of the P+-type collector region and the P+-type collector region narrows the moving channel of hole carriers near the P+-type collector region, thereby limiting the injection efficiency of holes and improving the injection efficiency of electrons. The structure can reduce the density of holes near the collector region to further balance the carrier concentration inside the semiconductor device.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

1 is a schematic diagram of an IEGT structure for increasing gate width in the prior art;

Fig. 2 is the IEGT structure schematic diagram of design cell in the prior art;

Fig. 3 is the distribution diagram of the internal carrier density of IEGT in the prior art;

4 is a schematic structural diagram of a first embodiment of a semiconductor device provided by the present application;

5 is a distribution diagram of the internal carrier density in the first embodiment of the semiconductor device provided by the present application;

6 is a schematic structural diagram of a second embodiment of the semiconductor device provided by the present application;

7 is a schematic structural diagram of a third embodiment of the semiconductor device provided by the present application;

8 is a distribution diagram of the internal carrier density in the third embodiment of the semiconductor device provided by the present application;

FIG. 9 is a schematic structural diagram of a fourth embodiment of the semiconductor device provided by the present application;

FIG. 10 is a schematic flowchart of the first embodiment of the manufacturing method of the semiconductor device provided by the present application;

FIG. 11 is a schematic flowchart of a second embodiment of the method for fabricating a semiconductor device provided by the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all the structures related to the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

Semiconductor devices generally include semiconductor triodes, bipolar semiconductor devices, field-effect semiconductor devices, IGBTs, and IEGTs. Among them, the IGBT is a transistor designed in series on the MOS structure (full name MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide-semiconductor field-effect transistor structure), and a large amount is injected into the drift region 11 of the MOS structure through the transistor during conduction. The majority carrier, thereby enhancing the current capability of the MOS tube; when it is turned off, the transistor is also turned off, which can enhance the high-voltage resistance of the MOS tube itself. On the basis of the IGBT structure, the IEGT10 is usually obtained by increasing the width of the gate 12. As shown in Figure 1, this structure can balance the spatial distribution of the carrier density inside the device and reduce the on-state loss; The dummy cell is designed, as shown in Fig. 2, this structure can limit the injection efficiency of holes and balance the carrier density inside the IEGT.

After long-term research, the inventors of the present application found that the method of increasing the gate width as shown in Figure 1 physically limits the hole injection efficiency at the bottom of the IEGT. In order to obtain a stable working saturation current, the IEGT needs to inject a larger The electron current can supplement the carrier concentration inside the device. The carrier density distribution inside the existing IEGT 20 is shown in Figure 3. It can be seen from Figure 3 that although increasing the width of the gate 22 can preliminarily balance the carrier concentration inside the IEGT, the structure near the gate 22 is relatively large. The on-resistance is still one of the bottlenecks of the device impedance, resulting in the carrier density near the gate electrode 22 is still lower compared to the carrier density near the collector electrode 21 . To this end, the present application proposes the following embodiments.

Referring to FIG. 4, FIG. 4 is a schematic structural diagram of a first embodiment of a semiconductor device provided by the present application. In this embodiment, the semiconductor device is an IEGT, wherein the IEGT 40 includes a first metal layer 401, an insulating layer 402, An N+ type emitter region 403 , a P type base region 404 , an N type drift region 405 , an N type buffer region 406 , a P+ type collector region 407 and a second metal layer 408 . The first metal layer 401 is disposed on the side of the N+ type emitter region 403 away from the P+ type collector region 407 , and the second metal layer 408 is disposed on the side of the P+ type collector region 407 away from the N+ type emitter region 403 .

Optionally, the IEGT 40 further includes a first gate 409 and a second gate 410, wherein the first gate 409 and the second gate 410 are trench gates, which are arranged in the corresponding trenches and pass through the N+ type emitter The pole region 403, the P-type base region 404 and part of the N-type drift region 405; in this embodiment, the first gate 409 and the second gate 410 may be arranged perpendicular to the upper surface of the IEGT 40. The upper surfaces of the first gate 409, the second gate 410 and the IEGT 40 can also be designed with a certain inclination angle (for example, 20 degrees), which can reduce the scattering resistance of carriers moving in the trench, and further Reduce the turn-on voltage drop of the IEGT40.

Optionally, the N+-type emitter region 403 includes a first N+-type emitter region 403a and a second N+-type emitter region 403b, wherein the first N+-type emitter region 403a and the second N+-type emitter region 403b are in the lateral direction The directions are spaced apart, and the lateral direction is also the direction indicated by the X arrow shown in FIG. 4 , and the first gate 409 penetrates the first N+ type emitter region 403a, and the second gate 410 penetrates the second N+ type emitter The electrode regions 403 b , namely the first N+ type emitter regions 403 a are disposed on both sides of the first gate 409 , and the second N+ type emitter regions 403 b are disposed on both sides of the second gate 410 .

Optionally, a first gate oxide layer 409a and a second gate oxide layer 410a are respectively disposed between the first gate electrode 409 and the second gate electrode 410 and the corresponding trenches, wherein the first gate oxide layer 409a and the second gate oxide layer 410a respectively cover the surface of each trench, and are in contact with the gate electrode and the P-type base region 404; the first gate electrode 409 and the second gate electrode 410 are filled and disposed away from the gate oxide layer On one side of the N-type drift region 405, and the depths of the first gate 409 and the second gate 410 are smaller than the depths of the corresponding trenches, the depth direction is also the direction indicated by the Y arrow shown in FIG. 4, wherein, The direction indicated by the Y arrow is the extending direction of the depth of the first gate 409 and the second gate 410 .

Further, the IEGT 40 further includes an N+-type collector region 411 extending through the P+-type collector region 407, wherein the N+-type collector region 411 includes a first N+-type collector region 411a and a second N+-type collector region 411b. An N+-type collector region 411 a and a second N+-type collector region 411 b are spaced apart along the lateral direction in the P+-type collector region 407 , and both are connected to the N-type buffer region 406 . In this embodiment, the first N+-type collector region 411a and the second N+-type collector region 411b may be respectively disposed at both ends of the P+-type collector region 407 along the lateral direction, and are respectively connected with the first gate 409 and The second gate 410 is correspondingly arranged.

In this embodiment, when a forward voltage is applied to the gate, the electron channel formed by the reverse of the regions where the first gate 409 and the second gate 410 are formed can communicate with the N+ type emitter region 403 and the N-type drift. area 405 to realize the switching function of the entire IEGT40. Specifically, when the voltage applied to the gate and the source is positive and greater than the turn-on voltage, a channel is formed in the MOSFET in the IEGT40 and a current is provided for the semiconductor device to turn on the IEGT40; when the gate and the source are turned on When no signal is applied or reverse voltage is applied, the channel in the MOSFET disappears, the current in the IEGT is cut off, and the IEGT40 is turned off.

It can be understood that the insulating layer 402 can fully protect the first gate 409 and the second gate 410 during the manufacturing process or the use process, so that the device stability of the IEGT 40 is better. The insulating layer 402 is disposed between the first gate 409 and the first metal layer 401 and between the second gate 410 and the second metal layer 401 . In addition, the widths of the first gate 409 and the second gate 410 in the lateral direction are larger than the gate widths of general semiconductor device structures.

Optionally, the IEGT 40 may further include an N+-type blocking region (not shown), the N+-type blocking region is disposed between the N-type drift region 405 and the N-type buffer region 406 to form an FS structure.

In some embodiments, the specific type of material for forming the IEGT40 is not particularly limited, and any IGBT substrate commonly used in the art can be used, and those skilled in the art can make corresponding selections according to the specific electrical performance requirements of the semiconductor device. In some embodiments, the material for forming the N+-type emitter region 403 , the P-type base region 404 , the N-type drift region 405 and the P+-type collector region 407 may be Si, because the semiconductor device made of silicon has better stability , The voltage is low and the adaptability is strong. In other embodiments, the material for forming the above-mentioned base layer may also be SiC, so that the IEGT40 has better withstand voltage performance, higher current and higher voltage.

In this embodiment, by periodically injecting N+ ions into the P+-type collector region 407 on the backside of the IEGT 40 , a first penetrating P+-type collector region 407 is formed at both ends of the P+-type collector region 407 in the lateral direction. The N+-type collector region 411a and the second N+-type collector region 411b narrow the movement channel of hole carriers near the P+-type collector region 407, thereby limiting the injection efficiency of holes, while the injection efficiency of electrons Further improvement, the density distribution of carriers in this embodiment is shown in FIG. 5 , the dotted line part in FIG. 5 represents the density distribution of carriers in the existing semiconductor device, and the solid line part represents the carriers in this embodiment It can be seen that compared with the general IEGT, the novel IEGT40 structure reduces the carrier concentration near the back P+-type collector region 407, and increases the carrier near the gate and the emitter. concentration, such a structure is beneficial to reduce the resistance near the gate of the IEGT 40 and the N-type drift region 405, thereby reducing the on-voltage drop and on-state loss of the device.

It can be understood that the change in the composition of the carrier concentration is beneficial to the turn-off characteristics of the semiconductor device. When the device is turned off, a large number of hole carriers usually remain inside the device, which can prolong the turn-off time of the device. . If the hole concentration decreases and the electron concentration increases in the carrier concentration distribution of the device, the turn-off time and turn-off loss of the device can be improved.

In some other embodiments, the N+-type collector region 411 may penetrate through the P+-type collector region 407 and at least part of the N-type buffer region 406 . Such a structure can further limit the injection efficiency of holes, thereby improving the load carrying capacity inside the device. The carrier concentration is balanced. The N+-type collector region 411 may also penetrate through all the N-type buffer regions 406 and be directly connected to the N-type drift region 405 .

Therefore, in this embodiment, by periodically injecting N+ ions into the P+ type collector region 407 on the back side of the IEGT40, a periodic structure of the N+ type collector region 411 and the P+ type collector region 407 is formed, thereby reducing the internal structure of the device. The injection efficiency of holes improves the balance of carrier concentration inside IEGT40.

Referring to FIG. 6, FIG. 6 is a schematic structural diagram of a second embodiment of a semiconductor device provided by the present application. In this embodiment, the semiconductor device is an IEGT, wherein the IEGT 60 includes a first metal layer 601, an insulating layer 602, N+-type emitter region 603, P-type base region 604, N-type drift region 605, N-type buffer region 606, P+-type collector region 607, and second metal layer 608; and in the above embodiment, the N+-type emitter region 603 is penetrated , the first gate 609 and the second gate 610 of the P-type base region 604 and part of the N-type drift region 605 . The N+-type emitter region 603 includes a first N+-type emitter region 603a and a second N+-type emitter region 603b, which are spaced along the lateral direction of the IEGT 60, that is, the X direction shown in FIG. 6 .

The IEGT 60 further includes a first gate oxide layer 609a disposed between the first gate 609 and the corresponding trench, and a second gate oxide 610a disposed between the second gate 610 and the corresponding trench, wherein, The first gate 609 and the second gate 610 are filled and disposed on the side of the gate oxide layer away from the N-type drift region 605 .

Further, the IEGT 60 also includes an N+ type collector region 611 penetrating the P+ type collector region 607. The difference from the previous embodiment is that the number of the N+ type collector regions 611 in this embodiment is multiple, as shown in FIG. 6, the three N+-type collector regions 611 in FIG. 6 can divide the P+-type collector region 607 into two. At this time, there are two N+-type collector regions 611 which are arranged in the lateral direction of the P+-type collector region 607. The P+-type collector region 607 can also be divided into three or four, and the N+-type collector region 611 is arranged in the middle part of the P+-type collector region 607, so that a plurality of N+-type collector regions 611 The collector regions 611 and the plurality of P+-type collector regions 607 are alternately arranged laterally. The quantity is not specifically limited here.

In this embodiment, the periodic structure composed of a plurality of N+ type collector regions 611 and a plurality of P+ type collector regions 607 further limits the injection efficiency of holes, while the injection efficiency of electrons is further improved, which is beneficial to reduce the backside The carrier concentration near the P+ type collector region 607 increases the carrier concentration near the first gate 609 , the second gate 610 and the emitter metal electrode to further balance the carrier concentration inside the IEGT 60 .

Referring to FIG. 7, FIG. 7 is a schematic structural diagram of a third embodiment of the semiconductor device provided by the present application. In this embodiment, the semiconductor device is an IEGT, wherein the IEGT 70 includes a first metal layer 701, an insulating layer 702, N+-type emitter region 703, P-type base region 704, electron storage layer 705, N-type drift region 706, N-type buffer region 707, P+-type collector region 708, and second metal layer 709; also including through N+-type emitter The first gate 710 and the second gate 711 of the region 703 , the P-type base region 704 and part of the N-type drift region 706 .

The IEGT 70 further includes a first gate oxide layer 710a disposed between the first gate electrode 710 and the corresponding trench, and a second gate oxide layer 711a disposed between the second gate electrode 711 and the corresponding trench, wherein, The first gate 710 and the second gate 711 are filled and disposed on the side of the gate oxide layer away from the N-type drift region 706 .

Different from the previous embodiment, this embodiment is provided with an electron storage layer 705 between the P-type base region 704 and the N-type drift region 706, the electron storage layer 705 is used for trapping holes, and an N+-type emitter region The first N+ type emitter region 703a and the second N+ type emitter region 703b in 703 are respectively disposed on opposite sides of the first gate 710 and the second gate 711, that is, the first gate 710 and the second gate 711. The two gate electrodes 711 are away from each other on one side.

Specifically, by injecting a high concentration of N+ ions at the bottom of the P-type base region 704 of the IEGT70, an N+-type electron storage layer is formed, and the N+-type electron storage layer can be used as a trap for holes. Since the injected N+ ions are negatively charged, and The holes are positively charged, therefore, a large number of free electrons in the N+ type electron storage layer attract the hole carriers in the direction of the N-type drift region 706 away from the first metal layer 701 to move to the electron storage layer 705, so that the electron storage layer 705 is moved. The electrons and holes are recombined, and the recombination process will increase the density of electrons and holes in the area near the electron storage layer 705, that is, the carrier density in the area near the electron storage layer 705 is increased. At the same time, the N-type buffer in the IEGT70 The area near the region 707 loses some holes, so the carrier density in the area near the N-type buffer area 707 is reduced.

Further referring to FIG. 8, FIG. 8 is a distribution diagram of the internal carrier density in the third embodiment of the semiconductor device provided by the present application, wherein the dotted line part represents the carrier density distribution in the existing semiconductor device, and the solid line part is Representing the carrier density distribution in this embodiment, it can be seen that due to the existence of the electron storage layer 705, the carrier density near the gate is increased, while the carrier density near the collector is relatively reduced, so that The structure can further balance the carrier distribution of the device, so as to be more suitable for the application of household appliances such as inverter air conditioners.

Therefore, in this embodiment, the N+ type electron storage layer is formed by injecting a high concentration of N+ ions between the P-type base region 704 and the N-type drift region 706, so that the carrier density in the vicinity of the electron storage layer 705 is increased. , On the basis of increasing the gate width to initially balance the carrier concentration inside the IEGT, the carrier concentration inside the IEGT40 is further balanced.

Referring to FIG. 9, FIG. 9 is a schematic structural diagram of a fourth embodiment of a semiconductor device provided by the present application. In this embodiment, the semiconductor device is an RC-IEGT (Reverse Conducting IEGT, reverse conducting IEGT). For the reverse conducting IEGT For the IEGT, it is usually hoped that the electron current near the transmitter is as high as possible, which is beneficial to improve the modulation conductance near the gate and reduce the turn-off loss; and for the anti-parallel FRD (Fast recovery diode) in the reverse conduction type IEGT, For fast recovery diodes), in order to reduce the peak reverse recovery current and improve the softness of the switch, it is usually desirable to reduce the charge concentration near the emitter, which is an inherent contradiction of RC-IGBTs.

Therefore, in this embodiment, the RC-IEGT 90 includes a stacked first metal layer 901, an insulating layer 902, an N+ type emitter region 903, a P type base region 904, an N type drift region 905, an N type buffer region 906, The P+ type collector region 907 and the second metal layer 908 . Also included are a first gate 909 and a second gate 910 penetrating the N+ type emitter region 903 , the P type base region 904 and part of the N type drift region 905 .

Optionally, the N+ type emitter region 903 includes a first N+ type emitter region 903a and a second N+ type emitter region 903b, wherein the first N+ type emitter region 903a is disposed on the first gate 909 close to the second gate The second N+ type emitter region 903b is disposed on the side of the second gate 910 close to the first gate 909 and connected with the second The gate oxide layer 910a is connected to the first metal layer 901 . Compared with the common semiconductor device structure, the N+ type emitter region 903 outside the gate on the P type base region 904 is removed.

Further, the RC-IEGT 90 further includes an N+-type collector region 911 extending through the P+-type collector region 907, wherein the N+-type collector region 911 includes a first N+-type collector region 911a and a second N+-type collector region 911b , the first N+-type collector region 911a and the second N+-type collector region 911b are spaced apart along the lateral direction in the P+-type collector region 907, in some embodiments, the N+-type collector region 911 may also penetrate part of the N-type collector region 911b Buffer 906. In this embodiment, the first N+-type collector region 911a and the second N+-type collector region 911b are respectively disposed at both ends of the P+-type collector region 907 and the N-type buffer region 906 along the lateral direction.

In this embodiment, since the N+ type emitter region 903 is disposed inside the first gate 909 and the second gate 910, the opposite sides of the two, that is, the side away from each other, are not provided with emitters; at this time, In the depth direction (Y direction) of the opposite outer sides of the first gate 909 and the second gate 910, an N+ type collector formed by doping N+ ions into the P+ type collector region 907 and the N type buffer region 906 on the backside of the semiconductor device The electrode region 911 is arranged opposite to the P-type base region 904 with a part of the emitter region removed from the front side, forming a P-N structure, that is, forming an FRD, so that the integrated FRD and IEGT are both affected by the periodic structure of the collector region. To a certain extent, they are isolated from each other, so that the two are relatively independent in structure. The relatively independent FRD and IEGT can alleviate the inherent contradiction in the requirements of emitter carrier density in semiconductor devices.

In some embodiments, the depths of the first gate 909 and the second gate 910 are not particularly limited, and those skilled in the art can make corresponding designs according to specific electrical performance requirements of the semiconductor device. In some embodiments, the distance between the bottoms of the first gate 909 and the second gate 910 and the upper surface of the P-type base region 904 close to the N-type drift region 905 may be 0.2 to 1 micrometer, so that the gates may be Better control of conductance modulation effects. In some embodiments, the distance between the bottom of each gate and the upper surface of the P-type base region 904 near the N-type drift region 905 may be 0.5 microns.

In some other embodiments, the depth of the first gate 909 and the second gate 910 may be greater than 1/3 of the overall depth of the semiconductor device, and less than 1/2 of the overall depth of the semiconductor device. Such a structural design can further enhance the FRD The layout is relatively independent from the IEGT, which can further alleviate the contradiction between the two on the different requirements of the emitter carrier density.

In some embodiments, the distance between the first gate 909 and the second gate 910 is not particularly limited, and those skilled in the art can design it accordingly according to the specific electrical performance requirements of the semiconductor device. In some embodiments, the distance between the first gate 909 and the second gate 910 may be 1 to 3 microns, so that the maximum current density that can flow through the semiconductor device can be increased. In some embodiments, the spacing between the first gate 909 and the second gate 910 may be 2 microns.

Referring to FIG. 10, FIG. 10 is a schematic flowchart of a first embodiment of a method for fabricating a semiconductor device provided by the present application. The method includes:

S11: Provide a semiconductor substrate.

The material of the semiconductor substrate may be silicon nitride.

S12: forming a gate on the semiconductor substrate.

Specifically, step S12 mainly includes: forming a first trench and a second trench on the semiconductor substrate, and the first trench and the second trench pass through the N+ type emitter region, the P type base region and part of the N type drift region ; A first gate and a second gate are formed in the first trench and the second trench, respectively.

S13: respectively making a P-type base region and an N+-type emitter region.

The first gate, the second gate, the P-type base region and the N+-type emitter region constitute the active region of the semiconductor device.

S14: respectively forming an N-type drift region and an N-type buffer region on the side of the P-type base region away from the N+-type emitter region.

S15: A P+-type collector region and an N+-type collector region are formed on the side of the N-type buffer zone away from the N-type drift region.

The N+-type collector region runs through the P+-type collector region and is connected to the N-type buffer region.

The N+-type emitter region, P-type base region, N-type drift region, N-type buffer region, and collector region are stacked and formed by ion implantation.

Referring to FIG. 11 , FIG. 11 is a schematic flowchart of a second embodiment of a method for fabricating a semiconductor device provided by the present application, and the method includes:

S201. Implantation and trap push of the field confinement ring: perform high temperature oxidation on the silicon wafer, grow an implantation mask on its surface, perform ion implantation through a lithography plate, and perform high temperature well push, and then perform an annealing process to form a field limit The ring structure, depending on the lithographic window, is placed in a P-type field-limiting ring after annealing.

S202. Etching the active area: grow a layer of field oxygen with a thickness of 0.3 to 0.5 microns on the surface of the silicon wafer, and photolithographically form the active area. The active area includes an N+ type emitter area, a P type base area and a gate structure .

S203, making the gate: depositing a TEOS protective layer on the surface of the silicon wafer, lithography out the window for trench etching, and then forming the first trench and the second trench of the gate structure, and forming the inner wall of the trench A gate oxide layer is formed, and then polysilicon is deposited in the trench to form a first gate electrode and a second gate electrode, respectively.

S204. Implantation and well push of P-type base region and N+-type emitter region: The device is fabricated by ion implantation of P-type impurity and N-type impurity, and high-temperature push-well is performed, and the P-type base region and N+-type of the device are formed after annealing. emitter region.

S205 , making the emitter: depositing metal on the surface of the device, and using photolithography and etching processes to form a first metal layer, that is, the emitter metal.

S206, implantation of N+ type blocking region: forming an electric field blocking region of the device by ion implanting N+ type impurities.

S207. Implantation of N-type buffer and P+-type collector region: by ion implantation of N+-type impurities, a buffer zone is formed in the silicon wafer with high crystal quality; the silicon wafer is turned over, the thickness of the silicon wafer is reduced, and P is injected into the back of the silicon wafer type impurities and annealed to form a P+ type collector region.

S208, implantation of N+ type collector region: periodically injecting N+ type impurities into the P+ type collector region and annealing to form an N+ type collector region. Wherein, the N+-type collector regions and the P+-type collector regions are arranged alternately laterally.

S209, back gold annealing: perform a backside laser annealing process on the backside of the silicon wafer.

S210, making a collector electrode: depositing metal on the backside to form a second metal layer, that is, a collector electrode.

The above-mentioned manufacturing method can shorten the development time and reduce the production cost by adopting a limited-process improved production process on the original IGBT production line.

In the description of this specification, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. . For those of ordinary skill in the art, the above-mentioned specific meanings in the present application can be understood according to specific situations.

In the description of this specification, the description of the terms "one embodiment", "another embodiment", etc. means that a particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present application or in the example. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above description is only an embodiment of the present application, and is not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims (14)

1. A semiconductor device, characterized in that the semiconductor device comprises: N+-type emitter region, P-type base region, N-type drift region, N-type buffer region and P+-type collector region arranged in layers; a first gate and a second gate, which penetrate the N+ type emitter region, the P-type base region and part of the N-type drift region; Wherein, the P+-type collector region is provided with an N+-type collector region which penetrates through the P+-type collector region and is connected to the N-type buffer region. 2. The semiconductor device according to claim 1, wherein The N+ type collector region includes: the first N+ type collector region; the second N+ type collector region; Wherein, the first N+-type collector region and the second N+-type collector region are in the P+-type collector region and are arranged at intervals along the lateral direction. 3. The semiconductor device according to claim 2, wherein, The first N+-type collector region and the second N+-type collector region are respectively disposed at both ends of the P+-type collector region along the lateral direction, and are respectively connected with the first gate and the second gate electrode. grid corresponds. 4. The semiconductor device according to claim 1, wherein, The number of the N+-type collector regions is multiple, and the multiple N+-type collector regions divide the P+-type collector regions into multiples, so that the multiple N+-type collector regions are connected with the multiple N+-type collector regions. The P+-type collector regions are alternately arranged. 5. The semiconductor device according to any one of claims 1-4, wherein, The N+ type emitter region includes: the first N+ type emitter region; The second N+ type emitter region; Wherein, the first N+ type emitter region and the second N+ type emitter region are arranged at intervals along the lateral direction, the first gate passes through the first N+ type emitter region, and the second gate passes through the the second N+ type emitter region. 6. The semiconductor device according to claim 5, wherein, The first N+ type emitter region is disposed on the side of the first gate close to the second gate, and the second N+ type emitter region is disposed on the second gate close to the first gate extreme side. 7. The semiconductor device according to claim 1, wherein, The depths of the first gate and the second gate are greater than 1/3 of the overall depth of the semiconductor device and less than 1/2 of the overall depth of the semiconductor device. 8. The semiconductor device of claim 1, wherein The N+-type collector region penetrates the P+-type collector region and at least part of the N-type buffer region. 9. The semiconductor device of claim 1, wherein The first gate and the second gate are trench gates, and an oxide layer is disposed between each gate and the corresponding trench. 10. The semiconductor device of claim 1, wherein The N-type drift region and the N-type buffer region are also provided with an N+-type blocking region. 11. The semiconductor device of claim 1, wherein The semiconductor device further includes a first metal layer, an insulating layer, and a second metal layer; Wherein, the first metal layer is arranged on the side of the N+ type emitter region away from the P+ type collector region, and the second metal layer is arranged at the P+ type collector region away from the N+ type emitter region On one side of the pole region, the insulating layer is disposed between the first gate electrode and the first metal layer, and between the second gate electrode and the first metal layer. 12. A method of fabricating a semiconductor device, wherein the method comprises: providing a semiconductor substrate; forming a gate on the semiconductor substrate; Make P-type base region and N+-type emitter region respectively; respectively making an N-type drift region and an N-type buffer region on the side of the P-type base region away from the N+-type emitter region; forming a P+-type collector region and an N+-type collector region on the side of the N-type buffer zone away from the N-type drift region; Wherein, the N+-type collector region penetrates the P+-type collector region and is connected to the N-type buffer region, and the gate penetrates the N+-type emitter region, the P-type base region and part of the the N-type drift region. 13. The method of claim 12, wherein The forming a P+-type collector region and an N+-type collector region on the side of the N-type buffer zone away from the N-type drift region includes: P+-type ions and N+-type ions are implanted alternately to form laterally alternately arranged P+-type collector regions and N+-type collector regions on the side of the N-type buffer zone away from the N-type drift region. 14 . A household appliance, characterized in that the household appliance comprises the semiconductor device according to any one of claims 1 to 11 , or a semiconductor device manufactured by the method according to claim 12 or 13 .

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