CN112866593A - Pixel circuit and infrared imaging system - Google Patents
Pixel circuit and infrared imaging system Download PDFInfo
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- CN112866593A CN112866593A CN202110014440.2A CN202110014440A CN112866593A CN 112866593 A CN112866593 A CN 112866593A CN 202110014440 A CN202110014440 A CN 202110014440A CN 112866593 A CN112866593 A CN 112866593A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
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Abstract
The invention provides a pixel circuit and an infrared imaging system, and relates to the field of pixel circuits. The circuit comprises: the integrated circuit comprises an integration unit circuit, an analog-to-digital conversion unit circuit and a storage unit circuit; the integration unit circuit receives and integrates the photocurrent generated by the photoelectric detector to generate voltage to be quantized; the analog-to-digital conversion unit circuit acquires a voltage to be quantized, quantizes the voltage to be quantized and generates a digital quantity corresponding to photocurrent; the storage unit circuit acquires and stores the digital quantity and outputs the digital quantity to the column-level circuit; the overturning voltage of the comparator in the analog-digital conversion unit circuit is fixed as the reference voltage. In the working process of the comparator, the output deviation is low, the power consumption of the comparator is not required to be increased, the comparator can normally work only according to basic working characteristics, the linearity of the whole pixel circuit is high, and the practicability is good.
Description
Technical Field
The invention relates to the field of pixel circuits, in particular to a pixel circuit and an infrared imaging system.
Background
The infrared imaging system comprises the following components: the infrared optical system, the infrared detector array, a reading circuit of an electric signal output by the detector array and a machine core assembly for carrying out post-processing on an image. The infrared focal plane reading circuit is used as an important component of a focal plane detector assembly and is a bridge between an electrical signal generated by a detector array and a subsequent signal processing circuit. The readout circuit is divided according to the type of signal output from the readout circuit, and can be classified into an analog readout type and a digital readout type. The digital readout type can be further divided into output buffer stage analog-to-digital conversion, column stage analog-to-digital conversion, and pixel stage analog-to-digital conversion according to the position of the ADC.
In the pixel level analog-to-digital conversion, the area requirement of the pixel array is strict, wherein the output deviation of the comparator is high, and the power consumption of the comparator is necessarily increased in order to reduce the output deviation of the comparator, so how to reduce the output deviation of the comparator without increasing the power consumption of the comparator is a problem to be solved urgently.
Disclosure of Invention
The invention provides a pixel circuit and an infrared imaging system, and provides a technical scheme which reduces output deviation of a comparator and does not increase power consumption of the comparator.
A first aspect of an embodiment of the present invention provides a pixel circuit, where the pixel circuit includes: the integrated circuit comprises an integration unit circuit, an analog-to-digital conversion unit circuit and a storage unit circuit;
the integration unit circuit receives photocurrent generated by the photoelectric detector, integrates the photocurrent and generates voltage needing to be quantized;
the analog-to-digital conversion unit circuit acquires the voltage to be quantized, quantizes the voltage to be quantized and generates a digital quantity corresponding to the photocurrent;
the memory cell circuit acquires and stores the digital quantity, and outputs the digital quantity to the column stage circuit.
Optionally, the integration unit circuit comprises: the device comprises a first switch component, an NMOS tube and an integrating capacitor;
the source electrode of the NMOS tube is connected with the photoelectric detector;
the grid electrode of the NMOS tube is connected with the signal control circuit;
the drain electrode of the NMOS tube is respectively connected with the first end of the first switch component, the first end of the integrating capacitor and the analog-to-digital conversion unit circuit;
the second end of the first switch component is connected with the reset voltage end;
and the second end of the integrating capacitor is grounded.
Optionally, the analog-to-digital conversion unit circuit includes: the sampling circuit comprises a second switch component, a third switch component, a fourth switch component, a fifth switch component, a sampling capacitor and a comparator;
the first end of the second switch component is respectively connected with the drain electrode of the NMOS tube, the first end of the first switch component and the first end of the integrating capacitor;
the second end of the second switch component is respectively connected with the first end of the third switch component, the first end of the fourth switch component and the first end of the sampling capacitor;
a second terminal of the third switching component is connected with the reset voltage terminal;
the second end of the fourth switch component is connected with the slope voltage end;
the second end of the sampling capacitor is respectively connected with the inverting end of the comparator and the first end of the fifth switch component;
the in-phase end of the comparator is connected with the second end of the fifth switch component and the reference voltage end respectively;
the output end of the comparator is connected with the storage unit circuit.
Optionally, the memory cell circuit includes: a memory;
the memory is respectively connected with the output end of the comparator, the output end of the n-bit counter and the column level circuit.
Optionally, the signal control circuit generates an integration signal, a first reset signal, a second reset signal, a sampling signal, and a quantization signal;
the rising edge time point of the integration signal is the same as the rising edge time point of the first reset signal;
the falling edge time point of the integrated signal is the same as the rising edge time point of the second reset signal and the falling edge time point of the quantized signal;
the falling edge time point of the second reset signal is the same as the rising edge time point of the sampling signal;
the falling edge time point of the sampling signal is the same as the rising edge time point of the quantized signal.
Optionally, a high level holding time of the integration signal is longer than a high level holding time of the first reset signal;
the low level maintaining time of the integration signal is greater than the sum of the high level maintaining time of the first reset signal and the high level maintaining time of the second reset signal;
the low level maintaining time of the integral signal is longer than that of the quantized signal;
the low level maintaining time of the quantized signal is equal to the sum of the high level maintaining time of the first reset signal and the high level maintaining time of the second reset signal.
Optionally, when the integrated signal is at a high level, the NMOS transistor is turned on;
when the integral signal is at a low level, the NMOS tube is switched on and off;
when the first reset signal is at a high level, the first switch component is closed;
when the first reset signal is at a low level, the first switch assembly is switched off;
when the sampling signal is at a high level, the second switch component is closed;
when the sampling signal is at a low level, the second switch component is switched off;
when the second reset signal is at a high level, the third switch component is closed;
when the second reset signal is at a low level, the third switch component is turned off;
when the quantized signal is at a high level, the fourth switch component is closed;
when the quantized signal is at a low level, the fourth switch component is turned off;
when any one of the sampling signal and the second reset signal is at a high level, the fifth switch component is closed;
and when the sampling signal and the second reset signal are both at a low level, the fifth switch component is switched off.
Optionally, when the first switch component is closed, the voltage of the integrating capacitor is the same as the voltage of the reset voltage terminal;
when the NMOS tube is conducted, the photocurrent is integrated on the integrating capacitor to generate the voltage to be quantized;
when the third switch component is closed, the voltage of the first end of the sampling capacitor is the same as the voltage of the reset voltage end;
when the second switch component is closed, the voltage to be quantized is sampled to the first end of the sampling capacitor;
when the fourth switch component is closed, the voltage of the first end of the sampling capacitor is changed from the voltage needing to be quantized to the ramp voltage, and the voltage of the second end of the sampling capacitor is changed from the voltage of the reference voltage end to:
after the voltage of the reference voltage end is summed with the ramp voltage, the sum is subtracted from the voltage needing to be quantized to obtain a difference value;
when the fourth switch component is closed, the voltage of the second end of the sampling capacitor decreases with the decrease of the ramp voltage, and when the voltage of the second end of the sampling capacitor decreases to be equal to the voltage of the reference voltage end, the comparator sends an inversion to output a low level.
Optionally, the actual quantized voltage magnitude is:
and performing difference between the voltage of the reset voltage end and the voltage needing to be quantized to obtain the size of the difference value.
A second aspect of an embodiment of the present invention provides an infrared imaging system, including: an infrared detector and a plurality of pixel circuits as described in any one of the first aspect arranged according to the requirements of the pixel array.
In the pixel circuit provided by the invention, the integration unit circuit receives photocurrent generated by the photoelectric detector, integrates the photocurrent and generates voltage needing to be quantized; the analog-to-digital conversion unit circuit acquires a voltage needing to be quantized, quantizes the voltage needing to be quantized, generates a digital quantity corresponding to the photocurrent, and the storage unit circuit acquires and stores the digital quantity and outputs the digital quantity to the column-level circuit.
In the technical scheme of the invention, because the turnover voltage of the comparator in the analog-to-digital conversion unit circuit is fixed as the reference voltage and does not change along with the change of the photocurrent voltage, the delay time of the comparator is fixed for the analog-to-digital conversion of each pixel, so that the output deviation of the comparator is consistent when all pixels are subjected to the analog-to-digital conversion, and the output deviation can be naturally and directly removed as the background current, so that the linearity of the whole pixel circuit is higher, and the power consumption of the comparator is not required to be increased in the working process of the comparator. The pixel circuit has better practicability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a block diagram of a pixel circuit according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a preferred pixel circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of various signals in an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, there is shown a modular schematic diagram of a pixel circuit according to an embodiment of the invention, the circuit comprising: the integrated circuit comprises an integration unit circuit, an analog-to-digital conversion unit circuit and a storage unit circuit; the integration unit circuit receives photocurrent generated by the photoelectric detector, integrates the photocurrent and generates voltage needing to be quantized; the analog-to-digital conversion unit circuit acquires a voltage needing to be quantized, the voltage needing to be quantized is quantized, a digital quantity corresponding to photocurrent is generated, and the overturning voltage of a comparator in the analog-to-digital conversion unit circuit is fixed as a reference voltage VREF(ii) a The storage unit circuit acquires and stores the digital quantity and outputs the digital quantity to the column-level circuit; the n-bit counter counts time from the beginning of quantization to the time point when the comparator turns over, and the counting duration is the digital quantity of the corresponding photocurrent, so that analog-to-digital conversion of the pixel is realized.
Specifically, a schematic structural diagram of a preferred pixel circuit in an embodiment of the present invention is shown in fig. 2. The Pixel circuit (Pixel circuit) in fig. 2 includes: NMOS tube M1 and integrating capacitor CPIXThe circuit comprises a first switch assembly S1, a second switch assembly S2, a third switch assembly S3, a fourth switch assembly S4, a fifth switch assembly S5 and a sampling capacitor CSHComparator CMP, memory.
Wherein, integration unit circuit includes: NMOS tube M1 and integrating capacitor CPIXA first switch module S1; the analog-to-digital conversion unit circuit includes: a second switch assembly S2, a third switch assembly S3, a fourth switch assembly S4, a fifth switch assembly S5, a sampling capacitor CSHComparator CMP and memory. It should be noted that, in the embodiment of the present invention, the first switch groupThe device S1, the second switch assembly S2, the third switch assembly S3, the fourth switch assembly S4, and the fifth switch assembly S5 are all controlled by different signals, which are generated and sent by the signal control circuit 40. All components that can utilize the signal to realize the switch function can all be regarded as the switch module, for example: a Field Effect Transistor (MOS Transistor), a relay, and the like may all implement the function of closing and opening the circuit of the switch, which is not specifically limited in the embodiment of the present invention.
Specifically, the source of the NMOS transistor M1 and the photodetector DGThe gate of the NMOS transistor M1 is connected to the signal control circuit 40, and is controlled by the integration signal INT sent by the signal control circuit 40, where when the integration signal INT is at a high level, the NMOS transistor M1 is turned on, and when the integration signal INT is at a low level, the NMOS transistor M1 is turned off. The drain of the NMOS transistor M1, the first terminal of the first switch element S1, and the integrating capacitor CPIXFirst terminal (i.e. integrating capacitor C)PIXUpper plate of) and a first terminal of a second switching element S2 in the analog-to-digital conversion unit circuit, respectively. The second terminal of the first switch module S1 is connected with the reset voltage terminal VR, and the integrating capacitor CPIXSecond terminal (i.e. integrating capacitor C)PIXLower plate of) is grounded GND. The first switch element S1 is controlled by a first reset signal RST1 sent by the signal control circuit 40, wherein when the first reset signal RST1 is at a high level, the first switch element S1 is closed, and when the first reset signal RST1 is at a low level, the first switch element S1 is open.
The second terminal of the second switch element S2, the first terminal of the third switch element S3, the first terminal of the fourth switch element S4, and the sampling capacitor CSHFirst terminal (i.e. sampling capacitor C)SHLower plates) are connected respectively; the second switch module S2 is controlled by the sampling signal SH sent by the signal control circuit 40, when the sampling signal SH is at a high level, the second switch module S2 is closed, and when the sampling signal SH is at a low level, the second switch module S2 is open. A second terminal of the third switching component S3 is connected to the reset voltage terminal VR; the third switch assembly S3 is controlled by the second reset signal RST2 sent by the signal control circuit 40, when the second reset signal RST2 is at a high level, the third switch assembly S3 is closed, and the second reset signal RS is sentWhen T2 is low, the third switch element S3 is open. The fourth switch module S4 is controlled by the quantization signal AD sent by the signal control circuit 40, when the quantization signal AD is at a high level, the fourth switch module S4 is closed, and when the quantization signal AD is at a low level, the fourth switch module S4 is open.
The second end of the fourth switching component S4 is connected with the ramp voltage end VRAMP(ii) a Sampling capacitor CSHSecond terminal (i.e. sampling capacitor C)SHUpper plate of) is connected to the inverting terminal of the comparator CMP and the first terminal of the fifth switching element S5, respectively; the non-inverting terminal of the comparator CMP and the second terminal of the fifth switch module S5, the reference voltage terminal VREFAre respectively connected; the output terminal OUT of the comparator CMP is connected to the memory in the memory cell circuit. The memory is connected to the output terminal OUT of the comparator CMP, the output terminal of the n-bit counter, and the column stage circuit 50, respectively.
The fifth switch element S5 is controlled by the sampling signal SH and the second reset signal RST2 sent by the signal control circuit 40, and when any one of the sampling signal SH and the second reset signal RST2 is at a high level, the fifth switch element S5 is closed, and when both the sampling signal SH and the second reset signal RST2 are at a low level, the fifth switch element S5 is open.
In the embodiment of the present invention, the signal control circuit 40 is configured to generate the integration signal INT, the first reset signal RST1, the second reset signal RST2, the sampling signal SH, and the quantization signal AD; referring to fig. 3, a timing diagram of various signals in an embodiment of the invention is shown. Wherein, the rising edge time point of the integration signal INT is the same as the rising edge time point of the first reset signal RST 1; the falling edge time point of the integration signal INT is the same as the rising edge time point of the second reset signal RST2 and the falling edge time point of the quantization signal AD; the falling edge time point of the second reset signal RST2 is the same as the rising edge time point of the sampling signal SH; the falling edge time point of the sampling signal SH is the same as the rising edge time point of the quantization signal AD.
The high-level hold time of the integration signal INT is longer than that of the first reset signal RST 1; the low-level hold time of the integration signal INT is longer than the sum of the high-level hold time of the first reset signal RST1 and the high-level hold time of the second reset signal RST 2; the low level maintaining time of the integration signal INT is longer than that of the quantization signal AD; the low-level sustain time of the quantization signal AD is equal to the sum of the high-level sustain time of the first reset signal RST1 and the high-level sustain time of the second reset signal RST 2.
The above preferred pixel circuit in the embodiment of the present invention combines the time sequence of each signal, and the specific working principle is as follows: assuming that, for a pixel array with a frame frequency of 1kHz, at the beginning of a frame time, the integration signal INT and the first reset signal RST1 are both high, the NMOS transistor M1 is turned on, and the first switch element S1 is closed. Although the NMOS transistor M1 is turned on, the integrating capacitor CPIXThe voltage of the upper plate is still reset by the reset voltage terminal VR to be the same as the voltage generated by the reset voltage terminal VR, and the voltage is assumed to be VR. The first reset signal RST1 then goes low, the first switch element S1 is turned off, the integration signal INT continues to stay high, and the photodetector DGThe generated photocurrent is applied to an integrating capacitor CPIXUntil the integration signal INT becomes low level, the integration process is completed, at this time, the NMOS tube M1 is turned off, and the integration capacitor CPIXThe voltage to be quantized is accumulated on the upper plate, and the voltage to be quantized is assumed to be VSH。
Since the quantization signal AD is always high during the high level of the integration signal INT, the fourth switching component S4 is closed and the sampling capacitor C is closedSHThe voltage of the lower polar plate is a slope voltage end VRAMPVoltage of (2), assumed to be VRAMP. When the integration signal INT changes to the low level, the quantization signal AD changes to the low level, the second reset signal RST2 changes to the high level, the third switch element S3 is turned on, the fourth switch element S4 is turned off, and at the same time, the fifth switch element S5 is also turned on, so that the sampling capacitor C is turned onSHUpper plate voltage V ofINIs equal to the voltage V of the reference voltage terminalREFSampling capacitor CSHThe lower plate voltage is reset to a voltage V by a reset voltage terminal VRR. After which the second reset signal RST2 goes low while the sampling signal SH goes high, at which time the third switching elementS3 is opened, the second switch module S2 is closed, and the fifth switch module S5 is also closed because the sampling signal SH becomes high, and the sampling capacitor CSHLower plate and integrating capacitor CPIXThe upper polar plate is connected until the sampling signal SH changes into low level, the sampling is completed, and the sampling capacitor CSHFrom the lower plate voltage of VRBecomes VSH. I.e. the sampling capacitor CSHThe lower plate of (a) is the voltage that needs to be quantized.
When the sampling signal SH changes to the low level, the quantization signal AD changes to the high level, and at this time, the second switch element S2 is turned off, the fifth switch element S5 also turns off because both the sampling signal SH and the second reset signal RST2 change to the low level, and the fourth switch element S4 is turned on, so that the sampling capacitor C is turned onSHThe lower plate voltage of which is again from VSHBecomes VRAMPBased on the charge conservation characteristic of the capacitor, the voltage difference between the two ends of the capacitor is not changed, so when the capacitor C is sampledSHThe voltage value of the lower plate voltage is again from VSHBecomes VRAMPTime, sampling capacitor CSHUpper plate voltage V ofINWill be from VREFBecomes VREF+VRAMP-VSH。
With the quantization proceeding, the ramp voltage VRAMPWill gradually fall, sampling the capacitor CSHThe voltage value of the lower plate voltage is reduced, and then the sampling capacitor CSHUpper plate voltage V ofINThe voltage value will also decrease as the sampling capacitor CSHUpper plate voltage V ofINIs reduced to VREFThe comparator CMP will send an inversion and the output OUT will output a low level to the memory. Since at the beginning of the frame the integrating capacitor CPIXThe upper plate has a voltage of VRThen the photocurrent is measured at the integrating capacitor CPIXIs integrated to accumulate the voltage to be quantized as VSHI.e. essentially integrating the capacitance CPIXIs from VRBecomes VSHSo that the voltage that is actually finally quantized is VRAnd VSHA difference of (i.e. V)R-VSHAnd a point of time when the quantized signal AD changes to a high levelThe time length up to the time point when the comparator CMP is turned over is the digital quantity corresponding to the frame photocurrent, i.e. the digital quantity corresponding to the frame photocurrent of the pixel array. This duration is recorded by an n-bit counter and stored in a memory under the control of a write signal TRAN, and then output row by row to the column stage circuit 50 under the control of a row select signal RS.
Since a larger photocurrent will result in a lower V when the pixel circuit is operatedSHThen the signal V is actually quantizedR-VSHThe larger the quantization, the more proportional quantization is achieved. The n-bit counter records the quantization duration (i.e. the duration from the time point when the quantization signal AD changes to the high level to the time point when the comparator CMP flips), which is proportional to the amount of the quantized signal, so that the count result of the n-bit counter is the final quantization result.
And the flip voltage of the comparator CMP (i.e., the voltage at which the comparator CMP outputs a low level) is fixed to the reference voltage VREFTherefore, for the analog-to-digital conversion of each pixel, the delay time of the comparator CMP is fixed, so that the output deviation of the comparator CMP is substantially consistent when all pixels are subjected to the analog-to-digital conversion, and naturally, the output deviation can be directly removed as the background current, so that the linearity of the whole pixel circuit is higher, and the comparator CMP does not need to increase the power consumption of the comparator in the working process and only needs to normally work according to basic working characteristics, so that the pixel circuit has better practicability.
Based on the pixel circuit, an embodiment of the present invention further provides an infrared imaging system, where the infrared imaging system includes: an infrared detector and a plurality of pixel circuits as described above arranged according to the requirements of the pixel array.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A pixel circuit, the circuit comprising: the integrated circuit comprises an integration unit circuit, an analog-to-digital conversion unit circuit and a storage unit circuit;
the integration unit circuit receives photocurrent generated by the photoelectric detector, integrates the photocurrent and generates voltage needing to be quantized;
the analog-to-digital conversion unit circuit acquires the voltage to be quantized, quantizes the voltage to be quantized and generates a digital quantity corresponding to the photocurrent;
the storage unit circuit acquires and stores the digital quantity and outputs the digital quantity to the column-level circuit;
and the overturning voltage of the comparator in the analog-to-digital conversion unit circuit is fixed as the reference voltage.
2. The circuit of claim 1, wherein the integration cell circuit comprises: the device comprises a first switch component, an NMOS tube and an integrating capacitor;
the source electrode of the NMOS tube is connected with the photoelectric detector;
the grid electrode of the NMOS tube is connected with the signal control circuit;
the drain electrode of the NMOS tube is respectively connected with the first end of the first switch component, the first end of the integrating capacitor and the analog-to-digital conversion unit circuit;
the second end of the first switch component is connected with the reset voltage end;
and the second end of the integrating capacitor is grounded.
3. The circuit of claim 2, wherein the analog-to-digital conversion unit circuit comprises: the sampling circuit comprises a second switch component, a third switch component, a fourth switch component, a fifth switch component, a sampling capacitor and a comparator;
the first end of the second switch component is respectively connected with the drain electrode of the NMOS tube, the first end of the first switch component and the first end of the integrating capacitor;
the second end of the second switch component is respectively connected with the first end of the third switch component, the first end of the fourth switch component and the first end of the sampling capacitor;
a second terminal of the third switching component is connected with the reset voltage terminal;
the second end of the fourth switch component is connected with the slope voltage end;
the second end of the sampling capacitor is respectively connected with the inverting end of the comparator and the first end of the fifth switch component;
the in-phase end of the comparator is connected with the second end of the fifth switch component and the reference voltage end respectively;
the output end of the comparator is connected with the storage unit circuit.
4. The circuit of claim 3, wherein the memory cell circuit comprises: a memory;
the memory is respectively connected with the output end of the comparator, the output end of the n-bit counter and the column level circuit.
5. The circuit of claim 3, wherein the signal control circuit generates an integration signal, a first reset signal, a second reset signal, a sampling signal, a quantization signal;
the rising edge time point of the integration signal is the same as the rising edge time point of the first reset signal;
the falling edge time point of the integrated signal is the same as the rising edge time point of the second reset signal and the falling edge time point of the quantized signal;
the falling edge time point of the second reset signal is the same as the rising edge time point of the sampling signal;
the falling edge time point of the sampling signal is the same as the rising edge time point of the quantized signal.
6. The circuit of claim 5, wherein a high level holding time of the integrated signal is longer than a high level holding time of the first reset signal;
the low level maintaining time of the integration signal is greater than the sum of the high level maintaining time of the first reset signal and the high level maintaining time of the second reset signal;
the low level maintaining time of the integral signal is longer than that of the quantized signal;
the low level maintaining time of the quantized signal is equal to the sum of the high level maintaining time of the first reset signal and the high level maintaining time of the second reset signal.
7. The circuit of claim 5, wherein the NMOS transistor is turned on when the integrated signal is high;
when the integral signal is at a low level, the NMOS tube is switched on and off;
when the first reset signal is at a high level, the first switch component is closed;
when the first reset signal is at a low level, the first switch assembly is switched off;
when the sampling signal is at a high level, the second switch component is closed;
when the sampling signal is at a low level, the second switch component is switched off;
when the second reset signal is at a high level, the third switch component is closed;
when the second reset signal is at a low level, the third switch component is turned off;
when the quantized signal is at a high level, the fourth switch component is closed;
when the quantized signal is at a low level, the fourth switch component is turned off;
when any one of the sampling signal and the second reset signal is at a high level, the fifth switch component is closed;
and when the sampling signal and the second reset signal are both at a low level, the fifth switch component is switched off.
8. The circuit of claim 7, wherein when the first switch component is closed, the voltage of the integrating capacitor is the same as the voltage of the reset voltage terminal;
when the NMOS tube is conducted, the photocurrent is integrated on the integrating capacitor to generate the voltage to be quantized;
when the third switch component is closed, the voltage of the first end of the sampling capacitor is the same as the voltage of the reset voltage end;
when the second switch component is closed, the voltage to be quantized is sampled to the first end of the sampling capacitor;
when the fourth switch component is closed, the voltage of the first end of the sampling capacitor is changed from the voltage needing to be quantized to the ramp voltage, and the voltage of the second end of the sampling capacitor is changed from the voltage of the reference voltage end to:
after the voltage of the reference voltage end is summed with the ramp voltage, the sum is subtracted from the voltage needing to be quantized to obtain a difference value;
when the fourth switch component is closed, the voltage of the second end of the sampling capacitor decreases with the decrease of the ramp voltage, and when the voltage of the second end of the sampling capacitor decreases to be equal to the voltage of the reference voltage end, the comparator sends an inversion to output a low level.
9. The circuit of claim 1, wherein the actual quantized voltage magnitude is:
and performing difference between the voltage of the reset voltage end and the voltage needing to be quantized to obtain the size of the difference value.
10. An infrared imaging system, comprising: an infrared detector and a plurality of pixel circuits as claimed in any one of claims 1 to 9 arranged in accordance with the requirements of the pixel array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110014440.2A CN112866593B (en) | 2021-01-06 | 2021-01-06 | A pixel circuit and an infrared imaging system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110014440.2A CN112866593B (en) | 2021-01-06 | 2021-01-06 | A pixel circuit and an infrared imaging system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112866593A true CN112866593A (en) | 2021-05-28 |
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| CN114173073A (en) * | 2021-12-06 | 2022-03-11 | 锐芯微电子股份有限公司 | Circuit structure and working method thereof |
| CN114172517A (en) * | 2021-08-18 | 2022-03-11 | 北京大学 | Infrared reading circuit and analog-to-digital converter |
| CN114205542A (en) * | 2021-11-18 | 2022-03-18 | 北京领丰视芯科技有限责任公司 | Pixel-level circuit and infrared imager |
| CN114245040A (en) * | 2021-11-18 | 2022-03-25 | 北京领丰视芯科技有限责任公司 | Reading circuit and infrared imager |
| CN115037897A (en) * | 2022-06-06 | 2022-09-09 | 北京大学 | Pixel-level analog-to-digital conversion circuit, analog-to-digital converter and infrared detection equipment |
| CN115032447A (en) * | 2022-06-06 | 2022-09-09 | 北京大学 | Micro voltage difference quantization circuit with non-uniformity calibration function and sensing equipment |
| CN115086580A (en) * | 2022-07-18 | 2022-09-20 | 昆明钍晶科技有限公司 | Pixel-level analog-to-digital conversion digital reading circuit and infrared detector |
| CN117110692A (en) * | 2023-10-24 | 2023-11-24 | 武汉市聚芯微电子有限责任公司 | Current integrating circuit, photo-generated current reading circuit and chip |
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| CN114205542A (en) * | 2021-11-18 | 2022-03-18 | 北京领丰视芯科技有限责任公司 | Pixel-level circuit and infrared imager |
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| CN114205542B (en) * | 2021-11-18 | 2022-12-16 | 北京领丰视芯科技有限责任公司 | Pixel-level circuit and infrared imager |
| CN114173073A (en) * | 2021-12-06 | 2022-03-11 | 锐芯微电子股份有限公司 | Circuit structure and working method thereof |
| CN114173073B (en) * | 2021-12-06 | 2024-01-23 | 锐芯微电子股份有限公司 | Circuit structure and working method thereof |
| CN115037897A (en) * | 2022-06-06 | 2022-09-09 | 北京大学 | Pixel-level analog-to-digital conversion circuit, analog-to-digital converter and infrared detection equipment |
| CN115032447A (en) * | 2022-06-06 | 2022-09-09 | 北京大学 | Micro voltage difference quantization circuit with non-uniformity calibration function and sensing equipment |
| CN115032447B (en) * | 2022-06-06 | 2025-11-04 | 北京大学 | Miniature voltage difference quantization circuit and sensing device with non-uniformity calibration function |
| CN115037897B (en) * | 2022-06-06 | 2024-06-14 | 北京大学 | Pixel-level analog-to-digital conversion circuit, analog-to-digital converter and infrared detection equipment |
| CN115086580A (en) * | 2022-07-18 | 2022-09-20 | 昆明钍晶科技有限公司 | Pixel-level analog-to-digital conversion digital reading circuit and infrared detector |
| CN117110692B (en) * | 2023-10-24 | 2024-01-12 | 武汉市聚芯微电子有限责任公司 | Current integrating circuit, photo-generated current reading circuit and chip |
| CN117110692A (en) * | 2023-10-24 | 2023-11-24 | 武汉市聚芯微电子有限责任公司 | Current integrating circuit, photo-generated current reading circuit and chip |
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