CN113113473B - Field effect transistor structure and its manufacturing method, chip device - Google Patents

Field effect transistor structure and its manufacturing method, chip device Download PDF

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CN113113473B
CN113113473B CN202110502422.9A CN202110502422A CN113113473B CN 113113473 B CN113113473 B CN 113113473B CN 202110502422 A CN202110502422 A CN 202110502422A CN 113113473 B CN113113473 B CN 113113473B
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CN113113473A (en
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任炜强
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Shenzhen Zhenmaojia Semiconductor Co ltd
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    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
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    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
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    • H10W40/00—Arrangements for thermal protection or thermal control
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    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
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Abstract

本发明涉及一种场效晶体管结构及其制造方法、芯片装置，晶体管包括位于底部的漏极外延层、位于顶部的源极层以及嵌入于漏极外延层内的源极延伸倒鳍与栅极;栅极排列在源极延伸倒鳍之间,栅极两侧形成有成对由源极层至漏极外延层内部并联的对称型沟道;优选示例中,栅极两侧的沟道上方还形成有成对由源极层至漏极外延层并联的对称型领域电阻;优选示例中,漏极外延层在对应栅极的底部部位形成栅下浮空反极型结;优选示例中,漏极外延层在对应源极延伸倒鳍的底部部位形成屏蔽栅底部浮空反极型柱底结。本发明首创了双倒半鳍浮空超结栅式场效晶体管(DRFJ MOSFET)架构,具有衬底背面漏极与顶面源极电子流均匀化或帮助均匀化的增益效果。

Figure 202110502422

The invention relates to a field effect transistor structure, a manufacturing method and a chip device. The transistor includes a drain epitaxial layer at the bottom, a source layer at the top, and a source extension fin and a gate embedded in the drain epitaxial layer. ; The gate is arranged between the extended and inverted fins of the source, and a pair of symmetrical channels connected in parallel from the source layer to the drain epitaxial layer are formed on both sides of the gate; in a preferred example, above the channel on both sides of the gate Pairs of symmetrical field resistors connected in parallel from the source layer to the drain epitaxial layer are also formed; in a preferred example, the drain epitaxial layer forms a floating inversion junction under the gate at the bottom portion of the corresponding gate; in a preferred example, the drain The electrode epitaxial layer forms a floating inversion type post-bottom junction at the bottom of the shielded gate at the bottom portion of the inverted fin corresponding to the source extension. The invention initiates a double inverted half-fin floating super-junction gate field effect transistor (DRFJ MOSFET) structure, which has the gain effect of uniformizing or helping to uniformize the electron flow of the drain on the backside of the substrate and the source on the topside.

Figure 202110502422

Description

Field effect transistor structure, manufacturing method thereof and chip device
The priority basis of the present invention includes: application No. 202110414351.7, application date 2021.04.16, patent application entitled "field effect transistor structure and method of manufacturing the same, chip device".
Technical Field
The present invention relates to the field of semiconductor transistor technology, and more particularly, to a field effect transistor structure, a method for manufacturing the same, and a chip device.
Background
The field effect transistor structure is used as a key important device of a semiconductor chip, and various structures mainly comprise FinFET fin type field effect transistors, JFET junction type field effect transistors, surface field effect transistors, tunneling type field effect transistors, trench gate field effect transistors, split gate field effect transistors and super junction field effect transistors. The FinFET structure, JFET junction structure, surface field effect transistor structure, and tunneling field effect transistor structure all have source and drain contacts designed on the same surface of the semiconductor substrate, and as wafer thinning and device miniaturization trends develop, the problem of wafer backside leakage current is increasingly a difficult problem that needs to be faced and overcome. The JFET and the tunnel fet have serious leakage current problems due to the channel layer being designed in the active region of the semiconductor substrate, and the FinFET fin transistor has a channel layer designed on the protruding fin-shaped gate by additional deposition, which is relatively light in leakage current problems, but the device structure and process are relatively complicated. The channel layer of the FinFET fin transistor is formed by epitaxial surface of an oxide layer to form a single crystal structure which obviously does not have the channel layer formed in an in-situ mode, so the electrical property stability of the channel layer is not as good as that of a JFET junction field effect transistor, a surface field effect transistor and a tunneling field effect transistor. The limitation of silicon limit exists in a trench gate field effect transistor, so that the power density of a device which occupies a larger wafer area by the same on-resistance cannot be improved. Although the split gate field effect transistor and the super junction field effect transistor can break through the silicon limit, the process is complex and the process control window is narrow; in addition, the device is easy to have the phenomenon of poor current concentration reliability, so that the performance and the reliability of the device are difficult to be compatible.
Prior art FinFET fin transistors, found in CN103985712A, CN106981517A, CN106887461A, all have gate fins protruding from the substrate. JFET JFETs of the prior art can be found in CN1507070A, CN108257955A, have no gate protruding from the substrate and the channel layer is defined by a doped region pattern within the substrate. The prior art planar fet can be seen in CN107534060A, and has no gate protruding from the substrate, and the cell occupies a large surface area. In the prior art, the tunnel fet is shown in CN110797387A and CN110943121A, which are a variation of the FinFET fin transistor, two fin structures form an epitaxial layer in an epitaxial manner, the sidewalls of the fin structures cover and bury the gate layer, the gate function of the fin structures is changed into a channel function, and the tops of the two fin structures on the same surface are used as a source and a drain, respectively.
Disclosure of Invention
The invention mainly aims to provide a field effect transistor structure, and mainly aims to solve the problems of uneven source electronic current distribution, incompatible product performance and reliability and incompatible product performance and processing difficulty of a field effect transistor by using an innovative transistor architecture. The transistor architecture is named as Double inverted half fin Floating super Junction gate field effect transistor (DRFJ).
The present invention also provides a method for manufacturing a field effect transistor structure, which is used to manufacture a field effect transistor structure with uniform distribution of electron current at the electrode.
A third objective of the present invention is to provide a semiconductor chip device including a field effect transistor structure with DRFJ architecture.
The main purpose of the invention is realized by the following technical scheme:
a field effect transistor structure is proposed, comprising:
the drain electrode substrate is provided with a processing surface and a corresponding back surface, the processing surface is provided with first grooves which are parallel to each other, the inner walls of the first grooves are subjected to insulation processing, source electrode extension inverted fins are arranged in the first grooves, and the depth of the first grooves does not exceed the thickness of the drain electrode epitaxial layer;
the active layer is formed on the processing surface of the drain electrode epitaxial layer, a second groove is formed between the first grooves by the active layer, the inner wall of the second groove is subjected to insulation processing, a grid electrode is arranged in the second groove, and the second depth of the second groove is enough to penetrate through the active layer and smaller than the first depth of the first groove;
a third groove which is aligned with the first groove is formed by the inner dielectric layer, the inner wall of the third groove is not subjected to insulation treatment, and the width and the depth of the third groove are enough to directly expose the edge of the active layer and the bottom of the active layer to expose the top of the source electrode extension inverted fin;
and a source layer formed in the third trench to turn on the source extended inverted fin, wherein an inversion layer injection thickness direction of the active layer defines a channel length of the field effect transistor, instead of defining the channel length of the field effect transistor in a length direction of the active layer in the prior art, so as to provide a plurality of short-distance parallel transistor channels vertically oriented to the processing surface.
By adopting the technical scheme, the third groove which is aligned with the first groove is formed by the inner dielectric layer, the inner wall of the third groove is not subjected to insulation treatment, the width and the depth of the third groove are enough to directly expose the edge of the active layer on the side and expose the top of the source electrode extension inverted fin on the bottom, the bottom of the source electrode layer is connected with the source electrode extension inverted fin in a conduction mode, two sides of the source electrode layer are connected with the active layer in a conduction mode, the source electrode extension inverted fin has the function of an electron flow isolation gate, the source electrode layer conducts the active layer on two sides of the third groove, two side profiles of the gate insulation treatment along the active layer can be conducted to the drain electrode substrate, the channel length of the field effect transistor can be defined in the direction of the inversion layer injection thickness of the active layer, and particularly, a transistor channel can be planned on each side profile of the gate insulation treatment, because the grid embedding depth breaks through the active layer and reaches the interior of the drain electrode epitaxial layer, parallel channels which are vertical and parallel relative to the processing surface are formed on two sides of the embedded grid; the back of the drain substrate can be used as the contact of a drain pad, the movement of electron current is from the processing surface to the back of the drain epitaxial layer, the half gate of the channel at one side is opened after the processes of two-side shunting of the third groove and gate insulation processing, the source electrode extension inverted fins are distributed on the back surface of the drain electrode substrate under the field effect of the shunt and the isolation gate of the source electrode extension inverted fins, channels on two sides of two half-gate transistors under two adjacent source electrode shunts are conducted between the back surface of the drain electrode substrate and the source electrode extension inverted fins, the defect of leakage current on the back surface of the original substrate is converted into beneficial and meaningful drain electrode output, and the phenomenon that electron current such as fuse effect is concentrated in a local area on the back surface of the drain electrode substrate is avoided.
In addition, the source layer and the source extension inverted fin are separately designed and structurally conducted in the manufacturing process, the source layer only needs to be filled with the third groove with larger width in the process, the first groove with smaller width does not need to be filled, and the material selection of the source extension inverted fin has more freedom, so that the difficulty of filling the groove in the process filling hole is overcome, the thermal expansion adaptability of the drain epitaxial layer is improved, and the metal diffusion effect on the drain epitaxial layer is reduced.
The invention may in a preferred example be further configured to: the source layer is further formed on the inner dielectric layer, the active layer is formed by internalization of the processing surface of the drain epitaxial layer, and the width of the third groove is larger than that of the first groove.
By adopting the above preferred technical features, the source electrode layer further formed on the inner dielectric layer is utilized, and the source electrode layers in two adjacent third trenches are conducted on the inner dielectric layer to enlarge the source contact, and the inner dielectric layer electrically insulates the top of the gate electrode from the extended source electrode layer. The width of the third groove is larger than the width of the first groove, so that the top of the source electrode extension inverted fin is effectively opened at the bottom of the third groove, the third groove has the function of a contact hole, the defect that the source electrode layer and the source electrode extension inverted fin cannot be conducted due to the fact that the third groove is not aligned with the first groove is reduced, and finally the active layer and the drain electrode epitaxial layer have the same electric field potential in use. Preferably, a section where an inner sidewall of the third trench meets a bottom portion of the third trench is inclined to avoid excessive etching of a channel layer of the active layer when the third trench is formed.
The invention may in a preferred example be further configured to: the active layer is a multilayer structure comprising: the depth of the third groove enables the third groove to penetrate through the source electrode field layer and the current balance layer.
By adopting the preferable technical characteristics, the current balance layer is formed between the source electrode field layer and the channel layer by utilizing the multilayer structure of the active layer, the thickness of the current balance layer has resistance functions on two sides of the insulated gate electrode so as to provide a plurality of short-distance parallel resistors vertically arranged on the processing surface, and the parallel resistors are respectively connected between the corresponding parallel transistor channels and the source electrode field layer in a guide way, so that the burning of individual parallel transistor channels under larger electron flow is avoided, and the fuse effect is eliminated.
The invention may in a preferred example be further configured to: the bottom of the first groove is subjected to thick oxidation treatment, so that the insulation thickness of the first groove is larger at the bottom of the inner wall than at the side part of the inner wall.
By adopting the preferable technical characteristics, the insulation thickness of the first groove is larger at the bottom of the inner wall than at the side part of the inner wall, and the oxidation isolation stacking block is formed at the bottom of the inner wall of the first groove, so that the formation of electron tunneling between the bottom of the source extension inverted fin and the drain epitaxial layer is avoided, the avalanche breakdown resistance of the groove bottom and the gate oxide modification resistance of ion implantation in the post process are improved, the field effect at the bottom of the source extension inverted fin is reduced, and the shunt field effect of the shunt isolation gate is formed on two sides of the source extension inverted fin in the drain epitaxial layer.
The invention may in a preferred example be further configured to: and a deep implantation region is formed in the drain electrode epitaxial layer at a position corresponding to the bottom of the first groove so as to form a floating inverted-pole type bottom junction at the bottom of the shielding grid.
By adopting the preferable technical characteristics, the floating reverse pole type column bottom junction at the bottom of the shielding grid is utilized to be penetrated out from the bottom of the source electrode extension inverted fin, so that the charge balance of the floating reverse pole type column to the adjacent pole type column is increased, the depth of the first groove and the thickness of the bottom insulating layer can be reduced in the manufacturing process, and the filling formation of the source electrode extension inverted fin is facilitated.
The invention may in a preferred example be further configured to: and an implanted region is formed in the drain electrode epitaxial layer at the position corresponding to the bottom of the second groove to form a floating inverted-pole junction below the gate.
By adopting the preferable technical characteristics, the floating inverted-pole junction under the grid is penetrated out from the bottom of the grid, so that the bottom of the grid insulating layer is prevented from being damaged by a bottom concentrated electric field, the reliability of the grid insulating layer is improved, and the breakdown withstand voltage reduction caused by the concentration of the bottom grid oxide electric field is avoided.
The invention may in a preferred example be further configured to: by utilizing the electric field effect of the grid electrode, the electron flow from the source electrode layer is shunted by the side edge of the third groove and moves to the drain electrode substrate between the first grooves along one symmetrical side of the side wall outline of the second groove, and the drain electrode metal pad is uniformly arranged on the back surface of the drain electrode epitaxial layer or arranged on the back surface.
By adopting the preferable technical characteristics, the electron current is shunted from the top surface to the bottom surface at two sides of the third groove on the processing surface by utilizing the electric field effect of the grid electrode, and the separation between the first grooves of the drain electrode epitaxial layer is uniform.
The main purpose of the invention is realized by the following technical scheme:
a method for fabricating a field effect transistor structure is proposed, for fabricating a field effect transistor structure which may be combined according to any of the above-mentioned technical solutions, the method comprising:
providing a drain electrode substrate, wherein the drain electrode substrate is provided with a processing surface provided by a drain electrode epitaxial layer and a corresponding back surface, and first grooves which are parallel to each other are formed by etching the processing surface;
forming a first oxidation isolation layer in the processing surface and the first groove to enable the inner wall of the first groove to be subjected to insulation processing;
arranging a source extension inverted fin in the first groove in a deposition filling mode, and removing the source extension inverted fin and the part of the first oxidation isolation layer on the processing surface, wherein the depth of the first groove does not exceed the thickness of the drain electrode epitaxial layer;
etching the processing surface to form second grooves between the first grooves, wherein the second depth of the second grooves is smaller than the first depth of the first grooves;
forming a second oxidation isolation layer in the processing surface and the second groove to enable the inner wall of the second groove to be subjected to insulation processing;
arranging a grid in the second groove in a deposition filling mode;
forming an active layer under the processing surface of the drain electrode epitaxial layer in an energy injection mode, wherein the thickness and the depth of the active layer are within a range which can be penetrated by the second depth of the second groove;
forming an inner dielectric layer on the active layer and the grid electrode in a deposition covering mode, so that the grid electrode is of an embedded structure;
etching the inner dielectric layer to form a third groove aligned with the first groove, wherein the inner wall of the third groove is not subjected to insulation treatment, and the width and the depth of the third groove are enough to directly expose the edge of the active layer and expose the bottom of the active layer to expose the top of the source electrode extension inverted fin;
and forming a source layer in the third groove to conduct the source extension inverted fin, wherein the inversion layer of the active layer is injected in the thickness direction to define the channel length of the field effect transistor.
By adopting the technical scheme, the source extension inverted fin is prefabricated, the process difficulty of filling the source extension material in the groove of the drain epitaxial layer in the semiconductor manufacturing process is reduced, and the double inverted fin inter-half gate field effect transistor is finally manufactured.
The invention may in a preferred example be further configured to:
after the step of providing the drain substrate, further comprising: forming a floating-gate bottom inverted-pole type column bottom junction at the bottom of the shielding gate on the drain epitaxial layer at a position corresponding to the bottom of the first trench in an ion implantation mode, wherein the drain epitaxial layer is a conductive semiconductor wafer;
in the step of forming the first oxidation barrier layer, the method comprises: the method comprises the steps of forming a first oxidation isolation layer in a thermal oxidation or precipitation mode, forming a side wall protection layer in a first groove, anisotropically etching the side wall protection layer to form an opening at the bottom of the first groove, forming an oxidation isolation superposition block in the opening of the side wall protection layer, selectively etching and removing the side wall protection layer to expose the first oxidation isolation layer, wherein the thickness of the first oxidation isolation layer and the oxidation isolation superposition block at the bottom of the inner wall is larger than that of the first oxidation isolation layer at the side part of the inner wall;
in the step of arranging the source extension inverted fin, the method for removing the source extension inverted fin and the first oxidation isolation layer on the processing surface comprises chemical mechanical polishing or/and back etching;
in the step of forming the second trench, the preceding steps included are: preferably, after the second groove is formed, a gate-lower floating inverted-pole type junction is formed on the drain electrode epitaxial layer at a position corresponding to the bottom of the second groove in an ion implantation mode;
in the step of forming the second oxidation isolation layer, the second oxidation isolation layer is a gate oxide layer, the gate oxide layer is formed on the inner wall of the second groove and the processing surface in a thermal oxidation or thermal oxidation and deposition mode, and the method preferably further comprises the steps of forming a sacrificial gate oxide layer on the inner wall of the second groove before the gate oxide layer is formed, then removing the sacrificial gate oxide layer and cleaning the drain electrode epitaxial layer;
in the step of arranging the grid electrode, the method for removing the part of the grid electrode on the processing surface comprises chemical mechanical polishing or/and back etching;
in the step of forming the active layer, the active layer is formed by internalization of the processing surface of the drain electrode epitaxial layer, and comprises a channel layer positioned at the bottom, a current balance layer positioned on the channel layer and a source electrode field layer positioned on the current balance layer;
in the step of forming the third trench, the third trench is of an enlarged slot structure, an interval is maintained between the inner wall of the third trench and the inner wall of the second trench, the width of the third trench is greater than that of the first trench, and the depth of the third trench is smaller than the overall thickness of the active layer and greater than the sum of the thicknesses of the current balance layer and the source region layer;
and after the step of forming the source electrode layer, carrying out crystal back thinning and crystal back metallization on the back surface of the drain electrode epitaxial layer.
The corresponding technical effects as described above can be achieved by using the above-described corresponding features by adopting the above-described preferred technical features.
The main purpose of the invention is realized by the following technical scheme:
a semiconductor chip arrangement is proposed, comprising: the field effect transistor structure that may be combined according to any of the above-mentioned embodiments, or the field effect transistor structure used includes: the semiconductor device comprises a drain electrode epitaxial layer positioned below a processing surface, a source electrode layer positioned on the processing surface, and a source electrode extension inverted fin and a grid electrode embedded in the drain electrode epitaxial layer; the gate is arranged between the source extension inverted fins, symmetrical channels which are connected in parallel from the source electrode layer to the inside of the drain electrode epitaxial layer are formed on two sides of the grid electrode; preferably, the first and second liquid crystal materials are, symmetrical domain resistors connected in parallel from the source electrode layer to the drain electrode epitaxial layer are further formed above the channels on the two sides of the grid electrode; preferably, the first and second liquid crystal materials are, the drain electrode epitaxial layer forms a floating-under-gate inverted-pole junction at the bottom part corresponding to the grid electrode; in a preferred embodiment of the method of the invention, and the drain electrode epitaxial layer forms a shield grid bottom floating inverted pole type column bottom junction at the position corresponding to the bottom of the source electrode extension inverted fin.
By adopting the technical scheme, a plurality of vertical parallel channels defined in the thickness direction of the active layer are established by utilizing the source layer positioned on the processing surface and the grid embedded in the drain epitaxial layer, and the electron current can be uniformly output (or input) on the back surface. When the semiconductor chip device is arranged on the carrier plate, the drain contact connection is completed, the connection operation of an electrode position can be saved, and the problem of the leakage current on the back surface of the chip does not need to be considered along with the fact that the chip is thinner and thinner.
In summary, the present invention includes at least one of the following technical effects that contribute to the prior art:
1. a groove-shaped contact hole like a third groove is formed in the isolation gate (particularly the source electrode extending inverted fin) where the first groove is located for filling of the source electrode layer, and one or more effects of the following effects are achieved: a. the third groove serving as the contact hole is positioned above the source electrode extended inverted fin serving as the isolation grid, and compared with a structure in which the contact hole is arranged between the isolation grids, the contact hole area of the third groove can be increased, so that the heat dissipation performance and the current performance of the device are improved, and simultaneously, the SOA (safe operating area) can be correspondingly improved by more than 10%; b. the third groove serving as the contact hole is arranged on the source electrode extension inverted fin serving as the shunt isolation gate, the size of the contact hole is kept, meanwhile, the distance between the third groove and the gate can be increased, the safety margin in the manufacturing process can be further increased, and the processing yield can be increased; c. compared with a planar contact hole generally designed in the prior art, the reliability of the UIS (Unclamped Inductive Switching) of the device can be improved by the third trench serving as the contact hole; d. the contact hole is helped to extend the inverted fin short circuit in the source electrode of the whole isolation gate area to be connected with the source electrode of the device, compared with the original structure that only part of the area is short-circuited with the source electrode, the shielding gate of the whole device can simultaneously achieve charge balance without time delay among areas, and therefore the UIS of the device can be improved by more than 20%;
2. technical effects of the current balance layer with respect to the multi-layered structure active layer in configuration include: a. the addition of the layer is equivalent to that a resistor is introduced into each half-gate transistor corresponding to the source electrode in an equivalent circuit, so that the current of each transistor unit can be balanced, and the uniform and reliable temperature rise of the device can be increased; b. the reliability of parallel application of the device is improved;
3. technical effects on the configuration of the thick oxidation of the bottom of the isolation gate include: the thickness of a thermal oxidation layer at the bottom corner of the first trench is only 60-70% of the side wall due to different lattice structures, so that when an in-vivo field plate charge balance device is reversely blocked, an electric field is completely concentrated at the bottom of the isolation gate and a PN junction region, the addition of the oxidation isolation superposition block and the isolation gate floating counter region (such as a P region of an N-type field effect tube) is beneficial to further improving the bottom electric field, and the reliability of bottom thermal oxidation can be improved by introducing thick oxygen of the isolation gate;
4. the technical effects of the floating inverted-pole bottom junction (specifically, the floating P column at the bottom of the isolation gate of the N-type field effect transistor) in configuration include: a. the introduction of a charge balance area into the column bottom junction and the matching of a bulk field plate structure can realize the charge balance of EPI together, and can obtain better device performance when the same blocking voltage is realized; the growth test and ion implantation times of the epitaxial layer can be reduced relative to a complete isolation gate structure only with a groove;
5. the technical effects on the configuration of the floating-under-gate inverted junction (specifically, the floating-under-gate P region of the N-type field effect transistor) include: a. the grid oxygen reliability is improved, the electric field is totally concentrated at the bottom of the grid electrode and a PN junction area during reverse blocking, in order to reduce the probability that the Miller capacitor PN junction is closer to the bottom of the grid oxygen, but the closer the grid oxygen electric field is, the stronger the grid oxygen electric field is, the reliability of the device is influenced, and the breakdown characteristic is reduced; b. the UIS performance is improved, the electric field concentration at the bottom of the grid during UIS causes breakdown to influence the UIS, and the introduction of the floating-down reverse-pole junction under the grid reduces the electric field intensity and increases the UIS performance; C. the Miller capacitance is reduced.
Drawings
FIG. 1 is a partial cross-sectional gate structure of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 2 is a schematic view of a drain substrate provided in the process of fabricating a field effect transistor structure according to some preferred embodiments of the invention;
FIG. 3 is a schematic diagram illustrating the formation of first trenches parallel to each other by etching from the processing surface of the drain epitaxial layer during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
fig. 4 is a schematic diagram illustrating the formation of a floating bottom-gate type bottom-pillar junction at the bottom of a first trench by ion implantation in the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 5 is a schematic illustration showing the formation of a first oxide isolation layer on the processing surface and within the first trench during the fabrication of a field effect transistor structure in accordance with some preferred embodiments of the present invention;
fig. 6 is a schematic diagram illustrating the formation of a source-extended inverted fin in a first trench during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
fig. 7 is a schematic view illustrating the removal of the source-extended fin and the first oxide isolation layer from the surface of the process during the fabrication of the fet structure according to some preferred embodiments of the present invention;
FIG. 8 is a schematic illustration showing the formation of a mask layer on a processing surface during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 9 is a schematic diagram illustrating a second trench etched from the processing surface and forming a floating-gate inversion junction at the bottom of the second trench during the fabrication of a field effect transistor structure according to some preferred embodiments of the invention;
FIG. 10 is a schematic view of forming a second oxide isolation layer in the processing surface and in the second trench during the process of fabricating a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 11 is a schematic diagram illustrating the placement of a gate in a second trench during the fabrication of a field effect transistor structure according to some preferred embodiments of the invention;
FIG. 12 is a schematic diagram illustrating the formation of an active layer by energy implantation under a processing surface during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 13 is a schematic diagram illustrating the separation of an active layer into a channel layer and a field layer during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 14 is a schematic diagram illustrating a field layer region being divided into a current balance layer and a source field layer during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 15 is a schematic illustration showing the formation of an inter-dielectric layer over the active layer and over the gate during the fabrication of a field effect transistor structure according to some preferred embodiments of the present invention;
FIG. 16 illustrates a third trench etched from the IMD layer during the formation of a FET structure according to some preferred embodiments of the present invention;
FIG. 17 is a schematic illustration showing the formation of a source layer in the third trench during the fabrication of a field effect transistor structure according to some preferred embodiments of the invention;
FIG. 18 is a schematic diagram illustrating the flow of electrons during the in-use state of a field effect transistor structure fabricated in accordance with some preferred embodiments of the present invention;
FIG. 19 is a partial cross-sectional gate structure of a field effect transistor structure according to a first variation of the present invention;
FIG. 20 is a partial cross-sectional gate structure of a field effect transistor structure according to a second variation of the present invention;
fig. 21 is a partial structure diagram of a field effect transistor structure in a cross gate structure according to a third variation of the present invention.
Reference numeral 1, a drain substrate, 10, a drain epitaxial layer, 11, a processed surface, 12, a back surface, 13, a first groove, 14, a surface acidizing film, 15, a body region, 16, a drain metal pad, 17, a doping concentration clear change horizontal plane, 20, a source extension inverted fin, 30, an active layer, 31, a second groove, 32, a channel layer, 33, a current balance layer, 34, a source field layer, 40, a grid, 41, a mask layer, 50, an inner dielectric layer, 51, a third groove, 60, a source layer, 70, a floating-down-counter-type bottom pillar junction, 80, a floating-down-gate-down-counter-type junction, 91, a first oxidation isolation layer, 92, a second oxidation isolation layer, 93 and an oxidation isolation stacking block.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of embodiments for understanding the inventive concept of the present invention, and do not represent all embodiments, nor do they explain only embodiments. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention under the understanding of the inventive concept of the present invention are within the protection scope of the present invention.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture, and if the specific posture is changed, the directional indications are changed accordingly. In order to facilitate understanding of the technical solutions of the present invention, the field effect transistor structure, the manufacturing method thereof, and the chip apparatus of the present invention are described and explained in further detail below, but the scope of the present invention is not limited thereto. In the following embodiments, N-channel transistors are used, and may be modified to P-channel transistors in different variations, and it should be understood by those skilled in the art that the source and drain referred to in the description are relative concepts and not absolute concepts, and in specific applications of the variations, the source referred to in the description may be used as a drain connection, the drain referred to in the description may be used as a source connection, the source referred to in the description may be used as a source connection, the drain referred to in the description may be necessarily used as a drain connection, the source referred to in the description may be used as a drain connection, and the drain referred to in the description may be necessarily used as a source connection. For the convenience of understanding the technical solution of the present application, the specification and the protection scope still use "source" and "drain", and are not limited to the source and the drain actually, but use a first electrode and a second electrode representing two different potential electrodes. In addition, the term "counter electrode" as used herein means an electrode opposite to a base electrode, and for example, if the base electrode of a source/drain electrode is N-type, the counter electrode is P-type, and vice versa.
Fig. 1 is a partial cross-sectional gate structure of a field effect transistor structure according to some preferred embodiments of the present invention, fig. 2 to 17 are respective process steps of a field effect transistor structure according to some preferred embodiments of the present invention, and fig. 18 is a schematic in-use state of a field effect transistor structure according to some preferred embodiments of the present invention. The accompanying drawings illustrate various embodiments having a common component, and the various embodiments having differences or differences will be described with particularity. Therefore, based on the industrial characteristics and technical essence, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features or any combination of a plurality of the technical features described below can be characterized in the same embodiment or whether a plurality of technical features mutually exclusive can be respectively characterized in different variant embodiments.
Referring to fig. 1, a field effect transistor structure disclosed in the present embodiment of the invention mainly includes a drain substrate 1, a source extended fin 20, an active layer 30, a gate 40 and a source layer 60, so as to realize the basic functions of an electron current switch of the field effect transistor. The present embodiment is represented by an N-channel transistor, and those skilled in the art should be able to adjust the transistor to a P-channel transistor in the variation.
The drain substrate 1 is provided with a processing surface 11 and a corresponding back surface 12, wherein the processing surface 11 is provided with first grooves 13 which are parallel to each other, the inner walls of the first grooves 13 are subjected to insulation processing, source extension inverted fins 20 are arranged in the first grooves 13, and the depth of the first grooves 13 does not exceed the thickness of the drain epitaxial layer 10. The drain substrate 1 is a semiconductor wafer in a semiconductor process, a singulated die foundation layer in a product, a foundation material of the drain substrate 1 is usually silicon, or silicon carbide, III-V or II-VI compound, and has conductivity after being doped with an electron-providing substance or a hole-providing substance, and a doped region is in an active region of the die, either overall or in bulk, for example, heavy N-type doping. The drain substrate 1 is typically of a monocrystalline structure, in the case of an N-type transistor, N + monocrystalline silicon. The drain epitaxial layer 10 is a functional layer epitaxially grown from the drain substrate 1, and generally has the same crystal orientation as the drain substrate 1, and is also a single crystal structure, and is lower in conductivity than the drain substrate 1 in the case of an N-type transistor, specifically, N-single crystal silicon. One function of the drain epitaxial layer 10 is to provide a level of sharp variation in doping concentration between the drain epitaxial layer 10 and the drain substrate 1 to facilitate semiconductor fabrication of the vertical channel field effect transistor. The processing surface 11 is a processing surface of a semiconductor process, and the back surface 12 is a surface opposite to the processing surface 11. The first trenches 13 are formed by the processed surface 11, meaning that the first trenches 13 open towards the processed surface 11, the bottom of the first trenches 13 is towards the back surface 12, and the first trenches 13 do not penetrate the drain epitaxial layer 10. Although only two first grooves 13 are shown in the figure, the number of the grooves can be adjusted, the structure in fig. 1 can be properly and repeatedly expanded on the left and right sides, and the preferable groove shape is a plurality of parallel straight strips on the processing surface 111, but can also be various curved shapes with the same interval in parallel. The upper source-extended fin 20 is used to maintain the same field voltage as the source, the source-extended fin 20 is conductive, preferably polycrystalline conductive silicon or other conductive semiconductor material, which has the same or similar thermal expansion compatibility with the drain epitaxial layer 10, and in other examples, may also be conductive material used in semiconductor processing, such as: tungsten, copper, aluminum, tungsten is commonly used. The source extension inverted fin 20 may have a single-layer structure as shown in fig. 1 or a multi-layer stacked structure.
An active layer 30 is formed on the processing surface 11 of the drain epitaxial layer 10, a second groove 31 is formed between the first grooves 13 by the active layer 30, the inner wall of the second groove 31 is processed in an insulation mode, a gate 40 is arranged in the second groove 31, and the second depth of the second groove 31 is enough to penetrate through the active layer 30 and is smaller than the first depth of the first groove 13. A portion of the active layer 30 (the channel layer) is turned on and off by the electric field of the gate electrode 40 to form a flow of electrons. In the preferred embodiment, the active layer 30 is formed internally by the drain epitaxial layer 10, for example, by performing a counter-type ion implantation or further including a homopolar ion implantation on the drain epitaxial layer 10, and the active layer 30 and the drain epitaxial layer 10 have an integrally adapted lattice structure, and in a variation, the active layer 30 is epitaxially grown from the surface of the drain epitaxial layer 10, so that the active layer 30 can be formed in the processing surface 11 and also on the processing surface 11. The bottom of the second trench 31 is higher than the bottom of the first trench 13, i.e., the bottom of the second trench 31 is closer to the processing surface 11 than the first trench 13. The gate 40 is shaped on the processing surface 11 to conform to the source extension fin 20 to maintain the same spacing between the two. The gate 40 is conductive, preferably polycrystalline conductive silicon or other conductive semiconductor material, and has the same or similar thermal expansion compatibility with the drain epitaxial layer 10, and other conductive materials used in semiconductor processing, such as: tungsten, copper, aluminum, tungsten is commonly used. The structure of the gate electrode 40 may be a single layer structure as shown in fig. 1 or a multi-layer stacked structure. For example, the bottom of the gate 40 is a downward protruding arc-shaped section, and the bottom of the source extended inverted fin 20 is an upward middle concave section, specifically, the bottom of the second oxide isolation layer 92 and the bottom of the first oxide isolation layer 91 plus the oxide isolation stacking block 93 are combined to form the structure, which has the following functions: the electric field intensity and the tolerance to the electric field of the bottom insulating layer are improved. For another example, the dimension of the floating inversion type bottom stud junction 70 corresponding to the width of the trench can be larger than the dimension of the floating inversion type bottom stud junction 80 under the gate corresponding to the width of the trench, so that the width of the floating inversion type bottom stud junction 70 can exceed the width of the first trench 13.
The inner dielectric layer 50 is formed on the active layer 30 and the gate 40, so that the gate 40 is an embedded structure, a third trench 51 aligned with the first trench 13 is formed by the inner dielectric layer 50, the inner wall of the third trench 51 is not subjected to insulation treatment, and the width and depth of the third trench 51 are sufficient to directly expose the edge of the active layer 30 and the bottom of the third trench to expose the top of the source extended inverted fin 20. The inter-dielectric layer 50 is insulating and separates the gate electrode 40 from the source electrode layer 60, and the material of the inter-dielectric layer 50 may be PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass), and the liquid coating method thereof ensures the thickness of the inter-dielectric layer 50, so as to effectively separate the source electrode from the gate electrode. Although only one inner dielectric layer 50 is illustrated, it may be a multi-layered stacked insulating structure in various variations. The third trench 51 serves as a contact hole connection for electrically connecting the source extended flip-chip 20 and the source layer 60 or/and the field layer electrically connecting the active layer 30 and the source layer 60, the width of the contact hole (the width of the third trench 51) should be larger than the width of the first trench 13 to enlarge the contact area, and the depth of the third trench 51 cannot damage or penetrate the active layer 30 to avoid the electrical short circuit between the source and the drain. The embedded gate 40 can be electrically pulled out of the embedded region by its own end extension or connecting lead, or the gate connecting line can be pulled out by a conductive plug penetrating the inter-dielectric layer 50 outside the source region, so that the field potential of the gate 40 can be adjusted independently.
A source layer 60 is formed in the third trench 51 to turn on the source-extended inverted fin 20, and the inversion layer injection thickness direction of the active layer 30 defines the channel length of the fet, instead of defining the channel length of the fet in the length direction of the active layer 30 as in the prior art, to provide multiple, short-distance, parallel transistor channels standing on the processing surface 11. In this embodiment, the source layer 60 covers the entire surface of the cell region on the processing surface 11 and fills the third trench 51, and the source layer 60 conducts the field layer of the active layer 30 in addition to the source extension fin 20. The source layer 60 is preferably made of aluminum or other conductive metal material, and may additionally have a metal pad function to omit the metal pad, and in other examples, the source layer 60 may be made of other conductive materials used in semiconductor processes, such as: tungsten, copper, polycrystalline conductive silicon. The structure of the source layer 60 may be a single layer structure as shown in fig. 1 or a stacked-layer structure. The thickness direction of the inversion layer injection is specifically the thickness direction of the communication layer 32.
The basic principle of the embodiment is as follows: by forming the third trench 51 aligned with the first trench 13 from the inner dielectric layer 50, the inner wall of the third trench 51 is not insulated, the width and depth of the third trench 51 are sufficient to directly expose the edge of the active layer 30 and the bottom of the third trench to expose the top of the source-extended flip-fin 20, so that the bottom of the source layer 60 is connected to the source-extended flip-fin 20 and both sides of the source layer 60 are connected to the active layer 30, so that the source-extended flip-fin 20 has the function of an electron flow isolation gate, the source layer 60 is connected to the active layer 30 at both sides of the third trench 51, the active layer 30 can be connected to the drain epitaxial layer 10 along both side profiles of the gate 40 insulated from the active layer 30, so that the channel length of the field effect transistor can be defined in the direction of the reverse injection thickness of the active layer 30, specifically, each side profile of the gate 40 insulated from the active layer can define a transistor channel, because the gate 40 is embedded deeply to reach the inside of the drain epitaxial layer 10 through the active layer 30, parallel channels which are vertical and parallel to the processing surface 11 are formed on two sides of the embedded gate 40, and the back surface 12 of the drain substrate 1 can be used as a contact of a drain metal pad, the movement of electron current is from the processing surface 11 to the back surface 12 of the drain substrate 1, in the process, the half gate 40 of one side channel is switched on through the shunting on two sides of the third groove 51 and the insulation processing of the gate 40, and is dispersed on the back surface 12 of the drain substrate 1 under the field effect of the shunting and isolating gate of the source extension inverted fin 20, so that the two side channels of two half gate transistors under two adjacent source branches are switched between the back surface 12 of the drain substrate 1 and the source extension inverted fin 20, and the defect of the leakage current of the original substrate back surface 12 is converted into beneficial and meaningful drain output, and concentration of electron flow, such as a fuse effect, to a local area of the back surface 12 of the drain substrate 1 is avoided.
Therefore, the circuit structure of the field effect transistor of the present application is to provide two half-gate channel structures (corresponding to the thickness of the channel layer 32 of the active layer 30 along each side of the gate 40) between two shunt isolation gates (corresponding to the source extended inverted fin 20), the source layer 60 shunts on the shunt isolation gates, the shunted electron flow is collected in the drain epitaxial layer 10 through the respective half-gate channel structures together with the adjacent shunt electron flow, and is uniformly distributed on the back surface of the drain substrate 1, for example, the electron flow a passing through the left third trench 51 reaches the left side of the middle half-gate by a/2, the electron flow B reaching the right third trench 51 at the right side reaches the right side of the middle half-gate by B/2, the electron flow reaching the back surface 12 of the drain substrate 1 between the corresponding left and right third trenches 51 is a/2 plus B/2, the back surface electron flow between the other adjacent third trenches 51 is B/2 plus C/2, c is the electron current flux of the third trench 51 on the next adjacent side, so that the uniformity of the electron current on the back surface is realized, and the back leakage current is no longer a technical problem.
In addition, by utilizing the separate design and structural conduction in the process of manufacturing the source layer 60 and the source extension inverted fin 20, the source layer 60 only needs to fill the third trench 51 with a larger width in the process, and does not need to fill the first trench 13 with a smaller width, and the material selection of the source extension inverted fin 20 has more freedom, so as to overcome the difficulty of filling the trench in the process, improve the thermal expansion adaptability with the drain epitaxial layer 10, and reduce the metal diffusion effect on the drain epitaxial layer 10.
Regarding the embodiment of the source layer 60 and the third trench 51 for filling the source layer, in a preferred embodiment, the source layer 60 is further formed on the inter-layer dielectric layer 50, and the width of the third trench 51 is greater than the width of the first trench 13. The source layers 60 in adjacent two third trenches 51 are conducted to each other on the inner dielectric layer 50 by the source layers 60 further formed on the inner dielectric layer 50 to enlarge the source contact, and the inner dielectric layer 50 electrically insulates the top of the gate 40 from the extended source layers 60. By utilizing the width of the third trench 51 being greater than the width of the first trench 13, the top of the source extended inverse fin 20 is effectively opened at the bottom of the third trench 51, and the third trench 51 has a contact hole function, so as to reduce the defect that the source layer 60 and the source extended inverse fin 20 cannot be conducted due to the misalignment of the third trench 51 with respect to the first trench 13, and finally achieve the purpose that the two have the same electric field potential in use. In another variation, the width of the third trench 51 may be smaller than that of the first trench 13, and the conduction between the source layer 60 and the source extended reversed fin 20 can be achieved only by connecting the smaller-width third trench 51 in a plurality of contact holes with enlarged apertures in a partial region, except that the process is difficult to implement. In an example, the width of the first trench 13 is 0.2-3.0 um, the width of the second trench 31 is 0.21-4.0 um, and the width of the third trench 51 is 0.2-0.7 um. The height of the bottom of the second trench 31 is between the height of the bottom of the first trench 13 and the height of the bottom of the third trench 51. in an example, the height of the bottom of the second trench 31 is different from the height of the bottom of the first trench 13, and the depth of the first trench 13 from the processing surface 11 is between 1.5 and 10 um.
Regarding the embodiment of the active layer 30, the active layer 30 is formed by internalization from the processed surface 11 of the drain epitaxial layer 10, so that the lattice matching between the active layer 30 and the drain epitaxial layer 10 is realized, the defect of interface gap is avoided, the channel structure of the transistor and the drain epitaxial layer 10 are integrated into a whole structure, and the electric performance stability of the transistor is superior to that of an epitaxially grown active layer or channel layer. Preferably, a section where an inner sidewall of the third trench 51 meets a bottom portion is inclined to avoid excessive etching to the channel layer 32 of the active layer 30 when the third trench 51 is formed. In another variation, the active layer 30 may be epitaxially formed, and the channel layer formed by either the intrinsic or the epitaxial method has a single crystal structure, and the channel performance is stable, but the channel layer formed by the intrinsic drain epitaxial layer 10 has a better lattice matching degree with the drain epitaxial layer 10. In an example, the thickness of the active layer 30 is 0.5-3 um.
As to further details of the active layer 30, in a preferred example, the active layer 30 is a multilayer structure including: a channel layer 32 at the bottom, a current balance layer 33 on the channel layer 32, and a source domain layer 34 on the current balance layer 33, wherein the third trench 51 has a depth such that the third trench 51 penetrates the source domain layer 34 and the current balance layer 33. In the multi-layer structure of the active layer 30, the current balance layer 33 is formed between the source region layer 34 and the channel layer 32, and the thickness of the current balance layer 33 has resistance effects on both sides of the gate 40 after the insulation treatment, so as to provide a plurality of short-distance parallel resistors standing on the treatment surface 11, which are respectively connected between the corresponding parallel transistor channels and the source region layer 34 in a conductive manner, thereby avoiding the burning of the respective parallel transistor channels under a larger electron current, and eliminating the fuse effect. In an exemplary structure of an N-type transistor, the channel layer 32 is a P-type doped region, the current balance layer 33 and the source domain layer 34 are N-type doped regions, wherein the current balance layer 33 is lower than the source domain layer 34 with respect to N-type doping concentration, i.e., the current balance layer 33 is lightly N-type doped, the source domain layer 34 is heavily N-type doped, so the resistance of the current balance layer 33 is higher than the resistance of the source domain layer 34, and the source domain layer 34 tends to be conductive. While the P-type dopant species of the channel layer 32 may specifically be boron (B), the channeling of the channel layer 32 occurs in a thickness direction, rather than in a surface direction that is the same as or parallel to the processing surface 11. In another variation, the active layer 30 may include only: a channel layer 32 at the bottom, a source domain layer 34 on the channel layer 32. In an example, the thickness of the channel layer 32 is 0.1-2 um, the thickness of the current balance layer 33 is 0.05-1 um, and the thickness of the source region layer 34 is 0.05-1 um.
Regarding the insulation embodiment of the first trench 13, in a preferred example, the bottom of the first trench 13 is subjected to a thick oxidation process, so that the insulation thickness of the first trench 13 is greater at the bottom of the inner wall than at the side of the inner wall. By utilizing the fact that the insulation thickness of the first trench 13 is greater at the bottom of the inner wall than at the side of the inner wall, the oxidation isolation stacking block 93 is formed at the bottom of the inner wall of the first trench 13, thereby avoiding the formation of electron tunneling between the bottom of the source extension inverted fin 20 and the drain epitaxial layer 10, improving the slot bottom avalanche breakdown resistance and the gate oxide modification resistance of ion implantation in the post-process, and simultaneously reducing the field effect at the bottom of the source extension inverted fin 20, so that the shunt field effect of the shunt isolation gate is formed on two sides of the source extension inverted fin 20 in the drain epitaxial layer 10. In an example, the thickness of the first oxide isolation layer 91 on the sidewall of the first trench 13 is between 700 to 13000A, the combined thickness of the first oxide isolation layer 91 on the bottom of the first trench 13 and the oxide isolation stacking block 93 is between 1000 to 18000A, and the thickness of the second oxide isolation layer 92 on the second trench 31 is between 300 to 1300A.
In a specific embodiment of the drain epitaxial layer 10, in a preferred example, the drain epitaxial layer 10 is further formed with a deep implanted region at a position corresponding to the bottom of the first trench 13 to form a shield gate bottom floating inversion type bottom pillar junction 70. The floating inverted-pole type bottom junction 70 at the bottom of the shielding gate is exposed from the bottom of the source extension inverted-fin 20, so that the charge balance of the floating inverted-pole type column to the adjacent inverted-pole type column is increased, the phenomenon that electron currents between the source extension inverted-fins 20 in different regions are collected in advance is avoided, the depth of the first groove 13 can be reduced in manufacturing, the thickness of a bottom insulating layer can also be reduced, and the filling formation of the source extension inverted-fin 20 is facilitated. In the example, the reverse-polarity bottom-pillar junction 70 is P-type doped, and the reverse-polarity bottom-pillar junction 70 is used for improving the shunting isolation effect of the source extension inverted fin 20 and preventing the electron current from being collected in the drain epitaxial layer 10 in advance, so that the groove depth of the first trench 13 can be reduced under the same performance, and the filling difficulty of the source extension inverted fin 20 in the groove filling process is reduced. In an example, the bottom depth of the reverse-pole bottom-column junction 70 does not exceed the thickness of the drain epitaxial layer 10, so that the drain epitaxial layer 10 is not completely blocked by the reverse-pole bottom-column junction 70 between the first trenches 13, a reverse-pole doping substance cannot enter the drain substrate 1, and the existence of the horizontal plane 17 with clear change of doping concentration in a figure is maintained in the manufacturing process, so that the vertical channel field effect transistor has better product stability.
In another embodiment of the drain epitaxial layer 10 that can be used in parallel or simultaneously, in a preferred example, the drain epitaxial layer 10 is further formed with an implanted region at a position corresponding to the bottom of the second trench 31 to form an under-gate floating-inversion junction 80. The floating under-gate reverse-pole junction 80 is penetrated out from the bottom of the gate 40, so that the bottom of the gate insulating layer is prevented from being damaged by a bottom concentrated electric field, the reliability of the gate insulating layer is improved, and the breakdown withstand voltage reduction caused by the concentration of the bottom gate oxide electric field is avoided. The electron current on one side of the insulated side of the gate 40 climbs and returns to the other side of the insulated side of the gate 40 along the bottom contour of the gate 40, and both sides of the insulated side of the gate 40 can enter the drain epitaxial layer 10. In the example, the under-gate floating-cathode junction 80 is doped P-type, so that the drain epitaxial layer 10 forms a resistive effect under the gate 40, and the under-gate floating-cathode junction 80 can be adjusted to have a non-channel function based on the adjustment of the P-type doping concentration or/and the N-type and P-type mixed doping.
In a preferred example, by utilizing the electric field effect of the gate 40, the electron flow from the source layer 60 is shunted by the side of the third trench 51 to the drain epitaxial layer 10 moving between the first trenches 13 along one of the symmetrical sides of the sidewall profile of the second trench 31, and is uniform at the back surface 12 of the drain epitaxial layer 10 or a drain metal pad disposed at the back surface 12. By means of the electric field effect of the gate 40, a uniform separation of the electron flow is achieved from the top to the bottom side, shunting across the third trenches 51 on the treatment surface 11 and between the first trenches 13 of the drain epitaxial layer 10.
In addition, referring to fig. 2 to 17, another embodiment of the present invention further provides a method for manufacturing a field effect transistor structure, which is used for manufacturing a field effect transistor structure combined by any of the above-mentioned technical solutions, and the process steps are described as follows.
Referring first to fig. 2, a drain substrate 1 having a processed surface 11 provided by a drain epitaxial layer 10 and a corresponding back surface 12 is provided, corresponding to step S2, in which the drain substrate 1 is typically in the form of a wafer, specifically a silicon wafer. A surface acidizing film 14 is formed on the treated surface 11 of the drain epitaxial layer 10, and has the function of a hard mask so as to facilitate the formation of the first trench 13 in the later process. In the example, the drain substrate 1 with the drain epitaxial layer 10 is specifically an EPI wafer, the base layer of the drain substrate 1 is specifically a silicon substrate, i.e. the body region 15 in fig. 2, the epitaxial structure is epitaxially grown above the body region 15 to the processing surface 11, i.e. the drain epitaxial layer 10, so that the drain epitaxial layer 10 is functionally conductive as an epitaxial structure portion between the processing surface 11 and the back surface 12 and has the same single crystal structure and crystal orientation as the silicon substrate wafer, and the body region 15 is conductive of a semiconductor material. In an NFET structure, the body region 15 is specifically N + single crystal silicon and the drain epitaxial layer 10 is specifically N-single crystal silicon. A doping concentration sharp variation horizontal plane 17 is formed between the body region 15 and the drain epitaxial layer 10 and is parallel to the processing surface 11, so that the yield and the yield of the vertical channel can be kept. The body region 15 is provided in the subsequent processes of fig. 3 to 17 until the back grinding, but the illustration is omitted, the body region 15 is present to maintain the basic physical structure of the substrate as a process carrier, the thickness of the body region 15 after the back grinding is greatly reduced, but the drain epitaxial layer 10 is not damaged, and the thinned body region 15 in the chip product may or may not be retained. The above epitaxial structure is selected as appropriate according to device blocking voltage and device parameter requirements, the epitaxial structure is N-type but not limited to N-type, and the crystal orientation <100> is not limited to this crystal orientation.
Referring to fig. 3, in step S3, first trenches 13 are etched from the processing surface 11 and parallel to each other, and the surface acidification film 14 is removed after the first trenches 13 are formed. The material of the surface acidification film 14 is silicon oxide, the thickness is 1000A-8000A, or the surface deposition masking film can be selected to replace, the material of the surface deposition masking film is silicon nitride but is not limited to silicon nitride. And selecting a pattern of the region masking film in a photoetching and etching mode, etching the field plate groove of the shielding body, wherein the etching depth of the first groove 13 is between 1.5 and 10 microns according to different characteristics of devices.
Referring to fig. 4, as an optional step S4, after the steps of providing the drain substrate and forming the first trench 13, the method further includes: and forming a shielding grid bottom floating inverted pole type bottom column junction 70 at the part of the drain epitaxial layer 10 corresponding to the bottom of the first groove 13 in an ion implantation mode. Specific example sub-steps include: s41, before injecting the floating bottom of the shield grid into the bottom of the inverted pole type pillar bottom junction 70, the growth of the masking oxide layer is carried out, the growth thickness is 200-800A, S42, P pillar injection is carried out, B11 injection can comprise multiple times of injection, the injection energy is 20k-2Mev, and the injection dosage is 10 11 ～ 10 14 ions/cm 2 The method comprises the steps of forming a floating bottom-inverted-pole type pillar bottom junction 70 at the bottom of a shielding grid as shown in figure 4, wherein the depth of the pillar bottom junction is 0.5-5 microns, forming a sacrificial oxide layer at the temperature of 700-1100 ℃ and the thickness of the sacrificial oxide layer is 300-1000 angstroms, removing the sacrificial oxide layer in a selective dry etching mode through S44, and cleaning a drain electrode epitaxial layer 10 through S45. This step is for forming a reverse-polarity type bottom stud junction and cleaning the first trench 13, avoiding adverse effects of implantation of impurities on the insulation process of the first trench 13.
Referring to fig. 5, in step S5, a first oxide isolation layer 91 is formed on the processed surface 11 and the first trench 13 to insulate the inner wall of the first trench 13. The first oxide isolation layer 91 is specifically a thermal oxide layer or/and a deposited oxide layer, but is not limited to these two, and the thickness of the oxide layer may be between 700 to 13000A according to the device parameter requirements.
Referring again to fig. 5, the step of forming the first oxide isolation layer 91 includes: the method comprises the steps of forming a first oxidation isolation layer 91 in a thermal oxidation or precipitation mode, forming a side wall protection layer in a first groove 13, anisotropically etching the side wall protection layer to form an opening at the bottom of the first groove 13, forming an oxidation isolation superposition block 93 in the opening of the side wall protection layer, selectively etching and removing the side wall protection layer to expose the first oxidation isolation layer 91, wherein the thickness of the first oxidation isolation layer 91 and the oxidation isolation superposition block 93 at the bottom of the inner wall is larger than that of the first oxidation isolation layer 91 at the side part of the inner wall, specifically, the first oxidation isolation layer 91 is made of silicon oxide, and the side wall protection layer is made of silicon nitride. The thickness of the sidewall protection layer, such as silicon nitride, may be in the range of 500-10000A. When the oxide isolation stack block 93 may be formed on the processing surface 11 after being formed as a thick oxide layer on the bottom of the trench in an anisotropic deposition manner, the CMP may be used to remove the sidewall protection layer on the processing surface 11 and the excess portions of the oxide isolation stack block 93, and then selectively and chemically etch away the sidewall protection layer on the sidewall of the first trench 13.
Referring to fig. 6 and 7, a source extension inverse fin 20 is disposed in the first trench 13 by deposition filling, the depth of the first trench 13 does not exceed the thickness of the drain epitaxial layer 10, and the source extension inverse fin 20 and the first oxide isolation layer 91 are removed on the processing surface 11. Fig. 6 corresponds to step S6 for large area formation of the source-extended inverted fin 20, and fig. 7 corresponds to step S7 for shape trimming of the source-extended inverted fin 20. One exemplary, but not limiting, process condition of step S6 is: s61, depositing polysilicon (Poly) in the first trench 13 and forming on the processing surface 11, S62, in-stu doping and implanting dopant to make the polysilicon conductive, the doping concentration is between 10 18 ～ 10 21 ions/cm 3 The thickness is 1000-15000A.
Referring to fig. 7, as an optional step S7 after S6, in the step of disposing the source extension inverted fin 20, the source extension inverted fin 20 and the first oxide isolation layer 91 are removed from the processing surface 11 by a Chemical Mechanical Polishing (CMP) or/and etch back (etch back), and preferably, the source extension inverted fin 20 is made of conductive polysilicon.
Referring to fig. 8, as a step of forming the second trench 31, the pre-step S8 included is: a mask layer 41 is formed on the processing surface 11 to cover the processing surface 11 and the top of the source extended inverse fin 20. The mask layer 41 is used as a surface deposition masking film layer, and is made of, but not limited to, silicon oxide (SIO2) or silicon nitride (SIN), and the thickness is 1000A to 8000A.
Referring to fig. 9, in step S9, second trenches 31 located between the first trenches 13 are formed by etching the processing surface 11 by using the patterning of the mask layer 41, and the second depth of the second trenches 31 is smaller than the first depth of the first trenches 13, and referring to fig. 9, preferably, after the second trenches 31 are formed, an under-gate floating inversion junction 80 is formed in the drain epitaxial layer 10 at a position corresponding to the bottom of the second trenches 31 by ion implantation. An exemplary specific process of step S9 includes: the method comprises the steps of S91, selecting a hollow area of a mask layer 41 through photoetching and etching, S92, forming a second groove 31 through etching, wherein the groove depth of the second groove 31 is 0.5-2.0 um, S93, forming a shielding oxide layer (screen oxide) in the second groove 31, the growth thickness is 200-800A, S94 and ion implantation B11 comprise multiple times of implantation, the implantation energy is 20-200 kev, and the implantation dosage is 10 11 ～10 13 ions/cm 2 To form an under-gate floating inversion junction 80 as shown in figure 9.
Referring to fig. 10, in step S10, a second oxide isolation layer 92 is formed in the processed surface 11 and the second trench 31 to insulate the inner wall of the second trench 31. Referring to fig. 10 again, in the step of forming the second oxide isolation layer 92, the second oxide isolation layer 92 is specifically a gate oxide layer, and the gate oxide layer is formed on the inner wall of the second trench 31 and the processing surface 11 by thermal oxidation or thermal oxidation plus deposition, wherein the oxidation temperature of the gate oxide layer is 700 to 1100 ℃, and the thickness of the gate oxide layer is 300 to 1300A. Preferably, the step S10 further includes, before the gate oxide layer is formed, forming a sacrificial gate oxide layer on the inner wall of the second trench 31, wherein the oxidation temperature of the sacrificial gate oxide layer is 700-1100 ℃, and the thickness of the sacrificial gate oxide layer is 300-1000A, and then removing the sacrificial gate oxide layer and cleaning the drain epitaxial layer 10, in order to remove adverse effects on the inner wall surface of the second trench 31 during ion implantation and to remove implanted ions accumulated on the surface.
Referring to fig. 11, in step S11, a gate 40 is disposed in the second trench 31 by deposition filling. In the step of disposing the gate electrode 40, a method of removing the portion of the gate electrode 40 on the processing surface 11 includes chemical mechanical polishingPreferably, the material of the gate 40 includes conductive polysilicon containing doped ions. One exemplary, but not limiting, process condition of step S11 is: s111, depositing polysilicon (Poly) in the second trench 31 and forming on the processing surface 11, doping and implanting S112, in-stu to make the polysilicon conductive with a doping concentration between 10 18 ～ 10 21 ions/cm 3 And removing excess conductive polysilicon on the processing surface 11 by Chemical Mechanical Polishing (CMP) or/and etch back (etch back) to obtain the gate 40 in the second trench 31 (S113).
Referring to fig. 12, in step S12, an active layer 30 is formed under the processed surface 11 of the drain epitaxial layer 10 by energy implantation, and the thickness and depth of the active layer 30 are within the range that the second depth of the second trench 31 can penetrate. In the step of forming the active layer 30, the active layer 30 is formed by internalization of the processing surface 11 of the drain epitaxial layer 10, and the active layer 30 comprises a channel layer 32 positioned at the bottom, a current balance layer 33 positioned on the channel layer 32, and a source domain layer 34 positioned on the current balance layer 33. One exemplary, but not limiting, process condition of step S12 is: s121, defining a channel region by photoetching, and S122, implanting B11 for multiple times to form a P-body region with implantation energy of 20-800 kev and implantation dosage of 10 12 ～10 14 ions/cm 2 To form the active layer 30.
Referring to fig. 13, as an optional step S13, a field layer is formed on the upper layer of the active layer 30 by positive type implantation in the active layer 30 to define the upper boundary of the channel layer 32 and the lower boundary of the current balance layer 33 on the lower layer of the active layer 30. One exemplary, but not limiting, process condition of step S13 is: s131, defining a channel region by photoetching, S132, implanting As or P for multiple times to form an N-type current balance layer, wherein the implantation energy is 20-400 kev, and the implantation dosage is 10 13 ～10 15 ions/cm 2 To form a current balancing layer 33 of the active layer 30 and to define the channel layer 32.
Referring to fig. 14, as an optional step S14, a positive type note is again formed in the field layer of the active layer 30Then, the source region layer 34 is formed to define the upper boundary of the current balance layer 33 and the lower boundary of the source region layer 34. One exemplary, but not limiting, process condition of step S14 is: s141, implanting As or P for multiple times to form N-type source layer with implantation energy of 20-100 kev and implantation dose of 10 14 ～10 16 ions/cm 2 To form the source region layer 34 of the active layer 30 and define the current balance layer 33.
Referring to fig. 15, in step S15, an inter-dielectric layer 50 is deposited on the active layer 30 and the gate electrode 40, so that the gate electrode 40 is buried. One exemplary, but not limiting, process condition of step S15 is: the deposited dielectric layer is a combination of LTO (low temperature silicon oxide) or HTO (high temperature silicon oxide) and BPSG (boron phosphorus silicon glass) or PSG (phosphorus silicon glass), wherein the thickness of the LTO or HTO is 500-3000A, and the thickness of the BPSG or PSG is 2000-10000A.
Referring to fig. 16, in step S16, a third trench 51 is etched from the ild layer 50 to align with the first trench 13, the inner wall of the third trench 51 is not insulated, and the width and depth of the third trench 51 are sufficient to directly expose the edge of the active layer 30 and the bottom of the source-extended inverted fin 20. When the reverse-polarity dopant of the channel layer 32 is dry etched, it can be used as an etching stop signal, so the third trench 51 does not penetrate through the channel layer 32. In the step of forming the third trench 51, it is preferable that the third trench 51 is an enlarged slot structure, an inner wall of the third trench 51 is spaced apart from an inner wall of the second trench 31, a width of the third trench 51 is greater than a width of the first trench 13, and a depth of the third trench 51 is smaller than an entire thickness of the active layer 30 and greater than a sum of thicknesses of the current balance layer 33 and the source region layer 34. One exemplary, but not limiting, process condition of step S16 is: defining a contact hole region by photoetching to define the width of the third groove 51 to be larger than the width of the first groove 13 and smaller than the gap (spacing) between two adjacent second grooves 31 in advance S161, and etching to form the third groove 51, wherein the depth of the third groove 51 from the processing surface 11 is larger than the thickness of the source region layer 34 and the current balance layer 33 and smaller than the thickness of the active layer 30 so as to avoid penetrating through the active layer 30.
Referring to fig. 17, in step S17, a source layer 60 is formed in the third trench 51 to turn on the source-extended inverted fin 20, and the inversion layer implantation thickness direction of the active layer 30 defines the channel length of the field effect transistor. In the step of forming the source layer 60, the source layer 60 is further formed on the inner dielectric layer 50, the material of the source layer 60 is metal, and after the step of forming the source layer 60, back-of-crystal thinning and back-of-crystal metallization are performed on the back surface 12 of the drain substrate 1. The source layer 60 is specifically made of metal, a source contact pad is disposed above the finally manufactured field effect transistor and can be provided by the upper surface of the source layer 60, a drain contact pad 16 is disposed below the field effect transistor and is formed by metallization of the back surface 12, and the structure of the field effect transistor is located between the metal pads of the source and drain electrodes.
The basic principle of the embodiment of the method is as follows: by using the pre-fabrication of the source extension inverted fin 20, the process difficulty of filling the source extension in the trench of the drain epitaxial layer 10 in the semiconductor manufacturing process is reduced, and finally the double inverted fin inter-half gate field effect transistor is manufactured.
An embodiment of the present invention further provides a semiconductor chip device, including: the fet structure that may be combined according to any of the above-mentioned embodiments, or the fet structure used with reference to fig. 18 includes a drain epitaxial layer 10 located below a processing surface 11, a source layer 60 located on the processing surface 11, and source-extended inverted fins 20 and a gate 40 embedded in the drain epitaxial layer 10, wherein the gate 40 is arranged between the source-extended inverted fins 20, symmetrical channels are formed on both sides of the gate 40 in parallel from the source layer 60 to the drain epitaxial layer 10, a symmetrical field resistor is further formed on the channel on both sides of the gate 40 in parallel from the source layer 60 to the drain epitaxial layer 10, a gate-under-floating inverted junction 80 is preferably formed on the drain epitaxial layer 10 at a bottom portion corresponding to the gate 40, and a shield-gate bottom-floating inverted junction 80 is preferably formed on the drain epitaxial layer 10 at a bottom portion corresponding to the source-extended inverted fins 20 A bottom stud junction 70.
The basic principle of the embodiment is as follows: the source layer 60, which is located on the processing surface 11, and the gate electrode 40, which is embedded in the drain epitaxial layer 10, establish a plurality of vertical parallel channels defined in the thickness direction of the active layer 30, and the electron current can be uniformly outputted (or inputted) to the back surface 12 of the drain substrate 1. When the semiconductor chip device is arranged on the carrier plate, the drain contact connection is completed, the connection operation of an electrode position can be saved, and the problem of the leakage current on the back surface of the chip does not need to be considered along with the fact that the chip is thinner and thinner. The electron current is shunted by the source layer 60, under the electric field effect of the gate 40, the channel layer 32 is longitudinally conducted to reach the back surface 12 of the drain substrate 1, the source extended inverted fin 20 can prevent the electron current from collecting in advance in the drain epitaxial layer 10, and the source layer 60 and the back surface 12 are in a shunting staggered isolation gate form, so that a more uniform electron current distribution is formed, and the semiconductor power device is particularly suitable for application.
Fig. 19 shows a field effect transistor structure according to a first variation of the present invention, in which, in a local structure of a cross gate, the transistor includes a bottom drain epitaxial layer 10, a top source layer 60, and source extended fins 20 and a gate 40 embedded in the drain epitaxial layer 10, the gate 40 is arranged between the source extended fins 20, two sides of the gate 20 are formed with a pair of symmetrical channels connected in parallel from the source layer to the inside of the drain epitaxial layer, and the channel layer 32 is located at the edges of the channel layer thickness direction at two sides of the gate 40 in fig. 19, in this variation, a pair of symmetrical field resistors connected in parallel from the source layer 60 to the drain epitaxial layer 10 is further formed above the channel layer 32 at two sides of the gate 20, and the current balance layer 33 is located at the edges of the current balance layer 33 at two sides of the gate 40 along the thickness direction of the current balance layer, compared with the above-described preferred embodiments, the fabrication of the floating-under-gate inversion junction 80 is omitted. One of the main functions of the floating-under-gate inversion junction 80 is to reduce the electron current breakdown at the bottom of the gate 20, resulting in UIS (unclamped inductive switching) performance. The omission of the floating-under-gate inversion junction 80 may change some of the electrical properties of the fet, but the basic thermal dissipation, SOA enhancement, semiconductor fabrication process yield, and UIS reliability of the device may also be maintained. The structure can be used in the situation that the grid oxygen reliability is enough, and the manufacture of the floating-under-grid inverse-type junction 80 can be omitted, so that the semiconductor process is simplified.
Fig. 20 shows a field effect transistor structure according to a second variation of the present invention, in which, in a local structure of a cross gate, the transistor includes a drain epitaxial layer 10 at the bottom, a source layer 60 at the top, and source extended reversed fins 20 and a gate 40 embedded in the drain epitaxial layer 10, the gate 40 is arranged between the source extended reversed fins 20, symmetric channels are formed on both sides of the gate 20 in parallel from the source layer to the drain epitaxial layer, and are located at the edges of the channel layer 32 on both sides of the gate 40 along the thickness direction of the channel layer in fig. 20, and the second variation omits the formation of the floating inversion type bottom stud junction 70 and the floating inversion type bottom stud junction 80 compared with the first variation and omits the formation of the floating inversion type bottom stud junction 70 and the floating inversion bottom stud junction 80 compared with the above-described preferred embodiment. Basic heat dissipation performance, SOA improvement, semiconductor manufacturing process yield and UIS reliability of the device can be maintained. This architecture can be used where there is already sufficient barrier gate depth (the depth of the source extension fin 20 embedded in the drain epitaxial layer 10) and gate oxide reliability to simplify the semiconductor process. One of the main functions of the floating gate type bottom stud junction 70 in the semiconductor process is to reduce the etching depth of the first trench 13, reduce the thermal oxidation time and the process temperature, increase the process window, improve the yield, and omit the manufacturing of the floating gate type bottom stud junction 70 when the trench process capability and the accuracy of the semiconductor process are better.
FIG. 21 shows a third variation of the present invention, which comprises a bottom drain epitaxial layer 10, a top source layer 60, and source-extended inverted fins 20 and a gate 40 embedded in the drain epitaxial layer 10, wherein the gate 40 is arranged between the source-extended inverted fins 20, and symmetric channels are formed on both sides of the gate 20 from the source layer to the drain epitaxial layer in parallel, and the channel layer 32 is located on both sides of the gate 40 along the edges of the channel layer in the thickness direction of the channel layer in FIG. 21. compared with the second variation, the third variation omits the fabrication of the current balancing layer 33 and the oxidation isolation stacking block 93, i.e., the active layer 30 only includes the channel layer 32 and the source region layer 34 or/and the oxidation isolation stacking block 93, and compared with the first variation, omits the current balancing layer 33, the oxidation isolation stacking block 93, The fabrication of the oxide isolation stack block 93 and the floating-to-bottom-of-the-pole reverse-type stud junction 70, and the fabrication of the current balance layer 33, the oxide isolation stack block 93, the floating-to-bottom-of-the-pole reverse-type stud junction 70, and the floating-to-bottom-of-the-gate reverse-type stud junction 80 are omitted compared to the previous preferred embodiment. Basic heat dissipation performance, SOA improvement, semiconductor manufacturing process yield and UIS reliability of the device can be maintained. This architecture can be used where there is already sufficient uniformity of device temperature rise, sufficient shield gate depth (depth of source extension fin 20 embedded in drain epitaxial layer 10) and gate oxide reliability to simplify semiconductor processing. One of the main roles of the current balancing layer 33 is: the edge along the layer thickness direction on both sides of the gate 40 is equivalent to introducing a resistor at the source in the equivalent circuit of the transistor circuit structure to balance the current of the individual transistor units connected in parallel, and when the temperature rise of each transistor unit is uniform, the fabrication of the current balance layer 33 can be omitted. One of the main roles of the oxidation isolation building block 93 is: the problem that an electric field is completely concentrated at the bottom of the shielding grid when an internal field plate charge balance device is reversely blocked is solved by improving that the oxide layer at the bottom of the first groove 13 is too thin, and when the thickness of the oxide layer at the bottom of the first groove 13 is close to that of the side wall oxide layer (80%) or the requirement that the electric field is concentrated at the bottom of the shielding grid is not high, the manufacturing of the oxidation isolation superposition block 93 can be omitted.
Any of the floating-bottom-of-the-column junction 70, the floating-bottom-of-the-gate bottom-of-the-column junction 80, the oxide isolation stack 93, the current balance layer 33, or any combination thereof in the above preferred embodiment and the first to third variations is within the scope of the present invention.
The embodiments of the present invention are merely preferred embodiments for easy understanding or implementing of the technical solutions of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes in structure, shape and principle of the present invention should be covered by the claims of the present invention.

Claims (9)

1. A field effect transistor structure, comprising:
the drain electrode substrate is provided with a processing surface and a corresponding back surface, first grooves which are parallel to each other are formed on the processing surface, the inner walls of the first grooves are subjected to insulation processing through first oxidation isolation layers, and source electrode extension inverted fins are arranged in the first grooves;
an active layer formed on the processing surface of the drain substrate, wherein a second groove is formed between the first grooves by the active layer, the inner wall of the second groove is insulated and processed by a second oxidation isolation layer, a grid electrode is arranged in the second groove, and the second depth of the second groove is enough to penetrate through the active layer and is smaller than the first depth of the first groove;
the inner dielectric layer is formed on the active layer and the grid electrode, so that the grid electrode is of an embedded structure;
a source layer formed in the third trench to conduct the source extended inverted fin, the active layer having a thickness direction defining a channel length of the field effect transistor, the active layer having a multi-layer structure including: the depth of the third groove enables the third groove to penetrate through the source electrode field layer and the current balance layer;
the third groove is in an enlarged groove hole structure, the inner wall of the third groove keeps an interval with the inner wall of the second groove, the width of the third groove is larger than that of the first groove, and the depth of the third groove is smaller than the overall thickness of the active layer and larger than the sum of the thicknesses of the current balance layer and the source electrode field layer;
wherein, the section of the inner side wall of the third groove connected with the bottom is inclined to avoid over etching to the channel layer of the active layer when the third groove is formed;
when the third groove is formed and dry-etched to the counter-pole doping substance of the channel layer, the third groove is used as an etching stop signal, and the third groove cannot penetrate through the channel layer;
the current balance layer is lightly doped N type, the source electrode field layer is heavily doped N type, the source electrode extension inverted fin is made of conductive polysilicon, the top surface of the source electrode extension inverted fin is relatively recessed in the upper edges of the first oxidation isolation layers on the two sides, and the recessed position is filled with the source electrode layer.
2. The field effect transistor structure of claim 1, wherein the source layer is further formed on the inter-dielectric layer, the active layer being formed by internalization of the processed surface of the drain substrate.
3. The field effect transistor structure of claim 1 wherein the bottom of the first trench is subjected to a thick oxidation process such that the insulation thickness of the first trench is greater at the bottom of the inner wall than at the sides of the inner wall.
4. The field effect transistor structure of claim 1, wherein said drain substrate is further formed with a deep implanted region at a location corresponding to a bottom of said first trench to form a shielded gate bottom floating inversion type bottom-pillar junction.
5. The field effect transistor structure of claim 1, wherein said drain substrate is further formed with an implanted region at a location corresponding to a bottom of said second trench to form an under-gate floating-inversion junction.
6. The field effect transistor structure of any of claims 1-5, wherein electron flow from the source layer is shunted by a side of the third trench to the drain substrate between the first trenches along a symmetrical side of a sidewall profile of the second trench, and is uniform at the backside of the drain substrate or a drain metal pad disposed at the backside, by an electric field effect of the gate.
7. A method of fabricating a field effect transistor structure, comprising:
providing a drain electrode substrate, wherein the drain electrode substrate is provided with a processing surface and a corresponding back surface, and first grooves which are parallel to each other are formed by etching the processing surface;
forming a first oxidation isolation layer in the processing surface and the first groove to enable the inner wall of the first groove to be subjected to insulation processing;
arranging a source extension inverted fin in the first groove in a deposition filling mode, and removing the source extension inverted fin and the part of the first oxidation isolation layer on the processing surface;
etching the processing surface to form second grooves between the first grooves, wherein the second depth of the second grooves is smaller than the first depth of the first grooves;
forming a second oxidation isolation layer in the processing surface and the second groove to enable the inner wall of the second groove to be subjected to insulation processing;
arranging a grid in the second groove in a deposition filling mode;
in the step of forming the active layer, the active layer is formed by internalization of the processing surface of the drain electrode substrate, and comprises a channel layer positioned at the bottom layer, a current balance layer positioned on the channel layer and a source electrode field layer positioned on the current balance layer, wherein the current balance layer is lightly doped with N type, and the source electrode field layer is heavily doped with N type;
forming an inner dielectric layer on the active layer and the grid electrode in a deposition covering mode, so that the grid electrode is of an embedded structure;
forming a third groove aligned with the first groove by etching the inner dielectric layer, wherein the inner wall of the third groove is not subjected to insulation treatment, the third groove is of an enlarged slot structure, the inner wall of the third groove keeps an interval with the inner wall of the second groove, the width of the third groove is larger than the width of the first groove, the depth of the third groove is smaller than the whole thickness of the active layer and larger than the sum of the thicknesses of the current balance layer and the source electrode field layer, the section of the third groove, which is connected with the bottom part of the inner side wall, is inclined so as to avoid excessive erosion of the channel layer of the active layer when the third groove is formed, the width and the depth of the third groove are enough to directly expose the edge of the active layer and expose the top part of the source electrode extending inverted fin, and when the third groove is formed, the inverted pole type doping material of the channel layer is formed by dry etching, the third groove does not penetrate through the channel layer and is used as an etching stop signal;
and forming a source layer in the third groove to conduct the source extension inverted fin, wherein the thickness direction of the active layer defines the channel length of the field effect transistor, and the source extension inverted fin is relatively recessed in the first oxide isolation layers at two sides and is filled by the source layer.
8. The method of claim 7, wherein:
after the step of providing the drain substrate, further comprising: forming a floating reverse pole type column bottom junction at the bottom of the shielding grid on the part, corresponding to the bottom of the first groove, of the drain electrode substrate in an ion implantation mode, wherein the drain electrode substrate is a conductive semiconductor wafer;
or/and, in the step of forming the first oxidation isolation layer, comprises: the method comprises the steps of forming a first oxidation isolation layer in a thermal oxidation or precipitation mode, forming a side wall protection layer in a first groove, anisotropically etching the side wall protection layer to form an opening at the bottom of the first groove, forming an oxidation isolation superposition block in the opening of the side wall protection layer, selectively etching and removing the side wall protection layer to expose the first oxidation isolation layer, wherein the thickness of the first oxidation isolation layer and the oxidation isolation superposition block at the bottom of the inner wall is larger than that of the first oxidation isolation layer at the side part of the inner wall;
or/and, in the step of disposing the source extension inverted fin, the method for removing the source extension inverted fin and the first oxidation isolation layer on the processing surface comprises chemical mechanical polishing or/and back etching, or/and in the step of forming the second trench, the method comprises the following pre-steps: forming a mask layer on the processing surface to cover the processing surface and the top of the source electrode extension inverted fin, and forming a gate-lower floating inverted-pole type junction on the drain electrode substrate at a position corresponding to the bottom of the second groove in an ion implantation mode after the second groove is formed;
the method comprises the steps of forming a second oxidation isolation layer on the inner wall of a second groove, wherein the second oxidation isolation layer is a gate oxide layer, and the gate oxide layer is formed on the inner wall of the second groove and the processing surface in a thermal oxidation or thermal oxidation and deposition mode;
or/and in the step of arranging the grid electrode, the method for removing the part of the grid electrode on the processing surface comprises chemical mechanical polishing or/and back etching, wherein the material of the grid electrode comprises conductive polysilicon and doped ions;
and after the step of forming the source layer, carrying out crystal back thinning and crystal back metallization on the back surface of the drain electrode substrate.
9. A semiconductor chip apparatus, comprising: a field effect transistor structure as claimed in any one of claims 1 to 6.
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