CN113434331A

CN113434331A - Cross-frame coding management method, memory storage device and memory control circuit

Info

Publication number: CN113434331A
Application number: CN202110755286.4A
Authority: CN
Inventors: 张光耀; 张正锐
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2021-07-05
Filing date: 2021-07-05
Publication date: 2021-09-24
Anticipated expiration: 2041-07-05
Also published as: CN113434331B

Abstract

The present invention provides a cross-frame coding management method, a memory storage device and a memory control circuit unit. The method includes: reading label replacement information corresponding to the first entity group; encoding the first data; storing the first partial data of the encoded first data in the first entity group corresponding to the first label information. at least one first entity unit; and storing the second part of the encoded first data into at least one second entity unit corresponding to the second label information in the first entity group according to the label replacement information. The first label information corresponds to the first cross-frame coding group. The second label information corresponds to a second cross-frame coding group. The first cross-frame coding group is different from the second cross-frame coding group. Thereby, the use efficiency of the rewritable non-volatile memory module can be improved.

Description

Cross-frame coding management method, memory storage device and memory control circuit

Technical Field

The present invention relates to a group coding management technique inside a memory, and more particularly, to a cross-frame coding management method, a memory storage device, and a memory control circuit unit.

Background

Portable electronic devices such as mobile phones and notebook computers have grown rapidly in these years, so that the demand of consumers for storage media has also increased rapidly. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable electronic devices as exemplified above.

Under the Redundant Array of Independent Disks (RAID) Error Correction Code (ECC) architecture, data stored in multiple physical program units (e.g., physical pages) of a rewritable nonvolatile memory module may be encoded to generate parity data (also referred to as global parity data) that can protect data in the multiple physical program units simultaneously. When decoding data, the global parity data can utilize the logical relationship between data bits in multiple physical program units to perform error detection and/or correction across the physical program units.

However, when a memory storage device including a rewritable nonvolatile memory module is shipped, a plurality of physical programming units that can be synchronously encoded in the rewritable nonvolatile memory module are fixed and can be assigned with the same tag (also referred to as an encoding tag). When storing data, data in physical program units corresponding to the same tag may be synchronously encoded to generate corresponding global parity data. However, as the wear of the rewritable nonvolatile memory module increases (e.g., the P/E cycle increases), once a plurality of physical program cells with a higher Bit Error Rate (BER) simultaneously appear among the plurality of physical program cells assigned with the same tag, data read from the plurality of physical program cells may not be successfully decoded.

Disclosure of Invention

The invention provides a cross-frame coding management method, a memory storage device and a memory control circuit unit, which can dynamically manage the group coding configuration of data in a rewritable nonvolatile memory module, thereby improving the use efficiency of the rewritable nonvolatile memory module.

An exemplary embodiment of the present invention provides a cross-frame encoding management method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity groups. Each of the plurality of entity groups includes a plurality of entity units. The cross-frame coding management method comprises the following steps: reading tag permutation information corresponding to a first entity group of the plurality of entity groups; encoding the first data; storing a first portion of the encoded first data to at least a first entity unit of the first entity group corresponding to first tag information; and storing a second part of the encoded first data to at least one second entity unit corresponding to second tag information in the first entity group according to the tag replacement information. The first tag information corresponds to a first cross-frame encoding group. The second tag information corresponds to a second cross-frame encoding group. The first cross-frame encoding group is different from the second cross-frame encoding group.

In an exemplary embodiment of the invention, the method for managing cross-frame coding further includes: configuring tag information for each entity unit in the first entity group, wherein the tag information reflects a cross-frame coding group to which the each entity unit belongs.

In an exemplary embodiment of the invention, the method for managing cross-frame coding further includes: parity data is generated based on the encoding result of the first data. The parity data is used to protect the first portion of the first data stored in the at least one first physical unit and the second portion of the first data stored in the at least one second physical unit.

In an exemplary embodiment of the present invention, the step of storing the second part of the encoded first data to the at least one second entity unit corresponding to the second tag information in the first entity group according to the tag replacement information comprises: exchanging the second label information corresponding to the at least one second entity unit with the first label information corresponding to at least one third entity unit in the first entity group according to the label replacement information; and storing the second part of data to the at least one second entity unit according to the label exchanging result.

In an exemplary embodiment of the present invention, the step of storing the second part of the encoded first data to the at least one second entity unit corresponding to the second tag information in the first entity group according to the tag replacement information comprises: storing the second portion of the encoded first data to a data area in the at least one second physical unit; and storing the tag replacement information to an idle area in the at least one second physical unit.

In an exemplary embodiment of the invention, the method for managing cross-frame coding further includes: reading second data from the first group of entities prior to reading the tag permutation information corresponding to the first group of entities; storing the tag replacement information according to a bit error condition of the second data; moving the second data to a second entity group of the plurality of entity groups for storage; and erasing the first entity group.

In an exemplary embodiment of the present invention, the step of storing the tag replacement information according to the bit error condition of the second data comprises: in response to a bit error rate of data read from at least one third physical unit in the first physical group being higher than a preset value, storing the tag replacement information corresponding to the at least one third physical unit.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity groups. Each of the plurality of entity groups includes a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for reading the tag replacement information corresponding to a first entity group in the plurality of entity groups. The memory control circuit unit is also used for encoding first data. The memory control circuitry is further configured to store a first portion of the encoded first data to at least a first physical unit of the first physical group corresponding to first tag information. The memory control circuit unit is further configured to store a second portion of the encoded first data to at least a second entity unit of the first entity group corresponding to second tag information according to the tag permutation information. The first tag information corresponds to a first cross-frame encoding group. The second tag information corresponds to a second cross-frame encoding group. The first cross-frame encoding group is different from the second cross-frame encoding group.

In an example embodiment of the present invention, the memory control circuit unit is further configured to configure tag information for each physical unit in the first physical group, wherein the tag information reflects a cross-frame encoding group to which the each physical unit belongs.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to generate parity data according to an encoding result of the first data. The parity data is used to protect the first portion of the first data stored in the at least one first physical unit and the second portion of the first data stored in the at least one second physical unit.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: reading second data from the first group of entities prior to reading the tag permutation information corresponding to the first group of entities; storing the tag replacement information according to a bit error condition of the second data; moving the second data to a second entity group of the plurality of entity groups for storage; and erasing the first entity group.

An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of entity groups. Each of the plurality of entity groups includes a plurality of entity units. The memory control circuit unit comprises a host interface, a memory interface, an error checking and correcting circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuitry is coupled to the host interface, the memory interface, and the error checking and correcting circuitry. The memory management circuit is configured to read tag permutation information corresponding to a first entity group of the plurality of entity groups. The error checking and correcting circuit is used for coding first data. The memory management circuit is also configured to store a first portion of the encoded first data to at least a first physical unit of the first physical group corresponding to first tag information. The memory management circuit is further configured to store a second portion of the encoded first data to at least a second entity unit of the first entity group corresponding to second tag information according to the tag permutation information. The first tag information corresponds to a first cross-frame encoding group. The second tag information corresponds to a second cross-frame encoding group. The first cross-frame encoding group is different from the second cross-frame encoding group.

In an example embodiment of the present invention, the memory management circuit is further configured to configure tag information for each physical unit in the first physical group. The tag information reflects the cross-frame coding group to which each entity unit belongs.

In an exemplary embodiment of the invention, the error checking and correcting circuit is further configured to generate parity data according to an encoding result of the first data. The parity data is used to protect the first portion of the first data stored in the at least one first physical unit and the second portion of the first data stored in the at least one second physical unit.

In an exemplary embodiment of the present invention, the operation of storing the second part of the encoded first data to the at least one second entity unit corresponding to the second tag information in the first entity group according to the tag replacement information comprises: exchanging the second label information corresponding to the at least one second entity unit with the first label information corresponding to at least one third entity unit in the first entity group according to the label replacement information; and storing the second part of data to the at least one second entity unit according to the label exchanging result.

In an exemplary embodiment of the present invention, the bit error rate of the at least one second physical unit is lower than the bit error rate of the at least one third physical unit.

In an exemplary embodiment of the present invention, the operation of storing the second part of the encoded first data to the at least one second entity unit corresponding to the second tag information in the first entity group according to the tag replacement information comprises: storing the second portion of the encoded first data to a data area in the at least one second physical unit; and storing the tag replacement information to an idle area in the at least one second physical unit.

In an exemplary embodiment of the invention, the memory management circuit is further configured to: reading second data from the first group of entities prior to reading the tag permutation information corresponding to the first group of entities; storing the tag replacement information according to a bit error condition of the second data; moving the second data to a second entity group of the plurality of entity groups for storage; and erasing the first entity group.

In an exemplary embodiment of the present invention, the operation of storing the tag replacement information according to the bit error condition of the second data comprises: in response to a bit error rate of data read from at least one third physical unit in the first physical group being higher than a preset value, storing the tag replacement information corresponding to the at least one third physical unit.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of entity groups. Each of the plurality of entity groups includes a plurality of entity units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to send a read instruction sequence instructing reading of second data from a first physical group of the plurality of physical groups. The memory control circuit unit is further configured to adjust a configuration of a cross-frame encoding group of the first physical group according to a bit error condition of the second data. The configuration of the cross-frame coding group reflects that a plurality of entity units in the first entity group belong to the same cross-frame coding group. The memory control circuitry unit is also to access the first group of entities according to the adjusted configuration of the cross-frame encoding group.

In an exemplary embodiment of the present invention, adjusting the configuration of the cross-frame coding group of the first physical group according to the bit error condition of the second data comprises: adjusting a configuration of the cross-frame encoding group of the first physical group in response to a bit error rate of data read from at least a third physical unit in the first physical group being higher than a preset value.

In an exemplary embodiment of the present invention, adjusting the configuration of the cross-frame coding group of the first physical group according to the bit error condition of the second data comprises: exchanging a cross-frame coding group to which a part of the entity units in the first entity group belong with a cross-frame coding group to which another part of the entity units in the first entity group belong, so as to change the configuration of the cross-frame coding group of the first entity group.

In an exemplary embodiment of the present invention, the operation of swapping the cross-frame coding group to which the part of the physical units in the first physical group belong with the cross-frame coding group to which the other part of the physical units in the first physical group belong comprises: exchanging the tag information corresponding to the part of the entity units in the first entity group with the tag information corresponding to the other part of the entity units in the first entity group.

In an exemplary embodiment of the present invention, the operation of accessing the first entity group according to the adjusted configuration of the cross-frame coding group comprises: storing tag permutation information reflecting the adjusted configuration of the cross-frame encoding group of the first entity group; and accessing the first group of entities according to the tag permutation information.

Based on the above, after reading the tag replacement information corresponding to the first entity group, the first part of the encoded first data may be stored to the first entity unit corresponding to the first tag information in the first entity group. On the other hand, a second part of the encoded first data may be stored to a second entity unit corresponding to the second tag information in the first entity group according to the tag replacement information. The first tag information corresponds to a first cross-frame encoding group. The second tag information corresponds to a second cross-frame encoding group. The first cross-frame encoding group is different from the second cross-frame encoding group. By dynamically managing the group coding configuration of the data in the rewritable nonvolatile memory module, the use efficiency of the rewritable nonvolatile memory module can be improved.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;

FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a diagram illustrating writing new data according to an exemplary embodiment of the present invention;

FIG. 8 is a diagram illustrating a default tag configuration for a group of entities, in accordance with an exemplary embodiment of the present invention;

FIG. 9 is a diagram illustrating a high bit error rate physical unit in accordance with an exemplary embodiment of the present invention;

FIG. 10 is a diagram illustrating storage tag replacement information and movement data according to an exemplary embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating tag replacement according to an exemplary embodiment of the present invention;

FIG. 12 is a diagram illustrating writing new data according to an exemplary embodiment of the present invention;

FIG. 13 is a schematic diagram illustrating storing data according to an adjusted tag configuration, according to an exemplary embodiment of the present invention;

FIG. 14 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the present invention;

FIG. 15 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the present invention;

FIG. 16 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the present invention;

fig. 17 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.

Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.

In an example embodiment, the host system 11 may be connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.

In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 by wire or wirelessly through the data transmission interface 114.

In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, Near Field Communication (NFC) memory storage, wireless fidelity (WiFi) memory storage, Bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 3, in an exemplary embodiment, the host system 31 may be a digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, or the like. The memory storage device 30 may be any of various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded memory device 34 includes various types of embedded memory devices such as an embedded multimedia Card (eMMC) 341 and/or an embedded Multi-Chip Package (eMCP) memory device 342, which directly connects the memory module to the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In an exemplary embodiment, the connection interface unit 402 is compatible with the PCI Express (Peripheral Component Interconnect Express) standard. In an exemplary embodiment, the connection interface unit 402 may also be compatible with Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standards, MMC interface standards, eMMC interface standards, Universal Flash Storage (UFS) interface standards, eMCP interface standards, CF interface standards, Integrated Device Electronics (IDE) standards, or other suitable standards. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is connected to the connection interface unit 402 and the rewritable nonvolatile memory module 406. The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may include a Single Level Cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a two-Level Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.

In an exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundancy bit region stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit region may include 8, 16 or more or less physical fans, and the size of each physical fan may be larger or smaller. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, and an error checking and correcting circuit 508.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.

In an exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In an exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In an exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 through a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.

The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512. The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.

In an example embodiment, the memory storage device 10 of fig. 4 is also referred to as a flash memory storage device, the rewritable non-volatile memory module 406 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a flash memory controller. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6, the memory management circuit 502 can logically group the physical units 610(0) -610 (B) in the rewritable nonvolatile memory module 406 into a storage region 601 and an idle region 602. In the present exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In another exemplary embodiment, a physical unit may also be composed of a plurality of consecutive or non-consecutive physical addresses.

The physical units 610(0) -610 (A) in the storage area 601 are used to store user data (e.g., user data from the host system 11 of FIG. 1). For example, entity units 610(0) -610 (A) in the storage area 601 may store valid (valid) data and invalid (invalid) data. The physical units 610(a +1) to 610(B) in the idle region 602 store no data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit may be associated (or added) to the idle region 602. In addition, the physical cells in the idle region 602 (or the physical cells not storing valid data) can be erased. When writing new data, a physical unit may be fetched from the idle area 602 to store the new data. In an exemplary embodiment, the idle region 602 is also referred to as a free pool.

The memory management circuitry 502 may configure the logic units 612(0) - (612 (C) to map the physical units 610(0) - (610 (A) in the memory area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a Logical Address may include one or more Logical Block Addresses (LBAs) or other Logical management units. In another exemplary embodiment, a logic unit may also correspond to a logic program unit or be composed of a plurality of continuous or discontinuous logic addresses. In addition, a logical unit may be mapped to one or more physical units. It should be noted that if a certain physical unit is currently mapped by a certain logical unit, it indicates that the data currently stored in the physical unit is valid data. Otherwise, if a certain entity unit is not currently mapped by any logic unit, it indicates that the data currently stored in the entity unit is invalid.

The memory management circuit 502 may record management data (also referred to as logic-to-entity mapping information) describing a mapping relationship between logical units and physical units in at least one logic-to-entity mapping table. When host system 11 is going to read data from memory storage device 10 or write data to memory storage device 10, memory management circuit 502 may perform data access operations with respect to memory storage device 10 according to the logical-to-physical mapping table.

FIG. 7 is a diagram illustrating writing new data according to an exemplary embodiment of the invention. Referring to fig. 7, after receiving a write command from the host system 11 to store data 701, the memory management circuit 502 may instruct the encoding circuit 71 to encode the data 701. Then, the memory management circuit 502 can instruct the rewritable nonvolatile memory module to store the data 701 encoded by the encoding circuit 71 into one of the entity groups 70(0) -70 (D) in the rewritable nonvolatile memory module 406. Each of entity groups 70(0) -70 (D) may include a plurality of entity units of FIG. 6. In an exemplary embodiment, one or more physical groups may also form a virtual block.

Encoding circuitry 71 may be included in error checking and correction circuitry 508 and may be used to perform encoding (and decoding) on data 701. It is noted that encoding circuitry 71 may perform RAID ECC encoding or similar multi-block (also referred to as cross-block) encoding (and decoding) operations on data 701. For example, in RAID ECC encoding or similar multi-block encoding operations, data 701 may be encoded across physical units (e.g., across physical program units) to generate parity data (i.e., global parity data) that may be used to protect multiple physical units (e.g., multiple physical program units) simultaneously. For example, the encoding circuit 71 may encode (and decode) data using encoding/decoding algorithms such as Reed-solomon code (RS code) and Exclusive OR (XOR). The data 701 encoded by the encoding circuit 71 and the global parity data generated by encoding the data 701 may be stored into a plurality of physical units having the same tag (also referred to as encoding tag). Thereafter, when reading data, if there is an error in the read data 701, the encoding circuit 71 may read the encoded data 701 and the corresponding global parity data from a plurality of physical units having the same tag and decode the read data 701 using the data to attempt to correct the error in the read data 701.

Fig. 8 is a diagram illustrating a tag configuration of a group of entities according to an example embodiment of the present invention. Referring to fig. 8, taking the entity group 70(i) of the entity groups 70(0) to 70(D) as an example, the memory management circuit 502 may pre-configure a Tag (also referred to as an initial Tag) for each entity unit of the entity group 70(i), for example, one of the tags Tag _0 to Tag _ 5. For example, the tag corresponding to each entity unit may be pre-stored in each entity unit or in the system management table before the memory storage device 10 or the rewritable nonvolatile memory module 406 leaves the factory. The tag may reflect the cross-frame encoding group to which each physical unit belongs. After performing RAID ECC encoding or similar multi-block encoding operations on the data, the encoded data and corresponding global parity data may be stored in multiple physical units having the same tag. Thereafter, data stored in multiple physical units having the same tag may be used in common to decode errors of data in one or more of the physical units.

In an example embodiment, a particular tag corresponds to a particular cross-frame encoding group. Different tags correspond to different cross-frame coding groups. Taking FIG. 7 as an example, the encoded data 701 and the global parity data generated by encoding the data 701 may be preset to be stored in the entity blocks 810(0) -810 (7) of the entity group 70(i) corresponding to the same Tag _ 0. For example, the encoded data 701 may be stored in segments in the physical units 810(0) -810 (6), and the global parity data generated by encoding the data 701 may be stored in the physical units 810 (7). When data 701 is subsequently required to be read from physical group 70(i), all or at least a portion of the data stored in physical units 810(0) -810 (7) may be used to decode data read from any of physical units 810(0) -810 (7), thereby attempting to correct errors in the read data. By analogy, some data that is encoded and corresponding parity data (i.e., global parity data) may be stored in multiple physical units corresponding to the Tag _ k, and k may be any integer from 0-5.

In an exemplary embodiment, if there are too many errors in the data in the physical units corresponding to Tag _ k in the physical group 70(i), the encoding circuit 71 may not be able to correct all the errors in the data read from a physical unit corresponding to the same Tag _ k.

In an example embodiment, if there are too many errors in the data in the plurality of physical units corresponding to the Tag _ k in the physical group 70(i), the memory management circuit 502 may update, adjust or change the configuration of the cross-frame coding group of the physical group 70(i) (e.g., a certain physical unit corresponding to the Tag _ k is exchanged with a certain physical unit corresponding to the Tag _ p, and k is not equal to p), so as to improve the reliability of the data stored in the physical group 70(i) later.

FIG. 9 is a diagram illustrating a high bit error rate physical unit in accordance with an exemplary embodiment of the present invention. Referring to fig. 9, taking Tag _0 as an example, if there are too many error bits (marked as HECC in fig. 9) in the data read from the physical units 810(3) and 810(5) corresponding to Tag _0, the errors in the data read from the physical units 810(3) and/or 810(5) may not be completely corrected. In this case, if the grouping configuration of the entity unit corresponding to Tag _0 is not dynamically adjusted, data read from the entity unit corresponding to Tag _0 cannot be successfully decoded, and even the entire entity group 70(i) cannot be used.

FIG. 10 is a diagram illustrating storage tag replacement information and moving data according to an exemplary embodiment of the invention. Referring to FIG. 10, in an exemplary embodiment, the memory management circuit 502 may select the entity group 70(i) from the entity groups 70(0) -70 (D) of FIG. 7. In a state where the entity group 70(i) has stored data, the memory management circuit 502 can send a read command sequence to the rewritable nonvolatile memory module 406 to instruct the rewritable nonvolatile memory module 406 to read data (also referred to as second data) from the entity group 70 (i). The memory management circuit 502 may store the tag replacement information 1001 according to a bit error condition of the second data. For example, the memory management circuit 502 may instruct the error checking and correcting circuit 508 (or the encoding circuit 71) to decode the second data and obtain a bit error condition of the second data according to the decoding result. For example, if the decoding result of the second data can reflect the bit error rate of the second data, the memory management circuit 502 can obtain the bit error condition of the second data according to the bit error rate of the second data. Then, the memory management circuit 502 may generate the tag replacement information 1001 according to the bit error condition of the second data. The memory management circuitry 502 may store tag replacement information 1001 in the buffer memory 510.

In an exemplary embodiment, the tag permutation information 1001 is used to perform tag permutation on at least two physical units in the physical group 70 (i). By the tag replacement, a tag originally pointing to an entity with a higher bit error rate (e.g., a bit error rate higher than a predetermined value) can be changed to point to another entity with a lower bit error rate (e.g., a bit error rate not higher than the predetermined value). In an exemplary embodiment, compared to always using a fixed tag configuration, dynamically adjusting the tag configuration (i.e., the cross-frame coded packet configuration) of at least some of the physical units in the physical group 70(i) can effectively improve the efficiency of decoding the data in the physical group 70(i) and/or prolong the service life of the physical group 70 (i).

In an example embodiment, the memory management circuit 502 may move the second data originally stored in the physical group 70(i) to another physical group 70(j) according to a bit error condition of the second data. The value of i is not equal to the value of j. For example, in the process of moving the second data, the second data can be read from the entity group 70(i) and decoded by the error checking and correcting circuit 508 (or the encoding circuit 71). The decoded second data may then be stored into the entity group 70 (j). After the second data is moved, the second data still stored in the entity group 70(i) can be marked as invalid and the entity group 70(i) can be erased.

In an example embodiment, the memory management circuit 502 may determine whether the bit error condition of the second data satisfies a specific condition. If the bit error condition of the second data meets a specific condition, the memory management circuit 502 may generate the tag replacement information 1001. However, if the bit error condition of the second data does not satisfy the specific condition, the memory management circuit 502 may not generate the tag replacement information 1001 and move the second data to the physical group 70 (j).

In an exemplary embodiment, the memory management circuit 502 may determine whether the bit error rate of the data read from a physical cell in the physical group 70(i) is higher than a predetermined value. If the bit error rate of the data read from a physical cell in the physical group 70(i) is higher than the predetermined value, the memory management circuit 502 can mark the physical cell, for example, mark the physical cell as the physical cell with the high bit error rate (marked HECC in fig. 9).

In an exemplary embodiment, the memory management circuit 502 may determine whether the total number of the physical units belonging to the high bit error rate among the plurality of physical units corresponding to the same Tag _ k in the physical group 70(i) is higher than or equal to a predetermined number. If the total number of the entity units belonging to the high bit error rate among the entity units corresponding to the same Tag _ k in the entity group 70(i) is higher than or equal to the predetermined number, the memory management circuit 502 may generate the Tag replacement information 1001 corresponding to the Tag _ k. On the contrary, if the total number of the entity units belonging to the high bit error rate among the entity units corresponding to the same Tag _ k in the entity group 70(i) is lower than the preset number, the memory management circuit 502 may not generate the Tag replacement information 1001.

Taking fig. 8 and fig. 9 as an example, assume that the predetermined number is 2. When detecting that the physical units 810(3), 810(5) all belong to the physical units with high bit error rate, the memory management circuit 502 may determine that the total number (e.g., 2) of the physical units belonging to the high bit error rate among the plurality of physical units corresponding to the Tag _0 in the physical group 70(i) is equal to the predetermined number (e.g., 2). Thus, memory management circuit 502 may generate Tag permutation information 1001 corresponding to Tag _ 0. The Tag replacement information 1001 corresponding to the Tag _0 may record information for swapping the tags corresponding to the entity units 810(3), 810(5) with higher bit error rates (i.e., Tag _0) with the tags corresponding to the other entity units with lower bit error rates.

Fig. 11 is a schematic diagram illustrating tag replacement according to an exemplary embodiment of the present invention. Referring to fig. 11, according to the Tag replacement information 1001, when storing data into the entity group 70(i), the Tag _0 corresponding to the entity unit 810(3) and the Tag _2 corresponding to the entity unit 1110(3) may be exchanged, and the Tag _0 corresponding to the entity unit 810(5) and the Tag _4 corresponding to the entity unit 1120(5) may be exchanged. Thus, when storing data into the entity group 70(i), the entity units 810(3) and 810(5) originally corresponding to Tag _0 and having higher bit error rates can be adjusted to correspond to tags Tag _2 and Tag _4, respectively, thereby preventing too many entity units having higher bit error rates from storing data corresponding to the same Tag _0 at the same time.

In other words, in an exemplary embodiment, the Tag replacement information 1001 may be used to distribute a plurality of physical units originally corresponding to the same Tag _ k and having a higher bit error rate for storing data corresponding to other Tag tags Tag _ p, where p is different from k. Thereby, the total number of error bits in the data corresponding to the same Tag _ k can be reduced.

FIG. 12 is a diagram illustrating writing new data according to an exemplary embodiment of the invention. Referring to fig. 12, continuing with the example embodiments of fig. 7-11, after storing the tag replacement information 1001 in the buffer memory 510, the memory management circuit 502 may receive a write command indicating the storage data 1201 (also referred to as the first data) from the host system 11. According to this write instruction, the memory management circuit 502 may instruct the encoding circuit 71 to encode the data 1201. On the other hand, the memory management circuit 502 can extract the erased entity group 70(i) from the idle area 602 of fig. 6 and read the tag replacement information 1001 corresponding to the entity group 70(i) from the buffer memory 510. The memory management circuit 502 can instruct the rewritable nonvolatile memory module to store the data 1201 encoded by the encoding circuit 71 into the entity group 70(i) in the rewritable nonvolatile memory module 406 according to the tag replacement information 1001.

Fig. 13 is a schematic diagram illustrating storing data according to an adjusted tag configuration according to an exemplary embodiment of the invention. Referring to fig. 13, continuing with the example embodiment of fig. 12, memory management circuitry 502 may store encoded data 1201 and parity data generated by encoding data 1201 (i.e., global parity data) into physical group 70 (i). For example, according to the Tag configuration preset by the entity group 70(i), the memory management circuit 502 may store a portion of the encoded data 1201 (also referred to as a first portion of data) in the entity units 810(0) -810 (2), 810(4), 810(6) pointed by the Tag _0 and store the global parity data corresponding to the data 1201 in the entity units 810 (7).

On the other hand, according to the Tag permutation information 1001, the memory management circuit 502 may store another portion of the encoded data 1201 (also referred to as a second portion of data) in the entity units 1110(3) and 1120(5) pointed to by the exchanged Tag _ 0. For example, the entity units 1110(3), 1120(5) are used to replace the entity units 810(3), 810(5) to which the Tag _0 is pre-assigned, so as to reduce the bit error rate of the cross-frame coding group to which the data 1201 belongs.

In an exemplary embodiment, the bit error rate of physical units 1110(3) is lower than that of physical units 810(3), and the bit error rate of physical units 1120(5) is lower than that of physical units 810 (5). Compared to the Tag configuration (i.e., the cross-frame encoded group configuration) preset for the physical group 70(i), performing Tag permutation according to the Tag permutation information 1001 and storing the encoded data 1201, the bit error rate of the data stored in all physical units corresponding to the Tag _0 can be effectively reduced. In addition, through the Tag replacement, the entity units 810(3) and 810(5) originally corresponding to Tag _0 and having higher bit error rates can be distributed and adjusted to store part of the data corresponding to tags Tag _2 and Tag _4, thereby avoiding the entity units having higher bit error rates from being over-concentrated in use.

In an example embodiment, during the process of storing the encoded data 1201 and corresponding global parity data to the physical units 810(0) -810 (2), 1110(3), 810(4), 1120(5), 810(6), and 810(7), the data fragment of the data 1201 may be stored in a data area (data area) in each physical unit. Meanwhile, the memory management circuit 502 may store the tag replacement information 1001 to an idle area (spare area) in the tag-replaced physical unit. For example, the memory management circuit 502 may store tag replacement information related to entity unit 1110(3) in the tag replacement information 1001 in a free area of entity unit 1110(3), store tag replacement information related to entity unit 1120(5) in the tag replacement information 1001 in a free area of entity unit 1120(5), store tag replacement information related to entity unit 810(3) in a free area of entity unit 810(3) in the tag replacement information 1001, and store tag replacement information related to entity unit 810 (1001) in a free area of entity unit 810(5) in the tag replacement information. Then, the memory management circuit 502 may delete the tag replacement information 1001 in the buffer memory 510. Thereafter, when reading data from the entity units 1110(3), 1120(5), 810(3) and/or 810(5), the memory management circuit 502 can know that the current entity units 1110(3) and/or 1120(5) are used for storing data belonging to the Tag _0 (data not preset to the Tag _2 or Tag _ 4) according to the Tag replacement information in the entity units 1110(3), 1120(5), 810(3) and/or 810(5), the current entity unit 810(3) is used for storing data belonging to the Tag _2 (data not preset to the Tag _0) and/or the current entity unit 810(5) is used for storing data belonging to the Tag _4 (data not preset to the Tag _ 0). In an exemplary embodiment, when the data 1201 is to be read from the physical group 70(i), the memory management circuit 502 may instruct the rewritable nonvolatile memory module 406 to read data from the physical units 810(0) -810 (2), 1110(3), 810(4), 1120(5), 810(6), and 810(7) and instruct the encoding circuit 71 to decode the read data.

In an example embodiment, when specific data is to be stored to or read from the entity group 70(i), the memory management circuit 502 may determine whether tag replacement information (e.g., tag replacement information 1001) corresponding to the entity group 70(i) exists. For example, the memory management circuitry 502 may determine whether tag permutation information (e.g., tag permutation information 1001) corresponding to the entity group 70(i) is present in the buffer memory 510. Alternatively, the memory management circuit 502 may determine whether the tag replacement information exists in one or more physical units currently storing the data or one or more physical units currently being read. If the memory management circuit 502 can obtain the tag replacement information corresponding to the entity group 70(i), indicating that the tag replacement information (e.g., tag replacement information 1001) corresponding to the entity group 70(i) exists, the memory management circuit 502 can perform the data access after tag replacement for the entity group 70(i) according to the tag replacement information (e.g., tag replacement information 1001) corresponding to the entity group 70 (i). The details of the related operations are already described above, and are not repeated herein. In addition, if the memory management circuit 502 cannot obtain the tag replacement information corresponding to the entity group 70(i), indicating that the tag replacement information (e.g., the tag replacement information 1001) corresponding to the entity group 70(i) does not exist, the memory management circuit 502 may access the entity group 70(i) according to the tag configuration preset for the entity group 70(i) (i.e., the group configuration of the preset cross frame coding).

In an example embodiment, the memory management circuit 502 may send a read command sequence to the rewritable nonvolatile memory module 406. This sequence of read instructions indicates that data (e.g., the second data) is to be read from the entity group 70 (i). The memory management circuitry 502 may adjust the configuration of the cross-frame encoding group of the physical group 70(i) based on the bit error condition of the second data. In particular, the cross-frame coding group is configured to reflect that a plurality of physical units in the physical group 70(i) belong to the same cross-frame coding group (and/or that a physical unit in the physical group 70(i) belongs to a cross-frame coding group). Thereafter, the memory control circuit unit 502 may access the entity group 70(i) according to the adjusted configuration of the cross-frame encoding group.

In an exemplary embodiment, adjusting the configuration of the cross-frame encoding group of the entity group 70(i) may be achieved by generating or recording the tag replacement information corresponding to the entity group 70(i) for later querying when accessing the entity group 70 (i). Details of how to generate and use the tag replacement information corresponding to the entity group 70(i) are described above, and are not repeated herein.

In an exemplary embodiment, adjusting the configuration of the cross-frame coding group of the entity group 70(i) may also include directly adjusting the group configuration of the cross-frame coding of the entity group 70(i) or directly adjusting an algorithm that generates the configuration of the cross-frame coding group of the entity group 70(i), thereby changing the preset configuration (or the current configuration) of the cross-frame coding group of the entity group 70(i) to be adjusted. In an example embodiment, the memory management circuitry 502 may or may not access the entity group 70(i) according to the adjusted configuration of the cross-frame encoding group of the entity group 70(i) by directly adjusting the configuration of the cross-frame encoding group of the entity group 70(i) or adjusting an algorithm that generates the configuration of the cross-frame encoding group of the entity group 70 (i).

From another perspective, in an example embodiment, for the same physical group 70(i), as the bit error condition (e.g., bit error rate) of at least some of the physical units in the physical group 70(i) changes, the tag configuration for data storage in the physical group 70(i) (i.e., the group configuration for cross-frame encoding) may be continuously changed. For example, in the example embodiments of fig. 7 and 8, the data stored in the entity group 70(i) is stored in a first tag configuration mode (also referred to as a first group configuration of cross-frame encoding). However, as the bit error rate of at least some of the physical cells in the physical group 70(i) changes, in the example embodiments of fig. 12 and 13, the data stored in the physical group 70(i) is changed to be stored in a second tag configuration mode (also referred to as a second group configuration of cross-frame encoding). By changing the configuration of the cross-frame encoding group of the entity group 70(i), the utilization efficiency of the entity group 70(i) can be effectively improved, the service life of the entity group 70(i) can be prolonged, and even the service life of the entire rewritable nonvolatile memory module 406 can be prolonged.

Fig. 14 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the invention. Referring to fig. 14, in step S1401, tag replacement information corresponding to the first entity group is read. In step S1402, the first data is encoded. In step S1403, a first part of the encoded first data is stored to at least one first entity unit corresponding to a certain tag information (also referred to as first tag information) in the first entity group. In step S1404, a second partial data of the encoded first data is stored to at least a second entity unit corresponding to another tag information (also referred to as a second tag information) in the first entity group according to the tag permutation information. It should be noted that the first tag information corresponds to a certain cross-frame coding group (also referred to as a first cross-frame coding group), the second tag information corresponds to another cross-frame coding group (also referred to as a second cross-frame coding group), and the first cross-frame coding group is different from the second cross-frame coding group.

For example, in FIG. 13, the first entity units may include entity units 810(0) -810 (2), 810(4), 810(6), and 810(7), and the second entity units may include entity units 1110(3), 1120 (5). The initial tags corresponding to the entity units 810(0) - (810 (2), 810(4), 810(6) (and 810(7)) are Tag _0, and the initial tags corresponding to the entity units 1110(3), 1120 (5)) are Tag _2 and Tag _4, respectively. The cross-frame coding group corresponding to the tags Tag _2 and Tag _4 is different from the cross-frame coding group corresponding to the Tag _ 0. However, after adjusting the configuration of the cross-frame coding group (e.g., referring to the tag replacement information 1001), the entity units 810(0) -810 (2), 810(4), 810(6), 810(7), 1110(3), and 1120(5) may be used to store data in the same cross-frame coding group. The details of the related operations are already described above, and are not repeated herein.

It should be noted that, in the foregoing exemplary embodiment, the total number of physical units included in each physical group, the preset tag configuration, and the adjusted tag configuration are only examples and can be adjusted according to practical requirements, and are not intended to limit the present invention. Furthermore, the tag replacement information (e.g. tag replacement information 1001) may record any relevant information that can be used to adjust the tag configuration, and the present invention is not limited to the specific content thereof.

Fig. 15 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the invention. Referring to fig. 15, in step S1501, one entity group is selected from a plurality of entity groups as a first entity group. In step S1502, data (i.e., second data) is read from the first entity group. In step S1503, it is determined whether the error bit status of the data meets a specific condition. If the error bit condition of the data meets a specific condition, in step S1504, tag replacement information corresponding to the first entity group is stored. If the error bit condition of the data does not meet the specific condition, the process returns to step S1501 to select another entity group as the first entity group.

After step S1504, in step S1505, the data is moved from the first entity group to another entity group (i.e., a second entity group) of the plurality of entity groups for storage. In step S1506, the first entity group may be erased.

Fig. 16 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the invention. Referring to fig. 16, in step S1601, a write command instructing to store first data is received. In step S1602, first data is encoded. In step S1603, it is determined whether tag replacement information corresponding to the first entity group exists. If the tag replacement information corresponding to the first entity group exists, in step S1604, the tag replacement information corresponding to the first entity group is read. In step S1605, a first portion of the encoded first data is stored to at least one first entity unit corresponding to the first tag information in the first entity group. In step S1606, the second part of the encoded first data is stored to at least one second entity unit corresponding to the second tag information in the first entity group according to the tag permutation information. In addition, if the determination in step S1603 is no, in step S1607, the encoded first data is stored (only) in the first entity units corresponding to the first tag information in the first entity group, without accessing the first entity group according to the tag replacement result.

Fig. 17 is a flowchart illustrating a cross-frame encoding management method according to an exemplary embodiment of the invention. Referring to fig. 17, in step S1701, a read command instructing to read first data is received. In step S1702, it is determined whether tag replacement information corresponding to the first entity group exists. If the tag replacement information corresponding to the first entity group exists, in step S1703, the tag replacement information corresponding to the first entity group is read. In step S1704, a first part of first data is read from at least one first entity unit corresponding to the first tag information in the first entity group. In step S1705, a second part of the first data is read from at least one second entity unit corresponding to the second tag information in the first entity group according to the tag replacement information. In addition, if the determination in step S1702 is negative, in step S1706, the first data is read from (only) the plurality of first entity units corresponding to the first tag information in the first entity group, without accessing the first entity group according to the tag replacement result. Thereafter, in step S1707, the read first data is decoded. The decoded first data may be returned in response to the read command.

However, the steps in fig. 14 to 17 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 14 to 17 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods of fig. 14 to 17 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.

In summary, the exemplary embodiments of the invention can dynamically change the tag configuration (i.e., the configuration of the cross-frame encoding group) of a specific entity group in the rewritable nonvolatile memory module according to the usage status (e.g., the wear-out level and/or the bit error status of each entity unit) of the entity group. By dynamically managing the configuration of the cross-frame coding group in the rewritable nonvolatile memory module, the utilization efficiency of the rewritable nonvolatile memory module can be effectively improved (for example, the error correction capability of data stored in the rewritable nonvolatile memory module is improved and/or the service life of the rewritable nonvolatile memory module is prolonged).

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cross-frame coding management method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module comprises a plurality of entity groups, each entity group in the entity groups comprises a plurality of entity units, and the cross-frame coding management method comprises the following steps:

reading tag permutation information corresponding to a first entity group of the plurality of entity groups;

encoding the first data;

storing a first portion of the encoded first data to at least a first entity unit of the first entity group corresponding to first tag information; and

storing a second part of the encoded first data to at least a second entity unit corresponding to second tag information in the first entity group according to the tag replacement information,

wherein the first tag information corresponds to a first cross-frame coding group, the second tag information corresponds to a second cross-frame coding group, and the first cross-frame coding group is different from the second cross-frame coding group.

2. The cross-frame encoding management method of claim 1, further comprising:

configuring tag information for each entity unit in the first entity group, wherein the tag information reflects a cross-frame coding group to which the each entity unit belongs.

3. The cross-frame encoding management method of claim 1, further comprising:

generating parity data according to an encoding result of the first data,

wherein the parity data is used to protect the first portion of the first data stored in the at least one first physical unit and the second portion of the first data stored in the at least one second physical unit.

4. The cross-frame coding management method of claim 1, wherein the step of storing the second part of the encoded first data to the at least one second entity unit corresponding to the second tag information in the first entity group according to the tag permutation information comprises:

exchanging the second label information corresponding to the at least one second entity unit with the first label information corresponding to at least one third entity unit in the first entity group according to the label replacement information; and

and storing the second part of data to the at least one second entity unit according to the label exchanging result.

5. The method according to claim 4, wherein the bit error rate of the at least one second physical unit is lower than the bit error rate of the at least one third physical unit.

6. The cross-frame coding management method of claim 1, wherein the step of storing the second part of the encoded first data to the at least one second entity unit corresponding to the second tag information in the first entity group according to the tag permutation information comprises:

storing the second portion of the encoded first data to a data area in the at least one second physical unit; and

and storing the label replacement information to an idle area in the at least one second entity unit.

7. The cross-frame encoding management method of claim 1, further comprising:

reading second data from the first group of entities prior to reading the tag permutation information corresponding to the first group of entities;

storing the tag replacement information according to a bit error condition of the second data;

moving the second data to a second entity group of the plurality of entity groups for storage; and

erasing the first entity group.

8. The cross-frame encoding management method of claim 7, wherein the step of storing the tag permutation information according to the bit error condition of the second data comprises:

in response to a bit error rate of data read from at least one third physical unit in the first physical group being higher than a preset value, storing the tag replacement information corresponding to the at least one third physical unit.

9. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

the memory module comprises a plurality of entity groups, wherein each entity group in the entity groups comprises a plurality of entity units; and

a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuitry unit is to read tag permutation information corresponding to a first physical group of the plurality of physical groups,

the memory control circuit unit is further configured to encode first data,

the memory control circuit unit is further configured to store a first portion of the encoded first data to at least a first entity unit of the first entity group corresponding to first tag information, and

the memory control circuit unit is further configured to store a second portion of the encoded first data to at least a second entity unit of the first entity group corresponding to second tag information according to the tag permutation information,

10. The memory storage device of claim 9, wherein the memory control circuitry unit is also to configure tag information for each physical unit in the first physical group, wherein the tag information reflects a cross-frame encoding group to which the each physical unit belongs.

11. The memory storage device of claim 9, wherein the memory control circuit unit is further to generate parity data according to an encoding result of the first data, and

the parity data is used to protect the first portion of the first data stored in the at least one first physical unit and the second portion of the first data stored in the at least one second physical unit.

12. The memory storage device of claim 9, wherein storing the second portion of the encoded first data to the at least a second entity unit of the first entity group corresponding to the second tag information according to the tag permutation information comprises:

13. The memory storage device of claim 12, wherein a bit error rate of the at least one second physical unit is lower than a bit error rate of the at least one third physical unit.

14. The memory storage device of claim 9, wherein storing the second portion of the encoded first data to the at least a second entity unit of the first entity group corresponding to the second tag information according to the tag permutation information comprises:

15. The memory storage device of claim 9, wherein the memory control circuitry unit is further to:

erasing the first entity group.

16. The memory storage device of claim 15, wherein storing the tag permutation information according to the bit error condition of the second data comprises:

17. A memory control circuit unit, configured to control a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of entity groups, each of the entity groups includes a plurality of entity units, and the memory control circuit unit includes:

a host interface for connecting to a host system;

a memory interface for connecting to the rewritable nonvolatile memory module;

an error checking and correcting circuit; and

memory management circuitry connected to the host interface, the memory interface, and the error checking and correcting circuitry,

wherein the memory management circuitry is to read tag permutation information corresponding to a first physical group of the plurality of physical groups,

the error checking and correcting circuit is used for encoding first data,

the memory management circuit is further configured to store a first portion of the encoded first data to at least a first physical unit of the first physical group corresponding to first tag information, and

the memory management circuit is also configured to store a second portion of the encoded first data to at least a second entity unit of the first entity group corresponding to second tag information according to the tag permutation information,

18. The memory control circuitry unit of claim 17, wherein the memory management circuitry is further to configure tag information for each physical unit in the first physical group, wherein the tag information reflects a cross-frame encoding group to which the each physical unit belongs.

19. The memory control circuit unit of claim 17, wherein the error checking and correcting circuit is further configured to generate parity data according to an encoding result of the first data, and

20. The memory control circuitry unit of claim 17, wherein the operation of storing the second portion of the encoded first data to the at least a second entity unit of the first entity group corresponding to the second tag information in accordance with the tag permutation information comprises:

21. The memory control circuit unit of claim 20, wherein the bit error rate of the at least one second physical unit is lower than the bit error rate of the at least one third physical unit.

22. The memory control circuitry unit of claim 17, wherein the operation of storing the second portion of the encoded first data to the at least a second entity unit of the first entity group corresponding to the second tag information in accordance with the tag permutation information comprises:

23. The memory control circuitry unit of claim 17, wherein the memory management circuitry is further to:

erasing the first entity group.

24. The memory control circuitry unit of claim 23, wherein the operation of storing the tag permutation information in accordance with the bit error condition of the second data comprises:

25. A memory storage device, comprising:

a connection interface unit for connecting to a host system;

wherein the memory control circuit unit is to send a read instruction sequence instructing to read second data from a first physical group of the plurality of physical groups,

the memory control circuit unit is further configured to adjust a configuration of a cross-frame coding group of the first physical group according to a bit error condition of the second data, where the configuration of the cross-frame coding group reflects that a plurality of physical units in the first physical group belong to the same cross-frame coding group, and

the memory control circuitry unit is also to access the first group of entities according to the adjusted configuration of the cross-frame encoding group.

26. The memory storage device of claim 25, wherein adjusting a configuration of the cross-frame encoding group of the first physical group according to the bit error condition of the second data comprises:

adjusting a configuration of the cross-frame encoding group of the first physical group in response to a bit error rate of data read from at least a third physical unit in the first physical group being higher than a preset value.

27. The memory storage device of claim 25, wherein adjusting a configuration of the cross-frame encoding group of the first physical group according to the bit error condition of the second data comprises:

exchanging a cross-frame coding group to which a part of the entity units in the first entity group belong with a cross-frame coding group to which another part of the entity units in the first entity group belong, so as to change the configuration of the cross-frame coding group of the first entity group.

28. The memory storage device of claim 27, wherein the operation of swapping a cross-box coding group to which the portion of physical units in the first physical group belongs with a cross-box coding group to which the other portion of physical units in the first physical group belongs comprises:

exchanging the tag information corresponding to the part of the entity units in the first entity group with the tag information corresponding to the other part of the entity units in the first entity group.

29. The memory storage device of claim 25, wherein accessing the first group of entities according to the adjusted configuration of the cross-frame encoding group comprises:

storing tag permutation information reflecting the adjusted configuration of the cross-frame encoding group of the first entity group; and

accessing the first group of entities according to the tag permutation information.