CN1134837C - 改进的多层导体结构及其形成方法 - Google Patents

改进的多层导体结构及其形成方法 Download PDF

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Publication number
CN1134837C
CN1134837C CNB981207073A CN98120707A CN1134837C CN 1134837 C CN1134837 C CN 1134837C CN B981207073 A CNB981207073 A CN B981207073A CN 98120707 A CN98120707 A CN 98120707A CN 1134837 C CN1134837 C CN 1134837C
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CN
China
Prior art keywords
layer
conductor
dielectric layer
dielectric
low capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB981207073A
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English (en)
Chinese (zh)
Other versions
CN1213170A (zh
Inventor
��˹��ŵ��
德克·托本
彼得·韦甘德
÷
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Infineon Technologies AG
Original Assignee
Siemens Corp
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Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of CN1213170A publication Critical patent/CN1213170A/zh
Application granted granted Critical
Publication of CN1134837C publication Critical patent/CN1134837C/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
CNB981207073A 1997-09-29 1998-09-23 改进的多层导体结构及其形成方法 Expired - Lifetime CN1134837C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US939208 1992-09-01
US939,208 1997-09-29
US08/939,208 US5977635A (en) 1997-09-29 1997-09-29 Multi-level conductive structure including low capacitance material

Publications (2)

Publication Number Publication Date
CN1213170A CN1213170A (zh) 1999-04-07
CN1134837C true CN1134837C (zh) 2004-01-14

Family

ID=25472743

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB981207073A Expired - Lifetime CN1134837C (zh) 1997-09-29 1998-09-23 改进的多层导体结构及其形成方法

Country Status (6)

Country Link
US (1) US5977635A (2)
EP (1) EP0905778A3 (2)
JP (1) JPH11163142A (2)
KR (1) KR100544030B1 (2)
CN (1) CN1134837C (2)
TW (1) TW393753B (2)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627539B1 (en) * 1998-05-29 2003-09-30 Newport Fab, Llc Method of forming dual-damascene interconnect structures employing low-k dielectric materials
US6153512A (en) * 1999-10-12 2000-11-28 Taiwan Semiconductor Manufacturing Company Process to improve adhesion of HSQ to underlying materials
US6780783B2 (en) * 2001-08-29 2004-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wet etching low dielectric constant materials
US20050070103A1 (en) * 2003-09-29 2005-03-31 Applied Materials, Inc. Method and apparatus for endpoint detection during an etch process
DE102005045059B4 (de) 2005-09-21 2011-05-19 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Spule sowie Verfahren zur Herstellung
DE102005045056B4 (de) 2005-09-21 2007-06-21 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Kondensator
WO2017099736A1 (en) * 2015-12-09 2017-06-15 Intel Corporation Dielectric buffer layer

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3074713B2 (ja) * 1990-09-18 2000-08-07 日本電気株式会社 半導体装置の製造方法
US5310700A (en) * 1993-03-26 1994-05-10 Integrated Device Technology, Inc. Conductor capacitance reduction in integrated circuits
KR950034755A (2) * 1994-05-27 1995-12-28
US5548159A (en) * 1994-05-27 1996-08-20 Texas Instruments Incorporated Porous insulator for line-to-line capacitance reduction
EP0703611B1 (en) * 1994-08-31 2007-05-02 Texas Instruments Incorporated Method for insulating metal leads using a low dielectric constant material, and structures formed therewith
US5559055A (en) * 1994-12-21 1996-09-24 Advanced Micro Devices, Inc. Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance
US5691573A (en) * 1995-06-07 1997-11-25 Advanced Micro Devices, Inc. Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines
US5847464A (en) * 1995-09-27 1998-12-08 Sgs-Thomson Microelectronics, Inc. Method for forming controlled voids in interlevel dielectric

Also Published As

Publication number Publication date
TW393753B (en) 2000-06-11
EP0905778A2 (en) 1999-03-31
KR19990030133A (ko) 1999-04-26
EP0905778A3 (en) 2001-02-07
US5977635A (en) 1999-11-02
CN1213170A (zh) 1999-04-07
JPH11163142A (ja) 1999-06-18
KR100544030B1 (ko) 2007-03-02

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Owner name: INFINEON TECHNOLOGIES AG

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Effective date: 20130225

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