CN113853582A - 向量索引寄存器 - Google Patents

向量索引寄存器 Download PDF

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Publication number
CN113853582A
CN113853582A CN202080037252.5A CN202080037252A CN113853582A CN 113853582 A CN113853582 A CN 113853582A CN 202080037252 A CN202080037252 A CN 202080037252A CN 113853582 A CN113853582 A CN 113853582A
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China
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vector
vir
ovr
output
count
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CN202080037252.5A
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Chinese (zh)
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S·J·沃勒克
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Micron Technology Inc
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Micron Technology Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G06F9/3555—Indexed addressing using scaling, e.g. multiplication of index

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
CN202080037252.5A 2019-05-20 2020-04-17 向量索引寄存器 Pending CN113853582A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/417,500 US11340904B2 (en) 2019-05-20 2019-05-20 Vector index registers
US16/417,500 2019-05-20
PCT/US2020/028798 WO2020236367A1 (fr) 2019-05-20 2020-04-17 Registres d'indices vectoriels

Publications (1)

Publication Number Publication Date
CN113853582A true CN113853582A (zh) 2021-12-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080037252.5A Pending CN113853582A (zh) 2019-05-20 2020-04-17 向量索引寄存器

Country Status (5)

Country Link
US (3) US11340904B2 (fr)
EP (1) EP3973386A4 (fr)
KR (1) KR102703934B1 (fr)
CN (1) CN113853582A (fr)
WO (1) WO2020236367A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119862077A (zh) * 2025-03-25 2025-04-22 山东云海国创云计算装备产业创新中心有限公司 一种PCIe功能的测试方法、设备、介质及产品

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11340904B2 (en) 2019-05-20 2022-05-24 Micron Technology, Inc. Vector index registers
US11327862B2 (en) 2019-05-20 2022-05-10 Micron Technology, Inc. Multi-lane solutions for addressing vector elements using vector index registers
US11507374B2 (en) 2019-05-20 2022-11-22 Micron Technology, Inc. True/false vector index registers and methods of populating thereof
US11403256B2 (en) 2019-05-20 2022-08-02 Micron Technology, Inc. Conditional operations in a vector processor having true and false vector index registers
US20260037262A1 (en) * 2024-07-31 2026-02-05 International Business Machines Corporation Single instruction register providing multiple instruction operands

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226171A (en) * 1984-12-03 1993-07-06 Cray Research, Inc. Parallel vector processing system for individual and broadcast distribution of operands and control information
US6334176B1 (en) * 1998-04-17 2001-12-25 Motorola, Inc. Method and apparatus for generating an alignment control vector
US20040153623A1 (en) * 2002-12-04 2004-08-05 Rainer Buchty Vector indexed memory unit and method
US20060184765A1 (en) * 2005-02-17 2006-08-17 Texas Instruments Incorporated Method and apparatus for producing an index vector for use in performing a vector permute operation
US7366873B1 (en) * 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
CN104838357A (zh) * 2012-12-27 2015-08-12 英特尔公司 瓦解的多嵌套循环的向量化
US20160179526A1 (en) * 2014-12-23 2016-06-23 Intel Corporation Method and apparatus for vector index load and store
CN107003843A (zh) * 2014-12-23 2017-08-01 英特尔公司 用于对向量元素集合执行约减操作的方法和设备
CN107003845A (zh) * 2014-12-23 2017-08-01 英特尔公司 用于在掩码寄存器和向量寄存器之间可变地扩展的方法和装置

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2665111B2 (ja) * 1992-06-18 1997-10-22 日本電気株式会社 ベクトル処理装置
US6269435B1 (en) 1998-09-14 2001-07-31 The Board Of Trustees Of The Leland Stanford Junior University System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector
WO2002037264A2 (fr) 2000-11-06 2002-05-10 Broadcom Corporation Systeme de traitement reconfigurable et procede
US7127593B2 (en) 2001-06-11 2006-10-24 Broadcom Corporation Conditional execution with multiple destination stores
GB2382673B (en) 2001-10-31 2005-10-26 Alphamosaic Ltd A vector processing system
US20100274988A1 (en) 2002-02-04 2010-10-28 Mimar Tibet Flexible vector modes of operation for SIMD processor
US6954841B2 (en) 2002-06-26 2005-10-11 International Business Machines Corporation Viterbi decoding for SIMD vector processors with indirect vector element access
US7793084B1 (en) 2002-07-22 2010-09-07 Mimar Tibet Efficient handling of vector high-level language conditional constructs in a SIMD processor
JP3659252B2 (ja) 2003-03-28 2005-06-15 セイコーエプソン株式会社 ベクトルデータのアドレス参照方法およびベクトルプロセッサ
US20080016320A1 (en) 2006-06-27 2008-01-17 Amitabh Menon Vector Predicates for Sub-Word Parallel Operations
US7676647B2 (en) 2006-08-18 2010-03-09 Qualcomm Incorporated System and method of processing data using scalar/vector instructions
US7962718B2 (en) * 2007-10-12 2011-06-14 Freescale Semiconductor, Inc. Methods for performing extended table lookups using SIMD vector permutation instructions that support out-of-range index values
US8793472B2 (en) 2008-08-15 2014-07-29 Apple Inc. Vector index instruction for generating a result vector with incremental values based on a start value and an increment value
GB2470782B (en) 2009-06-05 2014-10-22 Advanced Risc Mach Ltd A data processing apparatus and method for handling vector instructions
US20130212354A1 (en) 2009-09-20 2013-08-15 Tibet MIMAR Method for efficient data array sorting in a programmable processor
US8972698B2 (en) 2010-12-22 2015-03-03 Intel Corporation Vector conflict instructions
US20130185540A1 (en) 2011-07-14 2013-07-18 Texas Instruments Incorporated Processor with multi-level looping vector coprocessor
CN104011649B (zh) 2011-12-23 2018-10-09 英特尔公司 用于在simd/向量执行中传播有条件估算值的装置和方法
US9696994B2 (en) 2011-12-23 2017-07-04 Arm Limited Apparatus and method for comparing a first vector of data elements and a second vector of data elements
CN104094218B (zh) 2011-12-23 2017-08-29 英特尔公司 用于执行写掩码寄存器到向量寄存器中的一系列索引值的转换的系统、装置和方法
CN103999037B (zh) 2011-12-23 2020-03-06 英特尔公司 用于响应于单个指令来执行横向相加或相减的系统、装置和方法
US9588762B2 (en) 2012-03-15 2017-03-07 International Business Machines Corporation Vector find element not equal instruction
US9116686B2 (en) 2012-04-02 2015-08-25 Apple Inc. Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction
US9489199B2 (en) 2012-12-28 2016-11-08 Intel Corporation Vector compare instructions for sliding window encoding
US9244684B2 (en) 2013-03-15 2016-01-26 Intel Corporation Limited range vector memory access instructions, processors, methods, and systems
US10732689B2 (en) 2013-07-09 2020-08-04 Texas Instruments Incorporated Controlling the number of powered vector lanes via a register field
US9513907B2 (en) 2013-08-06 2016-12-06 Intel Corporation Methods, apparatus, instructions and logic to provide vector population count functionality
US9424039B2 (en) 2014-07-09 2016-08-23 Intel Corporation Instruction for implementing vector loops of iterations having an iteration dependent condition
US20160026607A1 (en) 2014-07-25 2016-01-28 Qualcomm Incorporated Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, and related circuits, methods, and computer-readable media
US9715386B2 (en) 2014-09-29 2017-07-25 Apple Inc. Conditional stop instruction with accurate dependency detection
US20160092398A1 (en) 2014-09-29 2016-03-31 Apple Inc. Conditional Termination and Conditional Termination Predicate Instructions
US20160124651A1 (en) 2014-11-03 2016-05-05 Texas Instruments Incorporated Method for performing random read access to a block of data using parallel lut read instruction in vector processors
US9946541B2 (en) * 2015-12-18 2018-04-17 Intel Corporation Systems, apparatuses, and method for strided access
US20170177359A1 (en) 2015-12-21 2017-06-22 Intel Corporation Instructions and Logic for Lane-Based Strided Scatter Operations
US20170177363A1 (en) 2015-12-22 2017-06-22 Intel Corporation Instructions and Logic for Load-Indices-and-Gather Operations
US10409613B2 (en) 2015-12-23 2019-09-10 Intel Corporation Processing devices to perform a key value lookup instruction
GB2553783B (en) 2016-09-13 2020-11-04 Advanced Risc Mach Ltd Vector multiply-add instruction
US11269638B2 (en) 2017-06-28 2022-03-08 Texas Instruments Incorporated Exposing valid byte lanes as vector predicates to CPU
US10970081B2 (en) 2017-06-29 2021-04-06 Advanced Micro Devices, Inc. Stream processor with decoupled crossbar for cross lane operations
US11436010B2 (en) 2017-06-30 2022-09-06 Intel Corporation Method and apparatus for vectorizing indirect update loops
EP3428792B1 (fr) 2017-07-10 2022-05-04 Arm Ltd Valeurs de bit d'essai à l'intérieur d'éléments vectoriels
US11042375B2 (en) 2017-08-01 2021-06-22 Arm Limited Counting elements in data items in a data processing apparatus
US20190205137A1 (en) 2017-12-29 2019-07-04 Lawrence Meadows Methods and apparatus for multi-load and multi-store vector instructions
US10929145B2 (en) 2018-12-28 2021-02-23 Intel Corporation Mask generation using reduction operators and scatter use thereof
US11507374B2 (en) 2019-05-20 2022-11-22 Micron Technology, Inc. True/false vector index registers and methods of populating thereof
US11340904B2 (en) 2019-05-20 2022-05-24 Micron Technology, Inc. Vector index registers
US11403256B2 (en) 2019-05-20 2022-08-02 Micron Technology, Inc. Conditional operations in a vector processor having true and false vector index registers
US11327862B2 (en) 2019-05-20 2022-05-10 Micron Technology, Inc. Multi-lane solutions for addressing vector elements using vector index registers
US10963247B2 (en) 2019-05-24 2021-03-30 Texas Instruments Incorporated Vector floating-point classification
US12254316B2 (en) 2020-08-28 2025-03-18 Altera Corporation Vector processor architectures

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226171A (en) * 1984-12-03 1993-07-06 Cray Research, Inc. Parallel vector processing system for individual and broadcast distribution of operands and control information
US6334176B1 (en) * 1998-04-17 2001-12-25 Motorola, Inc. Method and apparatus for generating an alignment control vector
US20040153623A1 (en) * 2002-12-04 2004-08-05 Rainer Buchty Vector indexed memory unit and method
US7366873B1 (en) * 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US20060184765A1 (en) * 2005-02-17 2006-08-17 Texas Instruments Incorporated Method and apparatus for producing an index vector for use in performing a vector permute operation
CN104838357A (zh) * 2012-12-27 2015-08-12 英特尔公司 瓦解的多嵌套循环的向量化
US20160179526A1 (en) * 2014-12-23 2016-06-23 Intel Corporation Method and apparatus for vector index load and store
CN107003843A (zh) * 2014-12-23 2017-08-01 英特尔公司 用于对向量元素集合执行约减操作的方法和设备
CN107003845A (zh) * 2014-12-23 2017-08-01 英特尔公司 用于在掩码寄存器和向量寄存器之间可变地扩展的方法和装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN119862077A (zh) * 2025-03-25 2025-04-22 山东云海国创云计算装备产业创新中心有限公司 一种PCIe功能的测试方法、设备、介质及产品

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Publication number Publication date
EP3973386A1 (fr) 2022-03-30
KR20210156854A (ko) 2021-12-27
US11941402B2 (en) 2024-03-26
US11340904B2 (en) 2022-05-24
EP3973386A4 (fr) 2023-06-28
US20200371802A1 (en) 2020-11-26
KR102703934B1 (ko) 2024-09-09
US20240231831A1 (en) 2024-07-11
US20220261253A1 (en) 2022-08-18
WO2020236367A1 (fr) 2020-11-26

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