CN114709172A - Memory system, three-dimensional memory and manufacturing method thereof - Google Patents

Abstract

Embodiments of the present disclosure provide a three-dimensional memory and a method of manufacturing the same. The present disclosure also provides a storage system. The three-dimensional memory includes an array device including a channel layer and a semiconductor layer connected to the channel layer. The manufacturing method of the three-dimensional memory comprises the following steps: forming a first buffer layer on the semiconductor layer; removing a portion of the first buffer layer to expose a portion of the semiconductor layer; forming a conductive layer on the exposed semiconductor layer; forming a second buffer layer to cover the conductive layer and the remaining first buffer layer; and forming a source contact penetrating the second buffer layer and the first buffer layer and extending to the conductive layer.

Description

Memory system, three-dimensional memory and manufacturing method thereof

Technical Field

Embodiments of the present application relate to the field of semiconductor manufacturing, and more particularly, to a memory system, and a three-dimensional memory and a method of manufacturing the same.

Background

As the number of layers of a 3D NAND stack increases, the process challenge for Array devices (Array) of 3D NAND increases. In a related 3D NAND structure, a plurality of array devices including a plurality of NAND memory strings are first formed on a first substrate, and then an array interconnect layer is formed on the plurality of NAND memory strings. Meanwhile, a second substrate is formed and a peripheral device is formed on the second substrate, and then a peripheral interconnection layer is formed on the peripheral device. Next, the array device is inverted and the array interconnect layer is aligned with the peripheral interconnect layer, combining the array interconnect layer and the peripheral interconnect layer. Then, the first substrate is removed, a source layer is formed on the array device, an N-well leading-out NPU (N well pick up) contact is formed on the source layer to lead out a source end, the NPU is connected with a top metal layer (connected to an external circuit) to form a diode structure, and therefore the array device and the external circuit can be electrically connected to achieve signal output.

The current signal flows from the NAND string to the source layer, and then to the external circuit through the NPU. The 3D NAND architecture well reduces technical difficulties in the Array process. However, in the related three-dimensional memory, the NPU is only used as a connection contact to lead OUT the core region well, and since the core region includes a plurality of memory strings, a plurality of NPU contacts need to be provided, and each NPU contact needs to be connected with the top metal layer and the interlayer interconnection contact to lead OUT, so that wiring in the interconnection layer is complicated, the difficulty in arranging other functional wirings is increased, and a new challenge is provided for a PAD OUT (PAD OUT) process. In addition, in order to save cost, in the conventional process, the metal layer in the NPU connecting hole is usually filled and etched back together with the metal layer in the TSC (Through Silicon Contact) hole, however, in practical application, the etching depth and the size of the NPU hole and the TSC hole are different, which causes the difficulty of the process for forming the TSC to be increased.

Disclosure of Invention

One or more embodiments of the present application provide a memory system, and a three-dimensional memory and a method of manufacturing the same, which may solve, at least in part, at least one of the above-mentioned disadvantages or other disadvantages of the related art.

An aspect of the present application provides a method of manufacturing a three-dimensional memory including an array device including a channel layer and a semiconductor layer connected to the channel layer, the method including: forming a first buffer layer on the semiconductor layer; removing a part of the first buffer layer to expose a part of the semiconductor layer; forming a conductive layer on the exposed semiconductor layer; forming a second buffer layer to cover the conductive layer and the remaining first buffer layer; and forming a source contact that penetrates the second buffer layer and the first buffer layer and extends to the conductive layer.

In one embodiment, the array device includes a core region and a non-core region located at a periphery of the core region, wherein removing a portion of the first buffer layer to expose a portion of the semiconductor layer includes: removing the first buffer layer to expose the semiconductor layer in the core region and the non-core region, respectively; and between the core region and the non-core region, removing a portion of the first buffer layer to further expose the semiconductor layer between the core region and the non-core region, wherein the further exposed semiconductor layer connects the exposed semiconductor layer within the core region and the non-core region.

In one embodiment, the conductive layer includes a conductive layer well region, a conductive layer lead-out region, and a conductive layer connection path connecting the conductive layer well region and the conductive layer lead-out region, wherein forming a conductive layer on the exposed semiconductor layer includes: and forming the conductive layer well region, the conductive layer lead-out region and the conductive layer connecting channel on the semiconductor layer exposed from the core region, the semiconductor layer exposed from the non-core region and the semiconductor layer exposed between the core region and the non-core region respectively.

In one embodiment, forming a source contact through the second buffer layer and the first buffer layer and extending to the conductive layer comprises: and penetrating through the second buffer layer and the first buffer layer and the part of the first buffer layer corresponding to the conducting layer leading-out area to form a source contact extending to the conducting layer.

In one embodiment, forming a source contact extending to the conductive layer through portions of the second buffer layer and the first buffer layer corresponding to the conductive layer lead-out region includes: forming a source contact hole penetrating through the second buffer layer and the first buffer layer at a portion corresponding to the conductive layer lead-out region; and forming the source contact extending to the conductive layer in the source contact hole.

In one embodiment, prior to forming a source contact extending through the second buffer layer and the first buffer layer and to the conductive layer, the method further comprises: and forming an isolation part penetrating through the second buffer layer, the first buffer layer and the semiconductor layer, wherein the isolation part divides the semiconductor layer into a semiconductor layer main body region and a semiconductor layer peripheral region, and the conductive layer is positioned in the semiconductor layer main body region.

In one embodiment, the three-dimensional memory further comprises a peripheral device bonded to the array device, the array device further comprising a through silicon contact therein connected to the peripheral device, the method further comprising: and forming a peripheral contact penetrating through the second buffer layer, the first buffer layer and the semiconductor layer and connected with the through silicon contact in the array device in the peripheral region of the semiconductor layer.

In one embodiment, the peripheral contact is formed in synchronization with the source contact.

In one embodiment, the material of at least one of the first buffer layer and the second buffer layer comprises a dielectric material.

Another aspect of the present application also provides a three-dimensional memory including an array device including a channel layer and a semiconductor layer connected to the channel layer, wherein the array device further includes: a conductive layer on the semiconductor layer; a buffer layer positioned over the conductive layer and the semiconductor layer covering regions of the conductive layer and the semiconductor layer not covered by the conductive layer; and the source contact is positioned on the conducting layer, penetrates through the buffer layer and is connected with the conducting layer.

In one embodiment, the array device includes a core region and a non-core region located at a periphery of the core region, and the array device further includes a plurality of memory string channel structures having the channel layer within the core region.

In one embodiment, the conductive layer comprises: the conducting layer well region is positioned in the core region and covers the semiconductor layer region corresponding to the storage string channel structure; the conducting layer leading-out area is positioned in the non-core area; and the conducting layer connecting channel is connected with the conducting layer well region and the conducting layer leading-out region.

In one embodiment, the source contact is connected to the conductive layer lead-out region.

In one embodiment, the material of the conductive layer comprises a metal or a metal silicide.

In one embodiment, the three-dimensional memory further comprises a peripheral device bonded to the array device, the array device further comprising a through silicon contact connected to the peripheral device, wherein the array device further comprises: a spacer penetrating the buffer layer and the semiconductor layer to separate the semiconductor layer into a semiconductor layer body region and a semiconductor layer peripheral region, wherein the conductive layer is located in the semiconductor layer body region; and the peripheral contact is positioned in the peripheral region of the semiconductor layer, penetrates through the buffer layer and the semiconductor layer and is connected with the through silicon contact.

In one embodiment, the peripheral contact and the source contact comprise the same material.

In one embodiment, the material of the buffer layer comprises a dielectric material.

Yet another aspect of the present application also provides a memory system comprising a controller and at least one three-dimensional memory as described above, wherein the controller is electrically connected to the at least one three-dimensional memory for controlling the at least one three-dimensional memory.

According to one or more embodiments of the present application, a conductive layer is formed on a semiconductor layer connected to a channel layer to serve as a high-speed conductive path, which is beneficial to reducing capacitance-resistance delay (RC delay), reducing power consumption, improving circuit speed, and improving electrical performance and operating efficiency of a three-dimensional memory.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

fig. 1 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present application.

FIG. 2 is a flow chart of a method of fabricating a three-dimensional memory according to one architecture of an exemplary embodiment of the present application;

FIGS. 3A-3H are process diagrams of a method of fabricating a three-dimensional memory of one architecture according to an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of a storage system according to an exemplary embodiment of the present application; and

FIG. 5 is a schematic diagram of a storage system according to another exemplary embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first buffer layer, such as discussed in this application, may also be referred to as a second buffer layer, and vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

Further, in this document, when it is described that one portion is "on" another portion, the meanings of "on … …", "above … …" and "above … …" for example, should be interpreted in the broadest manner such that "on … …" not only means "directly on something", but also includes the meaning of "on something" with an intermediate feature or layer therebetween, and "above … …" or "above … …" does not absolutely mean above with respect to the direction of gravity, nor only means "above something" or "above something", but may also include the meaning of "above something" or "above something" without an intermediate feature or layer therebetween (i.e., directly on something).

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

It should be noted that the X direction marked in the relevant figures herein may be a direction of the three-dimensional memory from the core region to the step region.

Further, in this application, when "connected" is used, it can mean either direct contact or indirect contact between the respective components, unless there is an explicit other limitation or one that can be inferred from the context.

FIG. 1 is a schematic diagram of a three-dimensional memory according to an embodiment of the present application. As shown in fig. 1, the three-dimensional memory may include an array device 10 and a peripheral device 20 bonded to each other, and portions thereof bonded to each other may be located at regions adjacent to both the array device 10 and the peripheral device 20. The array device 10 may include, for example, a stack structure 10-1 and a semiconductor layer 200, wherein the stack structure 10-1 may be formed of a plurality of insulating layers and a plurality of gate layers alternately stacked, and further, a memory string channel structure including a channel layer, which may be connected with the semiconductor layer 200, may be further formed in the stack structure 10-1. The array device 10 may further include a partition 600 penetrating the semiconductor layer 200, and the partition 600 may partition the semiconductor layer 200 into a body region and a peripheral region. A plurality of source contacts, such as 500-1, 500-2, may be located in the body region of the semiconductor layer 200. The peripheral region of the semiconductor layer 200 may include a peripheral contact 800 connected to the through-silicon contact 700 in the stack structure 10-1. The peripheral device 20 may include, for example, a second substrate 20-1, a transistor device located on the second substrate 20-1, and the like (not shown).

FIG. 2 is a flow chart of a method of fabricating a three-dimensional memory of one architecture according to an exemplary embodiment of the present application; fig. 3A-3H are process diagrams of a method of fabricating a three-dimensional memory of one architecture according to an example embodiment of the present application. Referring to fig. 2 and 3A-3H, a three-dimensional memory according to an embodiment of the present application may include an array device 10, and the array device 10 may include a plurality of memory string channel structures 100 having channel layers 110 and a semiconductor layer 200 connected to the channel layers 110 of the plurality of memory string channel structures 100. The semiconductor layer 200 may be, for example, polysilicon. The method 1000 for manufacturing the three-dimensional memory having such a structure according to the embodiment of the present application may include the steps of:

s1, forming a first buffer layer 301 on the semiconductor layer 200;

s2, removing a portion of the first buffer layer 301 until a portion of the semiconductor layer 200 is exposed;

s3, forming a conductive layer 400 on the exposed semiconductor layer 200;

s4, forming a second buffer layer 302 to cover the conductive layer 400 and the remaining first buffer layer 301; and

s5, a source contact 500 is formed through the second buffer layer 302 and the first buffer layer 301 and extending to the conductive layer 400.

It is understood that the three-dimensional memory may include the array device 10 and the peripheral device 20 which are separately formed and bonded to each other before the above-described step S1 is performed. The array device 10 may include, for example, a first substrate (not shown) and a stack structure 10-1 formed on the first substrate, and the core region of the stack structure 10-1 may include a plurality of memory string channel structures 100 extending longitudinally through the stack structure 10-1 and into the first substrate. It should be noted that the first substrate is removed in the final structure, and is not shown in the drawings. The peripheral device 20 may include, for example, a second substrate 20-1 and a transistor device (not shown) located on the second substrate 20-1. After the array device 10 and the peripheral device 20 are bonded, the first substrate of the array device 10 is removed, and the storage medium layer on the top of the storage string channel structure 100 is removed to expose the channel layer 110 of the storage string channel structure 100, and further a semiconductor layer 200 connected to the storage string channel structure 100 is formed on the back of the stack structure 10-1, and the channel layer 110 is connected to the semiconductor layer 200, as shown in fig. 3A.

The steps of the method 1000 for fabricating a three-dimensional memory will be described in detail with reference to fig. 3B to 3H.

According to step S1 of the method 1000, referring to fig. 3B, a first buffer layer 301 is formed on the semiconductor layer 200. The first buffer layer 301 may include a dielectric material. In one embodiment, the first buffer layer 301 may be an oxide layer, for example. The material of the first buffer layer 301 may include, for example, silicon oxide. In one embodiment, the first buffer layer 301 may be formed using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and the like. In one embodiment, before forming the first buffer layer 301 on the semiconductor layer 200, a planarization operation may be further performed on the upper surface of the semiconductor layer 200 to facilitate better deposition of the subsequent first buffer layer 301. For example, the upper surface of the semiconductor layer 200 may be planarized by Chemical Mechanical Planarization (CMP).

According to step S2 of the method 1000, referring to fig. 3C, a portion of the first buffer layer 301 is removed to expose at least a portion of the semiconductor layer 200. The array device 10 in the three-dimensional memory according to this embodiment may include a core region and a non-core region located at a periphery of the core region, and the plurality of memory string channel structures 100 included in the array device 10 may be located in the core region of the array device 10. A portion of the first buffer layer 301 may be removed to expose at least a portion of the semiconductor layer 200, that is, at least a portion of the first buffer layer 301 in the core region of the array device 10 is removed to expose at least a portion of the semiconductor layer 200 in the core region of the array device 10, as shown in fig. 3C, and the portion of the semiconductor layer exposed in the core region may be referred to as a semiconductor layer well region 200-1. In this step, at least a portion of the first buffer layer 301 may be removed as described, for example, using a dry/wet etch process. The first buffer layer 301 partially positioned in the non-core region of the array device 10 may be removed to expose a portion of the semiconductor layer 200 positioned in the non-core region of the array device 10, as shown in fig. 3C, and the portion of the semiconductor layer exposed in the non-core region may be referred to as a semiconductor layer drawing region 200-2. In this step, a portion of the first buffer layer 301 may be removed as described, again using, for example, a dry/wet etching process.

Between the semiconductor layer in the exposed core region (i.e., the semiconductor layer well region 200-1) and the semiconductor layer in the exposed non-core region (i.e., the semiconductor layer lead-out region 200-2), it is necessary to remove a portion of the first buffer layer 301 until at least one semiconductor layer connection via 200-3 is exposed, as shown in fig. 3C-1, and the semiconductor layer connection via 200-3 may connect the semiconductor layer in the exposed core region (i.e., the semiconductor layer well region 200-1) and the semiconductor layer in the exposed non-core region (i.e., the semiconductor layer lead-out region 200-2). It should be noted that fig. 3C-1 is a top view of the three-dimensional memory structure in fig. 3C, i.e., a view of the three-dimensional memory structure as viewed from top to bottom along the direction of arrow a shown in fig. 3C, and fig. 3C-1 only shows exemplary forms of the semiconductor layer well region 200-1, the semiconductor layer lead-out region 200-2, and the semiconductor layer connection channel 200-3, which is merely illustrative and not intended to limit the embodiments of the present application. In other words, the semiconductor layer well region 200-1, the semiconductor layer lead-out region 200-2, and the semiconductor layer connection channel 200-3 may have different sizes, shapes, connection forms, and the like from those shown in the drawings. Further, it should be noted that other parts or structures that may be included in this view are not shown in FIG. 3C-1 for simplicity. In this step, a portion of the first buffer layer 301 may be removed as described, again using, for example, a dry/wet etching process.

According to step S3 of the method 1000, in conjunction with fig. 3D, a conductive layer 400 is formed on the exposed semiconductor layer 200. In one embodiment, forming the conductive layer 400 on the exposed semiconductor layer 200 may include: a conductive layer well region 400-1, a conductive layer lead-out region 400-2 and a conductive layer connecting channel 400-3 are respectively formed on the semiconductor layer exposed in the core region, i.e., the semiconductor layer well region 200-1, the semiconductor layer exposed in the non-core region, i.e., the semiconductor layer lead-out region 200-2, and the exposed semiconductor layer connecting channel 200-3, as shown in fig. 3D-1, and the conductive layer connecting channel 400-3 is connected with the conductive layer well region 400-1 and the conductive layer lead-out region 400-2 to form a conductive layer 400. It should be noted that fig. 3D-1 is a top view of the three-dimensional memory structure in fig. 3D, i.e., a view of the three-dimensional memory structure as viewed from the top down along the direction of the arrow a' shown in fig. 3D, and fig. 3D-1 only shows exemplary forms of the conductive layer well region 400-1, the conductive layer lead-out region 400-2, and the conductive layer connecting channel 400-3, which are merely illustrative and not intended to limit the embodiments of the present application. In other words, the conductive layer well region 400-1, the conductive layer lead-out region 400-2, and the conductive layer connection channel 400-3 may have different sizes, shapes, connection forms, and the like from those shown in the drawings. Further, it should be noted that other parts or structures that may be included in this view are not shown in FIG. 3D-1 for simplicity.

In one embodiment, the material of the conductive layer 400 including the conductive layer well region 400-1, the conductive layer lead-out region 400-2, and the conductive layer connection channel 400-3 may include a metal or a metal silicide.

In one embodiment, a metal layer may be deposited on semiconductor layer 200 using, for example, Physical Vapor Deposition (PVD). The metal layer may be made of nickel (Ni) or cobalt (Co), and then subjected to two Rapid Thermal Annealing (RTA) treatments and one selective wet etching treatment to form a metal silicide on the surface of the semiconductor layer 200. In other embodiments, other suitable metal materials besides Ni or Co may be selected and deposited in other manners, which is not intended to be limiting. The metal silicide used as the conducting layer has lower resistance, so that the capacitance resistance delay (RC delay) is reduced, the power consumption is reduced, the circuit speed is improved, and the electrical performance and the working efficiency of the three-dimensional memory are improved.

Connection of the sources of at least a portion of the memory string channel structure 100 may be achieved by forming the conductive layer well region 400-1. In one embodiment, the conductive layer well region 400-1 may enable connection of the sources of all of the memory string channel structures 100 in the core region. The conductive layer connection channel 400-3 may connect the conductive layer well region 400-1 and the conductive layer lead-out region 400-2, and thus, at least a portion or all of the source electrode of the memory string channel structure 100 may be connected to the conductive layer lead-out region 400-2 through the conductive layer connection channel 400-3. As described later, the source contact 500 may be formed in the conductive layer lead-out region 400-2, so that at least a portion or all of the source of the memory string channel structure 100 may be connected to the conductive layer lead-out region 400-2 through the conductive layer connection channel 400-3, and may be led out from the source contact 500. The conductive layer lead-out region 400-2 is located in the non-core region of the array device 10, so that at least part or all of the source of the memory string channel structure 100 can be led out of the non-core region of the array device 10 through the conductive layer 400 and the source contact 500.

By routing the sources of multiple or all of the memory string channel structures 100 out of the non-core region of the array device 10, multiple source contacts can be routed efficiently through the conductive layer at the same time. On the one hand, the conductive layer formed by the metal silicide can have lower resistance, so that the voltage conduction is more effective and the power consumption is lower. On the other hand, the source electrodes of a plurality of or all of the memory string channel structures 100 are commonly connected to the conductive layer well region 400-1, so that signal conduction is more uniform, and meanwhile, the problems that wiring in an interconnection layer is complicated and the difficulty in arrangement of other function wirings in the core region is increased due to the fact that a plurality of source electrode contacts such as 500-1 and 500-2 need to be arranged in the core region and the plurality of source electrode contacts need to be respectively connected with a top metal layer and an interlayer interconnection contact to be led out in the embodiment shown in fig. 1 can be avoided, and more operation space can be reserved for the other function wirings.

According to step S4 of the method 1000, as shown in fig. 3E, the second buffer layer 302 is formed to cover the conductive layer 400 and the remaining first buffer layer 301. The second buffer layer 302 may include a dielectric material. In one embodiment, the second buffer layer 302 may be, for example, an oxide layer. The material of the second buffer layer 302 may be the same as that of the first buffer layer 301. The material of the second buffer layer 302 may include silicon oxide. In one embodiment, the second buffer layer 302 may be formed using a thin film deposition process such as CVD, PVD, or ALD. The first buffer layer 301 and the second buffer layer 302 may be collectively referred to as a buffer layer 300, and the buffer layer 300 appearing hereinafter refers to the first buffer layer 301 and the second buffer layer 302.

According to step S5 in method 1000, a source contact 500 is formed that extends through the second buffer layer 302 and the first buffer layer 301 and to the conductive layer 400. In one embodiment, the source contact 500 may be formed at the conductive layer draw-out region 400-2, as shown in fig. 3H.

When the source contact 500 is formed in the conductive layer drawing region 400-2, the source contact hole 501 may be formed in the conductive layer drawing region 400-2, and then the source contact 500 may be formed in the source contact hole 501. In one embodiment, the etching to form the source contact hole 501 may stop at the conductive layer of the conductive layer lead-out region 400-2, as shown in fig. 3F. That is, the conductive layer 400 may serve as a stop layer for etching in an etching operation for forming the source contact hole 501, so that the etching process may be optimized. In general, the peripheral Contact hole 801 corresponding to the TSC (Through Silicon Contact) and the source Contact hole 501 may be etched simultaneously in one process. However, there may be a difference in etching depth between the peripheral contact hole 801 and the source contact hole 501, for example, the peripheral contact hole 801 needs to penetrate through the buffer layer 300 and the semiconductor layer 200, and the source contact hole 501 needs to penetrate through the buffer layer 300, that is, the etching depth of the peripheral contact hole 801 is greater than that of the source contact hole 501, which may result in a complicated etching process. In contrast, according to the embodiment of the present application, since the conductive layer 400 is formed and the source contact hole 501 is formed over the region of the conductive layer 400, the etching of the source contact hole 501 may be automatically stopped on the conductive layer 400 in the process operation of simultaneously etching the peripheral contact hole 801 and the source contact hole 501, thereby simplifying the process. For example, in the present embodiment, the source contact hole 501 is etched on the conductive layer lead-out region 400-2, and the etching of the source contact hole 501 is automatically stopped from the conductive layer at the conductive layer lead-out region 400-2.

According to an embodiment of the present application, before the step of forming the source contact 500 extending to the conductive layer 400 through the second buffer layer 302 and the first buffer layer 301, an isolation portion 600 may be further formed through the second buffer layer 302, the first buffer layer 301, and the semiconductor layer 200, and the isolation portion 600 may separate the semiconductor layer 200 into a semiconductor layer body region 200a and a semiconductor layer peripheral region 200b, as shown in fig. 3G.

In forming the isolation 600, an isolation groove 601 may be formed to penetrate the second buffer layer 302, the first buffer layer 301, and the semiconductor layer 200, and then the isolation groove 601 may be filled with a filling material to form the isolation 600. The isolation trench 601 may be formed using, for example, a dry/wet etching process. In one embodiment, the isolation trench 601 may be formed in the same process step as the peripheral contact hole 801 and the source contact hole 501, as shown in fig. 3F, and as described above, the etching of the source contact hole 501 is stopped at the metal silicide layer 402 during the etching process, and the isolation trench 601 and the peripheral contact hole 801 penetrate through the buffer layer 300 and the semiconductor layer 200 to extend to the stack structure 10-1.

In one embodiment, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be employed to again deposit, for example, an oxide layer within the isolation trench 601 to fill the isolation trench 601 to form the isolation 600.

In one embodiment, a deposition layer (e.g., an oxide layer) formed within the source contact hole 501 and the peripheral contact hole 801 after the deposition process described above may be secondarily etched using, for example, a dry/wet etching process. For example, all of the oxide deposited within source contact hole 501 may be removed to restore source contact hole 501. For example, the deposited oxide in the central portion of the peripheral contact hole 801 may be removed, leaving a portion of the deposited oxide layer on the sidewalls of the peripheral contact hole 801 to form an insulating isolation between the peripheral contact hole 801 and the semiconductor layer 200, thereby allowing the subsequent formation of the peripheral contact 800 in the peripheral contact hole 801 to be insulated from the semiconductor layer 200.

As can be seen from fig. 3G, the isolation portion 600 divides the semiconductor layer 200 into two parts, i.e., a semiconductor layer main body region 200a located on the right side of the isolation portion 600 and a semiconductor layer peripheral region 200b located on the left side of the isolation portion 600. The conductive layer 400, including the conductive layer well region 400-1, the conductive layer lead-out region 400-2, and the conductive layer connection channel 400-3, are located in the semiconductor layer body region 200 a. The peripheral contact 800 is located in the semiconductor layer peripheral region 200 b.

As previously described, the peripheral device 20 bonded to the array device 10 may be included in the three-dimensional memory, and may also include a through silicon contact 700 that extends through the array device 10 and connects to the peripheral device 20, as shown in fig. 3G or fig. 3H. According to an embodiment of the present application, the method 1000 may further include: a peripheral contact 800 is formed through the second buffer layer 302, the first buffer layer 301, and the semiconductor layer 200 and connected to the through-silicon contact 700 in the array device 10. A peripheral contact 800 may be formed in the semiconductor layer peripheral region 200 b.

According to one embodiment of the present application, the peripheral contact 800 and the source contact 500 may be formed simultaneously. Referring again to fig. 3G and 3H, after the isolation portion 600 is formed, a peripheral contact hole 801 insulated from the semiconductor layer 200 and a source contact hole 501 extending through the buffer layer 300 to the conductive layer 400-2 are formed by the second etching in combination as described above, as shown in fig. 3G; a conductive metal, such as metal tungsten (W), may then be deposited within peripheral contact holes 801 and source contact holes 501 to form peripheral contact 800 and source contact 500, respectively, as shown in fig. 3H. Electrical signals in the peripheral device 20 may be connected to the peripheral contact 800 via the through silicon contact 700 and may be drawn out by the peripheral contact 800 at one side of the array device 10. The source of part or all of the memory string channel structure 100 is connected to the conductive layer well region 400-1, connected to the conductive layer lead-out region 400-2 through the conductive layer connection channel 400-3, and led out from the source contact 500 located on the conductive layer lead-out region 400-2 in the non-core region of the array device 10.

Another embodiment of the present application also provides a three-dimensional memory. For the sake of clarity, some technical features which are known or irrelevant in relation to the technical problem to be solved have been omitted from the description of the memory. Unlike the example shown in fig. 1, a three-dimensional memory according to another embodiment of the present application is described below with reference to fig. 3H.

As shown in fig. 3H, the array device 10 of the three-dimensional memory includes a plurality of memory string channel structures 100 having channel layers 110 and semiconductor layers 200 connected to the channel layers 110 of the plurality of memory string channel structures 100. The array device 10 of the three-dimensional memory may further include a conductive layer 400 positioned over the semiconductor layer 200 to cover a portion of the semiconductor layer 200, and a buffer layer 300 positioned over the conductive layer 400 and the semiconductor layer 200 to cover at least a portion of the conductive layer 400 and the semiconductor layer 200 not covered by the conductive layer 400, and further include a source contact 500 positioned over the conductive layer 400, penetrating the buffer layer 300, and extending to the conductive layer 400.

The array device 10 may be divided into a core region and a non-core region located at a periphery of the core region, and the plurality of memory string channel structures 100 are located at the core region of the array device 10. The conductive layer 400 may include a conductive layer well region 400-1, a conductive layer lead-out region 400-2, and a conductive layer connection channel 400-3. The conductive layer well region 400-1 is located in the core region and covers at least a portion of the semiconductor layer 200 corresponding to the memory string channel structure 100. The conductive layer lead-out region 400-2 is located in the non-core region. The conductive layer connection channel 400-3 is used to connect the conductive layer well region 400-1 and the conductive layer lead-out region 400-2.

The source contact 500 may be formed at the conductive layer lead-out region 400-2. The material of the conductive layer 400 may include a metal or a metal silicide. The array device 10 may further include: the isolation portion 600 may separate the semiconductor layer 200 into a semiconductor layer body region 200a and a semiconductor layer peripheral region 200b, through the buffer layer 300 and the isolation portion 600 of the semiconductor layer 200. The conductive layer 400 may be located in the semiconductor layer body region 200 a.

In one embodiment according to the present application, the three-dimensional memory may further include a peripheral device 20 bonded to the array device 10, and the array device 10 further includes a through silicon contact 700 penetrating the array device 10 and connected to the peripheral device 20. Among them, the array device 10 may further include: a peripheral contact 800 extending through the buffer layer 300 and the semiconductor layer 200 and connected to the through-silicon contact 700 in the array device 10. The peripheral contact 800 may be located in the semiconductor layer peripheral region 200 b. In one embodiment, the peripheral contact 800 and the source contact 500 may comprise the same material, such as metal tungsten. In one embodiment, the material of the buffer layer 300 may include a dielectric material, such as silicon oxide.

The peripheral device 20 may include, for example, a second substrate 20-1 and a transistor device (not shown) located on the second substrate 20-1. A side of the peripheral device 20 remote from the second substrate 20-1 may be formed with a peripheral interconnection layer, which may be bonded to an array interconnection layer of the array device 10 formed at the other side opposite to the buffer layer 300 to achieve electrical connection between the array device 10 and the peripheral device 20. The portion where the peripheral interconnect layer and the array interconnect layer are bonded to each other may be located in a region adjacent to both the array device 10 and the peripheral device 20 as shown in fig. 3H.

In summary, according to the three-dimensional memory of the embodiment of the present application, on one hand, the conductive layer well region 400-1 is formed in the core region of the array device 10, and is connected to the conductive layer lead-out region 400-2 located in the non-core region of the array device 10 by the conductive layer connection channel 400-3 for lead-out, so that the source of each channel structure in the core region can be led out through the conductive layer 400, and each well region does not need to be led out through a separate wiring such as a top metal interconnection layer, and the process can be significantly simplified. Meanwhile, the conductive layer 400 may be a metal silicide layer, which has lower resistance and better conductivity, so that voltage conduction may be more efficient, and it is also beneficial to make electrical signals more uniformly conducted to the plurality of well regions. In addition, the source contact 500 is disposed at a non-core area of the array device 10, so as to leave more space for disposing other interconnection traces with the outside world above the core area of the array device 10. On the other hand, the process of forming the peripheral contact hole 801 and the source contact hole 501 in the same process can be simplified. Since the source contact hole 501 is formed at a position corresponding to the conductive layer lead-out region 400-2 according to the present application, and the conductive layer lead-out region 400-2 may be a metal silicide layer and may serve as an etching stop layer for the source contact hole 501, the process difficulty of simultaneously etching the peripheral contact hole 801 and the source contact hole 501 may be reduced.

In yet another aspect, the present application further provides a storage system. Fig. 4 and 5 are schematic diagrams of storage systems 2000a and 2000b according to an embodiment of the present application. As shown in fig. 4 and 5, the storage system 2000a or 2000b may include at least one three-dimensional memory 2100 and a controller 2200, where the three-dimensional memory 2100 may be a three-dimensional memory provided according to any of the above-described embodiments of the present application, and may accordingly include the structure described according to any of the above-described exemplary embodiments of the present application, and will not be described herein again.

The controller 2200 may be electrically connected with the three-dimensional memory 2100 through, for example, a channel (not shown) and control the three-dimensional memory 2100, and the three-dimensional memory 2100 may perform operations based on the control of the controller 2200. Illustratively, the three-dimensional memory 2100 may receive commands and addresses from the controller 2200, e.g., via channels, and access regions of the channel structure responsive to the addresses. In other words, the three-dimensional memory 2100 may perform an internal operation corresponding to a command on a region selected by an address.

In some examples, the controller 2200 and the one or more three-dimensional memories 2100 may be integrated into various types of storage devices, in other words, the storage systems 2000a, 2000b may be implemented and packaged into different types of final electronic products. In one example as shown in fig. 4, the controller 2200 and the single three-dimensional memory 2100 may be integrated into a storage system 2200a in the form of a memory card. The memory card may include a PC card (PCMCIA, personal computer memory card international association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), and the like. The memory system 2200a in the form of a memory card may also include a memory card connector 2300a for coupling it with a host (not shown).

In another example as shown in fig. 5, the controller 2200 and the plurality of three-dimensional memories 2100 may be integrated into a storage system 2000b in the form of a Solid State Disk (SSD), for example. The Solid State Disk (SSD) may also include an SSD connector 2300b coupling it with the host.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (18)

1. A method for manufacturing a three-dimensional memory, the three-dimensional memory comprising an array device comprising a channel layer and a semiconductor layer connected to the channel layer, wherein the method comprises: forming a first buffer layer on the semiconductor layer; removing part of the first buffer layer to expose part of the semiconductor layer; forming a conductive layer on the exposed semiconductor layer; forming a second buffer layer to cover the conductive layer and the remainder of the first buffer layer; and A source contact is formed through the second buffer layer and the first buffer layer and extending to the conductive layer. 2. The method of claim 1, the array device comprising a core region and a non-core region surrounding the core region, wherein removing a portion of the first buffer layer to expose a portion of the semiconductor layer comprises: removing the first buffer layer to expose the semiconductor layer in the core region and the non-core region, respectively; and Between the core region and the non-core region, a portion of the first buffer layer is removed to further expose the semiconductor layer between the core region and the non-core region, wherein the further exposed semiconductor layer is connected to the The exposed semiconductor layers in the core region and the non-core region are described. 3. The method according to claim 2, wherein the conductive layer comprises a conductive layer well region, a conductive layer lead-out region, and a conductive layer connection channel connecting the conductive layer well region and the conductive layer lead-out region, Wherein, forming a conductive layer on the exposed semiconductor layer includes: on the semiconductor layer exposed in the core region, on the semiconductor layer exposed in the non-core region, and the semiconductor layer exposed between the core region and the non-core region On the above, the conductive layer well region, the conductive layer lead-out region and the conductive layer connection channel are respectively formed. 4. The method of claim 3, wherein forming a source contact through the second buffer layer and the first buffer layer and extending to the conductive layer comprises: A source contact extending to the conductive layer is formed through portions of the second buffer layer and the first buffer layer corresponding to the conductive layer lead-out regions. 5 . The method of claim 4 , wherein a source electrode extending to the conductive layer is formed through portions of the second buffer layer and the first buffer layer corresponding to the conductive layer lead-out regions. 6 . Contacts include: forming source contact holes penetrating portions of the second buffer layer and the first buffer layer corresponding to the conductive layer lead-out regions; and The source contact extending to the conductive layer is formed in the source contact hole. 6. The method of any one of claims 1-5, wherein prior to forming source contacts extending through the second buffer layer and the first buffer layer and extending to the conductive layer The method also includes: forming an isolation portion penetrating the second buffer layer, the first buffer layer and the semiconductor layer, the isolation portion separating the semiconductor layer into a semiconductor layer body region and a semiconductor layer peripheral region, and the conductive layer is located at the semiconductor layer body region. 7. The method of claim 6, wherein the three-dimensional memory further comprises a peripheral device bonded to the array device, the array device further comprising through-silicon contacts connected to the peripheral device, wherein, The method also includes: In the peripheral region of the semiconductor layer, peripheral contacts are formed through the second buffer layer, the first buffer layer and the semiconductor layer and connected with the through-silicon contacts in the array device. 8. The method of claim 7, wherein the peripheral contact is formed simultaneously with the source contact. 9. The method of claim 1, wherein the material of at least one of the first buffer layer and the second buffer layer comprises a dielectric material. 10. A three-dimensional memory, comprising an array device, the array device comprising a channel layer and a semiconductor layer connected to the channel layer, wherein the array device further comprises: a conductive layer on the semiconductor layer; a buffer layer over the conductive layer and the semiconductor layer covering the conductive layer and areas of the semiconductor layer not covered by the conductive layer; and A source contact, located on the conductive layer, penetrates through the buffer layer and is connected to the conductive layer. 11. The three-dimensional memory of claim 10, wherein the array device comprises a core region, and a non-core region located at the periphery of the core region, and Within the scope of the core region, the array device further includes a plurality of string channel structures having the channel layers. 12. The three-dimensional memory of claim 11, wherein the conductive layer comprises: a conductive layer well region, located in the core region, covering the semiconductor layer region corresponding to the memory string channel structure; a conductive layer lead-out region, located in the non-core region; and The conductive layer connection channel connects the conductive layer well region and the conductive layer lead-out region. 13. The three-dimensional memory of claim 12, wherein the source contact is connected to the conductive layer lead-out region. 14. The three-dimensional memory according to any one of claims 10-13, wherein the material of the conductive layer comprises metal or metal silicide. 15. The three-dimensional memory of any one of claims 10-13, further comprising a peripheral device bonded to the array device, the array device further comprising through-silicon contacts connected to the peripheral device, wherein , the array device further includes: an isolation part, penetrating the buffer layer and the semiconductor layer, separating the semiconductor layer into a semiconductor layer body region and a semiconductor layer peripheral region, wherein the conductive layer is located in the semiconductor layer body region; and A peripheral contact, located in the peripheral region of the semiconductor layer, penetrates the buffer layer and the semiconductor layer and is connected with the through-silicon contact. 16. The three-dimensional memory of claim 15, wherein the peripheral contact and the source contact comprise the same material. 17. The three-dimensional memory of claim 10, wherein the material of the buffer layer comprises a dielectric material. 18. A storage system, comprising: at least one three-dimensional memory as claimed in any one of claims 10-17; and The controller is electrically connected with at least one of the three-dimensional memories, and is used for controlling the at least one of the three-dimensional memories.

Images