CN114968356A

CN114968356A - Data processing method and device, processor and computing equipment

Info

Publication number: CN114968356A
Application number: CN202110527272.7A
Authority: CN
Inventors: 张嘉临; 麻鹏豪; 王哲
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-02-19
Filing date: 2021-05-14
Publication date: 2022-08-30

Abstract

The present application discloses a data processing method, which is applied to a processor, wherein the processor includes a single instruction multiple data stream computing unit, a compiler, an instruction decoder, and a microcode read-only memory, and the microcode read-only memory It is used to store the correspondence between the first instruction and the at least two sub-instructions. Then the method specifically includes: the compiler acquires the task of data processing and compiles the task into a first instruction; the instruction decoder acquires the first instruction, and according to the correspondence between the first instruction and at least two sub-instructions, converts the first instruction into the first instruction. An instruction is decomposed into sub-instructions; finally, the SIMD computing unit executes the sub-instructions to obtain the processing result of the data processing task. The vectorized calculation of complex mathematical tasks is realized through the cooperation between the compiler and the instruction decoder.

Description

Data processing method and device, processor and computing equipment

Technical Field

The present application relates to the field of computers, and in particular, to a data processing method, apparatus, processor, and computing device.

Background

With the increase of data volume and the improvement of real-time requirements, various High Performance Computing (HPC) applications put higher requirements on computing performance, and implementing vectorization computing by a Single Instruction Multiple Data (SIMD) computing unit is one of important methods. SIMD realizes simultaneous processing of a set of data (i.e., vectors) through a complex circuit, and when data is processed in batch, performance can be improved by multiple times in theory compared with single instruction single data stream (SISD), and any scenario requiring the same processing on a large amount of data can be used in SIMD technology to realize performance improvement, and HPC application is also included therein.

The instruction set of the processor is divided into a reduced instruction set and a complex instruction set from the aspect of architecture, compared with a CISC instruction set, the instruction number of the RISC instruction set is small, each instruction adopts the same byte length, is aligned on a word boundary, and the field position is fixed, so the RISC instruction set can greatly simplify the design of a controller and other functional units of the processor, does not need to use a large number of special registers, particularly allows the instruction operation to be realized by a hardware line, and further saves the manufacturing cost of the processor. However, in the context of SIMD computation, RISC does not have a hardware structure for directly implementing the corresponding function, and needs to rely on software to implement the corresponding function, and relatively complex mathematical computation such as nonlinear function computation in RISC instruction set is not implemented for a single instruction. Therefore, at present, the function of the vectorization function library on the processor is not complete, most of the four basic operations are performed, the problems of difficult function expansion, complex use, insufficient performance and the like exist, the advantages of the SIMD instruction set cannot be fully exerted in an HPC scene, and finally, the performance of the processor for realizing the calculation of the SIMD function is low.

At present, aiming at the problem that the SIMD instruction set on a processor adopting the RISC architecture mainly includes a Neon instruction set and a Scalable Vector Extension (SVE) instruction set, how to provide a method for utilizing the existing SIMD instruction set so that the processor can use the SIMD technology to process complex mathematical calculations becomes an urgent solution.

Disclosure of Invention

A method, apparatus, processor and computing device for data processing are provided, whereby the processor is enabled to process complex mathematical calculations using SIMD techniques.

In a first aspect, a method for data processing is provided, where the method is applied to a processor, where the processor includes a Single Instruction Multiple Data (SIMD) calculation unit, a compiler, an instruction decoder, and a microcode rom, and the microcode rom is used to store a correspondence between a first instruction and at least two sub-instructions, and then the method includes: first, a compiler acquires a task of data processing and compiles the task into a first instruction. Further, the first instruction is obtained by the instruction decoder, and the first instruction is decomposed into at least two sub-instructions according to the corresponding relation between the first instruction and the at least two sub-instructions. Then, the instruction decoder sends the sub-instructions to the SIMD computation unit, and finally the SIMD computation unit executes the sub-instructions to obtain the processing result of the task of data processing. By the method, the compiler and the instruction decoder can be cooperatively used, and the instruction decoder can decompose the complex instruction into the simple instruction according to the corresponding relation between the first instruction and the at least two sub-instructions, so that the time consumption of the instruction decoder for fetching the instruction is reduced, and the calculation speed is increased. Meanwhile, the data processing task can be converted into an instruction which can be executed by the SIMD computing unit of the processor, so that more complex computation can be realized by using the SIMD technology, and the complexity of hardware is reduced.

In one possible implementation, the first instruction is a first level instruction and the at least two sub-instructions are a second level instruction, wherein the first level instruction has a higher complexity of operation than the second level instruction, the SIMD computation unit supporting execution of the second level instruction. It should be noted that, the present application does not limit the number of the instruction hierarchy, and for example, the instruction may be divided into an existing instruction layer instruction, a basic computation layer instruction, a computation step layer instruction, and a function layer instruction, where the first instruction may be a function layer instruction, and correspondingly, the at least two sub-instructions may be at least two basic computation layer instructions, or at least two existing instruction layer instructions, or at least one existing instruction layer instruction and at least one computation step layer instruction.

In another possible implementation, the at least two sub-instructions include any one of a Neon instruction set and a Scalable Vector Extensions (SVE) instruction set. The instruction decoder supports the instructions responsible for decoding the instructions into the existing instruction set, which can be extended. The two sub-instructions may be at least two instructions in a Neon instruction set, at least two instructions in an SVE instruction set, at least one instruction in a Neon instruction set, and at least one instruction in an SVE instruction set.

In another possible implementation, the at least two sub-instructions further include an instruction consisting of at least two instructions in the Neon instruction set and the SVE instruction set. The two sub-instructions may be both instructions composed of at least two instructions in a Neon instruction set, or instructions composed of at least two instructions in a scalable proper amount extension instruction set, or instructions composed of at least one Neon instruction set and at least one scalable proper amount extension instruction set.

In another possible implementation manner, before the compiler compiles the data processing task into the first instruction, a function in a vectorization function library may be obtained first, where the vectorization function library includes a function corresponding to an operation of any one of the Neon instruction set and the SVE instruction set. By the method, the compiler can adopt different compiling strategies according to the relationship between the data processing tasks and the functions in the vectorization function library, and the requirements of tasks in different forms are met.

In another possible implementation manner, the vectorization function library further includes a function corresponding to an operation of an instruction composed of at least two instructions in the Neon instruction set and the SVE instruction set.

In another possible implementation manner, when a function included in the code of the task belongs to a function in the vectorized function library, the first instruction includes a vector instruction, and the compiler compiles the task into the first instruction, which specifically includes: the compiler compiles the task into vector instructions. By the method, when the functions in the vectorization function library are directly used in the codes of the tasks, the tasks can be compiled into the instructions which can use the SIMD technology by directly using the compiler.

In another possible implementation manner, when a function included in the code of the task does not belong to a function in the vectorized function library, the first instruction includes a first jump instruction and a vector instruction, and the compiler compiles the task into the first instruction, which specifically includes: the compiler compiles the task into a first jump instruction and compiles a function operating on the task in the vectorized function library into a vector instruction, the jump instruction pointing to an address of the vector instruction. By the above method, when a function in the vectorization function base is not used in the code of the task of mathematical processing, the compiler can compile the task of mathematical processing into a jump instruction, pointing to a function compiled instruction in the vectorization function base that is the same as the operation of the task of mathematical processing, thereby using the instruction of SIMD technology at the time of execution.

In another possible implementation manner, the first instruction further includes a batch data processing instruction, and the first jump instruction points to an address of the batch data processing instruction, and the method further includes: the compiler compiles the batch data processing function into a batch data processing instruction, wherein the batch data processing instruction comprises a second jump instruction, and the second jump instruction points to an address of the vector instruction. With the above method, the input data of the data processing is preprocessed by first executing the batch data processing instruction before executing the vector instruction.

In another possible implementation, the task of data processing includes the calculation of an elementary function or the calculation of a non-linear function.

In another possible implementation, the hierarchy of instructions is divided into existing instruction layer instructions, basic computation layer instructions, computation step layer instructions, and function layer instructions, from simple to complex, according to the complexity of the corresponding operations. The SIMD compute units of the processor support instructions for the base compute layer, and the microcode ROM supports decode of compute step layers to the base compute layer and compute step layers to existing instruction layers. The method of calculating ln (x) includes: the compiler compiles the source code of ln (x) task into a first jump instruction, and at the same time, the compiler compiles the ln (x) function in the vectorization function library into instructions at the computation step layer, namely a multiplication reduction instruction, an approximation instruction and a range reconstruction instruction, wherein the first jump instruction points to the address of the multiplication reduction instruction. The instruction decoder obtains the above instructions, and in cooperation with the microcode rom 106, decomposes the multiply-reduce instruction into an extract exponent bit instruction and an extract mantissa bit instruction and decodes them to generate corresponding SIMD control signals, decomposes the approximate instruction into a polynomial approximation instruction and decodes them to generate corresponding SIMD control signals, and decomposes the range reconstruction instruction into a floating point addition instruction and a floating point multiply instruction and decodes them to generate corresponding SIMD control signals. And finally, executing the instructions of the existing instruction layer by the SIMD computing unit respectively to obtain the computing results of ln (x). By the method, the existing SIMD instruction can be expanded, the instruction of the basic operation layer is directly realized by using a hardware circuit, the calculation speed is improved, and meanwhile, the micro instruction is combined into the complex instruction of the calculation step layer by using the microcode read-only memory, so that the calculation time consumed by instruction fetching is further reduced, and the calculation speed is improved.

In another possible implementation, the hierarchy of instructions is divided into existing instruction layer instructions, base compute layer instructions, compute step layer instructions, and function layer instructions, from simple to complex, according to the complexity of the corresponding operations. The SIMD compute unit of the processor supports only instructions of the base compute layer, and the microcode ROM supports only decoding of instructions of the base compute layer into an existing instruction layer. The method of calculating ln (x) includes: the compiler compiles the source code of ln (x) task into a first jump instruction, and at the same time, the compiler compiles the ln (x) function in the vectorization function library into instructions of a basic computing layer, namely an exponent bit instruction, a digit extraction instruction, a polynomial approximation instruction, a floating point addition instruction and a floating point multiplication instruction, wherein the first jump instruction points to the address of the digit extraction instruction. The instruction decoder respectively obtains the instructions, decodes the exponent digit extracting instruction, the polynomial approximation instruction, the floating point number addition instruction and the floating point number multiplication instruction to generate corresponding SIMD control signals, and respectively executes the SIMD control signals by the SIMD computing unit to obtain the computed result of ln (x). By the method, the existing SIMD instruction can be expanded, the instruction of the basic operation layer is directly realized by using a hardware circuit, and the calculation speed is improved.

In another possible implementation, the hierarchy of instructions is divided into existing instruction layer instructions, basic computation layer instructions, computation step layer instructions, and function layer instructions, from simple to complex, according to the complexity of the corresponding operations. The SIMD compute unit of the processor supports only instructions of the existing instruction layer, i.e., existing SIMD instructions, and the microcode ROM supports the decoding of the compute step layer to the existing instruction layer. The method of calculating ln (x) includes: the compiler compiles ln (x) functions in the vectorization function library into instructions at the computation step level, i.e., a multiply-reduce instruction, an approximate instruction, and a range-reconstruct instruction, with a first jump instruction pointing to the address of the multiply-reduce instruction. The instruction decoder respectively obtains the instructions, and the instruction decoder is cooperated with the microcode read-only memory to sequentially decompose the instructions of the calculation step layer into the instructions of the existing instruction layer, specifically: the instruction decoder, in cooperation with the microcode ROM, decomposes the multiply-reduce instruction into an instruction and a shift instruction and decodes the instruction to generate a corresponding SIMD control signal, decomposes the approximate instruction into an FMA instruction and decodes the FMA instruction to generate a corresponding SIMD control signal, and decomposes the range reconstruction instruction into a floating point addition instruction and a floating point multiply instruction and decodes the floating point add instruction to generate a corresponding SIMD control signal. And finally, executing the instructions of the existing instruction layer by the SIMD computing unit respectively to obtain the computing results of ln (x). By the method, the existing SIMD instruction can be expanded, the instruction of the basic operation layer is directly realized by using a hardware circuit, and the calculation speed is improved.

In another possible implementation, the hierarchy of instructions is divided into existing instruction layer instructions, basic computation layer instructions, computation step layer instructions, and function layer instructions, from simple to complex, according to the complexity of the corresponding operations. Assuming that the SIMD compute units of the processor only support instructions of the existing instruction layer, the microcode ROM does not support decoding. The method of calculating ln (x) includes: the compiler compiles the source code of ln (x) task into a first jump instruction, and at the same time, the compiler compiles the ln (x) function in the vectorization function library into instructions of the existing instruction layer, namely an AND instruction, a shift instruction, an FMA instruction, a floating-point addition instruction and a floating-point multiplication instruction, wherein the first jump instruction points to the address of the AND instruction. The instruction decoder respectively obtains the instructions, decodes the instructions, the shift instruction, the bit instruction, the FMA instruction, the floating point addition instruction and the floating point multiplication instruction and generates corresponding SIMD control signals, and the SIMD control signals are respectively executed by the SIMD computing unit to obtain the computed result of ln (x). By the method, the hardware of the processor is not optimized for data processing, and all levels of operations are realized by a compiler. The function design of the hierarchical operation not only ensures the integrity and the expansibility of the operation of each layer, but also the user can respectively control the specific flow of the operation of each layer to complete the optimization of the details of the data processing.

In a second aspect, a data processing apparatus is provided, which includes a compiling unit, a decoding unit, an executing unit, and a storage unit, and includes modules for executing the method of the first aspect or any one of the possible implementations of the first aspect.

In a third aspect, a processor is provided, which includes a SIMD computation unit, an instruction decoder, a microcode rom, and a compiler, where the SIMD computation unit, the instruction decoder, the microcode rom, and the compiler are respectively configured to perform the operation steps of the method performed by the corresponding main body in any one of the possible implementations of the first aspect or the first aspect.

In a fourth aspect, a computing device for data processing is provided, which includes a processor and a memory, wherein the memory is used for storing a vectorization function library, and the processor includes a SIMD computing unit, a compiler, an instruction decoder, and a microcode read-only memory. The SIMD computation unit, the instruction decoder, the microcode rom and the compiler may each be adapted to perform the operational steps of the method performed by the corresponding subject matter of the first aspect or any one of the possible implementations of the first aspect.

The present application can further combine to provide more implementations on the basis of the implementations provided by the above aspects.

Drawings

Fig. 1 is a schematic structural diagram of a data processing computing device 100 according to an embodiment of the present application;

fig. 2 is a hardware structure diagram of a processor 10 for data processing according to an embodiment of the present application;

fig. 3 is a schematic flowchart of a method for data processing according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a layering of 4-layer operations as proposed by an embodiment of the present application;

FIG. 5 is a diagram illustrating a function of the 4-layer ln (x) operation proposed in an embodiment of the present application;

fig. 6 is a schematic flowchart of a method for implementing data processing of ln (x) according to an embodiment of the present application;

fig. 7 is a schematic diagram of a data processing apparatus 700 according to an embodiment of the present application.

Detailed Description

The technical solution in the embodiment of the present application is described below with reference to the accompanying drawings, and fig. 1 is a schematic structural diagram of a computing device 100 for data processing provided in the embodiment of the present application, and as shown in the figure, the computing device 100 includes a processor 10, a memory 20, and a bus 30. The processor 10 and the memory 20 are connected by a bus 30, where the bus 30 may be a data bus, a power bus, a control bus, a status signal bus, or the like, and the bus may also be a bus for realizing connection between devices in a computing device of other types.

The source code of the application is used to store instructions for tasks that require data processing, which are typically written in a high-level language and stored in the memory 20 for ease of use and to maintain high readability by the user.

The memory 20 is used for storing data and instructions for the operation of the application program, and the memory 20 may include a read-only memory and a random access memory, and may also include a nonvolatile random access memory.

The memory 20 may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example but not limitation, many forms of RAM are available, such as static random access memory (static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and direct bus RAM (DR RAM).

Compiler 50 runs in processor 10. Since the processor cannot recognize and execute instructions written in a high-level language, the compiler 50 is configured to convert the instructions in the high-level language used in the data processing task into instructions represented by binary codes and store the instructions in the memory 20. The processor 10 obtains the calculation result of the data processing by fetching the instruction of the calculation task from the memory 20 and executing it. The processor 10 may be a Central Processing Unit (CPU) or other general purpose processor, and the processor 10 may be a processor using an ARM architecture or other architecture that employs a RISC instruction set.

Fig. 2 is a hardware structure diagram of a data processing processor 10 provided in this embodiment, which may further illustrate a flow of instructions of the data processing processor 10 to execute tasks issued by an application program.

As shown in fig. 2, the processor 10 includes a memory address register 101, a memory data register 102, a program counter 103, an instruction register 104, an instruction decoder 105, a microcode rom 106, an operation controller 107, a computation unit 108, a general purpose register 109, an accumulator 110, a status register 111, a timing circuit 112, and a processor bus 120. The processor bus 120 may be a data bus, a power bus, a control bus, a status signal bus, or the like.

In the processor 10, the memory address register 101 and the memory data register 102 are used to hold an address of the memory 20 currently accessed by the processor 10, and data read or written from the address and an instruction read or written from the address by the processor 10, respectively, so as to compensate for a difference in operating speed between the processor and the memory.

Timing circuit 112 provides a time reference for each component by a fixed clock, and processor 10 executes an instruction for one instruction cycle. The program counter 103 is used for storing the address of the next instruction, and when the instructions are executed sequentially, the program counter 103 automatically adds the byte number of one instruction after each instruction is taken; when a branch instruction is encountered, the program counter 103 specifies the address of the next instruction by means of an address code field in the branch instruction. Instruction register 104 is used to hold the currently executing instruction. The instruction includes two fields, an opcode portion and an address code, the opcode portion being decoded by instruction decoder 105 to generate the control potentials for the operation required by the instruction. The operation controller 107 can generate various operation control signals according to the control potential signal output by the instruction decoder and the timing signal generated by the timing circuit 112, and control the rest of the components of the processor 10 to perform the operations of fetching and executing instructions.

The microinstruction is the smallest unit of the processor to execute the instruction, and one instruction may be a single microinstruction, or may be composed of several microinstructions, for example, an instruction to pop data stored in the register ebx, and may be composed of a load instruction, a store instruction, and an add instruction, where the load instruction, the store instruction, and the add instruction are all microinstructions, and the following code:

the instruction composed of multiple micro instructions is called complex instruction, the steps of the micro instructions corresponding to the complex instruction are stored in the microcode read-only memory 106, the instruction decoder 105 can inquire and obtain the operation code and address code of the micro instructions forming the complex instruction from the microcode read-only memory 106 in the decoding process, and the operation code part of the micro instructions is decoded in sequence to generate the control potential required by the micro instructions.

The general register set 109 is used for storing data corresponding to the address code according to the address code of the instruction. The calculation unit 108 is configured to receive an operation control signal from the operation controller 107 and perform calculations on data stored in the general register set 109, including arithmetic operations (including basic operations such as addition and subtraction of multipliers and additional operations thereof) and logical operations (including shifting, logical testing, or two-value comparison). Temporary variables generated during the calculation are stored in the accumulator 110, and generated state information, such as an operation result in/out flag (C), an operation result overflow flag (O), an operation result zero flag (Z), an operation result negative flag (N), and an operation result sign flag (S), is stored in the program state word register 111. The program status word register is also used to store information such as interrupts and computing device operating status so that the processor 10 can know the machine operating status and the program operating status in a timely manner.

The computing unit 108 includes various circuit modules, which can be respectively used for executing different instructions. In particular, in an instruction where a SIMD instruction is used to perform both arithmetic and logical operations on a vector, then, correspondingly, the compute unit 108 also includes a SIMD compute unit 1081 for executing the SIMD instruction.

The following describes the steps of executing a SIMD instruction by a processor, taking an instruction cycle as an example, and specifically includes the following steps:

1) initialization program counter 103: the address of an instruction in the memory 20, which may be a SIMD instruction or a complex instruction composed of multiple SIMD instructions, is specified by the program counter 103.

2) Instruction fetching: instructions are fed from the memory data register 102 to the instruction register 104 via the processor bus 120, in accordance with the address of the program counter 103 and control signals of the operation controller 107.

3) Instruction decoding: the instruction decoder 105 fetches an instruction from the instruction register 104, and determines whether the instruction is a complex instruction. When the instruction is a complex instruction, the instruction decoder 105 queries and obtains the operation code and the address code of the SIMD instruction constituting the complex instruction from the microcode rom 106; when the instruction is a simple instruction, the instruction decoder 105 directly obtains the operation code and address code of the SIMD instruction. In accordance with the operation code of the SIMD instruction, the instruction decoder 105 generates a control potential for an operation required by the instruction, and supplies it to the operation controller 107, and the operation controller 107 generates different SIMD operation control signals.

4) Executing the instructions: according to the difference of the operation code of the instruction, the operation controller 107 generates different SIMD operation control signals to control different components of the processor 10 to complete the operation of the instruction. For example, when the instruction is a read data instruction, the data corresponding to the address code of the SIMD instruction is sent from the memory data register 102 to the general register set 109 through the processor bus 120 in coordination with the operation control signal of the operation controller 107. The length of each general purpose register is fixed, being the maximum number of elements that a SIMD instruction can execute. For another example, when the instruction is an addition instruction of SIMD, the calculation unit 108 acquires two data from the general-purpose register set 109, calls the SIMD calculation unit to complete the calculation, and saves the calculation result in the general-purpose register set 109. If the addition operation produces a result that exceeds the size of data that the processor can handle, an operation result overflow flag is set in the program status word register 111.

5) Writing back the calculation result: the results of the operation are written into the processor's memory data register 102 for quick access by subsequent instructions.

6) Update program counter 103: the address of the next instruction is generated in the program counter 103.

The SIMD computation unit 1081 can execute different SIMD instructions according to different hardware circuits, and the hardware circuit of the existing SIMD computation unit 1081 is relatively simple and can be used for executing SIMD instructions of basic four-way operations. The present embodiment can use customized complex hardware circuits in the SIMD computation unit 801 according to user requirements, and directly receive complex instructions sent by the operation controller 107, without decoding the instructions into different SIMD instructions through the microcode rom 106. For complex instructions, the customized SIMD computing unit only needs to execute one instruction, so that the number of clock cycles required by the operation can be reduced, and the operation time can be shortened.

By the method, the calculation speed can be improved by directly realizing the complex instruction through a hardware circuit, and the method of combining a plurality of SIMD instructions into one complex instruction can be adopted, so that the clock period number of an instruction fetching stage and an instruction decoding stage is reduced without modifying the hardware circuit of a calculation unit. The user can select an appropriate method according to the needs and actual conditions of the calculation task, and the calculation speed and the hardware complexity of the processor are balanced.

The method for processing data provided in the embodiment of the present application will be described with reference to fig. 3 to 6, and fig. 3 is a flowchart illustrating a method for processing data provided in the embodiment of the present application, which can be executed using the processor 10 shown in fig. 1 or fig. 2. As shown in the figure, the specific method comprises:

s301, the compiler 50 determines the hierarchy of instructions that the SIMD computation unit can execute.

When the SIMD computation unit 1081 completes the computation, the compiler may convert the tasks of the data processing into instructions that can be executed using the SIMD computation unit 1081 by vectorization implementation. Vectorization refers to a programming method that allows instructions to be applied to an entire set of data at the same time, and operations in the source code of an application that require data processing using vector computations are compiled by a compiler into instructions that include SIMD instructions as well as complex instructions consisting of SIMD instructions. When the instruction is executed, the instruction decoder 105, in cooperation with the microcode rom 106, generates a control potential for data processing operations to instruct the SIMD computation unit to complete the computation.

The functions that can be realized by instructions in the existing SIMD instruction set are not abundant, so that the realization of data processing such as complex elementary functions and nonlinear functions can be expanded on the existing SIMD instruction set. Specifically, an operation of one data processing may be composed of a plurality of sub-operations, each of which can implement a partial operation of the data processing. According to the execution complexity, the operation can be divided into a plurality of levels, wherein the operation of the lowest level is the operation of the instructions in the existing SIMD instruction set, including the Neon instruction set and the SVE instruction set, and the operation of the high level is obtained by combining a plurality of operations of the low level. Through layering, the existing SIMD instruction combination of the lowest level can be utilized to complete the operation of the high level, thereby realizing the vectorization of the operation of the high level corresponding to the complex data processing. In the embodiments of the present application, the number of layers is not limited.

Fig. 4 is a schematic diagram of a hierarchy of 4-level operations, which are proposed in the embodiment of the present application, and the hierarchy is an existing instruction layer, a basic computation layer, a computation step layer, and a function layer from low to high. As shown in fig. 4, the operations of the existing instruction layer are all operations of instructions in the existing SIMD instruction set, such as and operation, bit operation, shaping division operation, shaping multiplication operation, shaping subtraction operation, and Fused Multiply Add (FMA) operation. The operations of the base compute layer may consist of operations of an existing instruction layer, for example, both the extract exponent bit operation and the extract mantissa bit operation may consist of an AND operation and a shift operation; the shaping and modulus-taking operation consists of shaping division operation, shaping multiplication operation and shaping subtraction operation; polynomial approximation operations are represented by FMA; the coefficient calculation operation is composed of a subtraction operation and a shift operation. Further, each operation of the computation step layer may in turn be composed of operations of the underlying computation layer, respectively, e.g., a multiplicative reduction operation may be composed of a decimated exponent bit operation and a decimated mantissa bit operation; the additive reduction operation may consist of an exponent bit extraction operation, a mantissa bit extraction operation, and a shaping modulo operation; the approximation operation and the interpolation operation may be constituted by a polynomial approximation operation and a coefficient calculation operation, respectively; the operations at the computation step level may also consist directly of operations at the existing instruction level, e.g., the range reconstruction operation consists directly of a floating point addition operation and a floating point multiplication operation. The operation of the function layer may then be combined from three operations of the computation step layer, namely a range reduction operation, an approximation operation (or interpolation operation), and a range reconstruction operation. The range reduction operation is used for reducing the input A into a certain numerical range through multiplication or addition, the multiplication reduction can be performed by exponent expansion with the base 2, the addition reduction can be performed by a floating point number remainder method, and the value after the scaling is recorded as C; the approximation operation or interpolation operation is used for obtaining a value D of the numerical value C after the expression calculation of the data processing through table lookup in a numerical range, when no value corresponding to the numerical value C exists in the table, the number E closest to the numerical value C is found by using an approximation or interpolation method, and the value D of the numerical value E after the expression calculation of the data processing is obtained through table lookup; the range reconstruction operation is used to obtain an output B using the value D through an operation opposite to the range reduction. The final function layer is a complex elementary function or an expression of a nonlinear function, and the output B of the input A after data processing can be directly obtained.

The code implementing the operation may be packaged as a function and stored in a vectorized function library, which may in turn be stored in memory 20. Each function is compiled by a compiler into an instruction that, when executed, performs the function's operation. For example, a function implementing the coefficient calculation operation may be compiled into a coefficient calculation instruction by a compiler, and the level of the instruction is the same as the level of the operation implemented by the corresponding function, that is, the function implementing the high-level operation is compiled to obtain the high-level instruction. According to the combination relationship between the operations, the high-level operation can be realized by calling a function of the low-level operation in the function. The function of the low-level operation receives the data of the high-level parameters and returns a calculation result to the function of the high-level, and the data between the functions are calculated and transmitted by taking the vector as a unit. Therefore, according to the calling relationship among the functions, each high-level function can be compiled into a plurality of low-level instructions by a compiler, and the operation of the function can be realized when all the low-level instructions are executed. For example, the function that implements the coefficient calculation operation may also be compiled by a compiler as a combination of a subtraction instruction and a shift instruction.

The hierarchical manner of the function of the 4-level operation is further described below by taking specific data processing as an example. Fig. 5 is a schematic diagram of a function of an ln (x) operation with 4 layers according to an embodiment of the present application, taking the hierarchical manner in fig. 3 as an example, as shown in fig. 5, in the conventional instruction layer, the and operation, the shift operation, the FMA operation, the floating-point addition operation, and the floating-point multiplication operation are packaged into an op _ and (x) function, an op _ move (x) function, an op _ FMA (x) function, an op _ fadd (x), and an op _ fmul (x) function, which are all functions capable of implementing the operation of the conventional SIMD instruction. At the base compute level, the decimate exponent bits, decimate mantissa bits, and polynomial approximations are encapsulated as v _ exendex (x) functions, v _ ex (x) functions, and v _ polyapprox (x) functions, respectively, each of which may call a function of an existing SIMD instruction. At the computation step level, the multiplicative reduction operation, the approximation operation, and the range reconstruction operation are packaged as a v _ mulreduce (x) function, a v _ approx (x) function, and a v _ construct (x) function, respectively. The v _ mulreduce (x) function can call the v _ index (x) function and the v _ ex (x) function in turn to decompose the operation into a decimation exponent bit operation and a decimation mantissa bit operation, and the v _ appprox (x) function can call the v _ polyappprox (x) function to decompose the operation into a plurality of polynomial approximation operations. Similarly, the function of the computation step layer may also directly call the function operated by the existing SIMD instruction, for example, the v _ constraint (x) function may call the op _ fadd (x) and the op _ fmul (x) functions. The operation of the function layer is packaged as a v _ ln (x) function, and provides a complete ln (x) function calculation function. Three functions are called in sequence in the v _ ln (x) function to decompose ln (x operation into a multiplication reduction operation, an approximation operation and a range reconstruction operation.

Among the instructions of different levels, the instruction of the level where the existing SIMD instruction is located may directly instruct the SIMD computation unit 1081 to complete the computation, while the instructions of other levels may be executed in two ways, specifically:

the first method is as follows: the hardware circuitry of custom SIMD compute unit 1081 executes instructions of a specified level.

Since the high-level instruction is composed of a plurality of low-level instructions, the number of clock cycles required for operation can be reduced and the operation time can be shortened by directly executing the high-level instruction, so that in the hardware design stage, the hardware circuit of the SIMD calculation unit 1081 can be designed according to the time required for data processing, so that the SIMD calculation unit 1081 can directly execute the control signal sent by the instruction of the specified level, and at this time, the instruction of the level is a microinstruction which can be added into a SIMD instruction set and is called an expanded SIMD instruction. While the SIMD computation unit 1081 may directly execute instructions at a specified level, or may directly execute instructions at a level below the specified level, these instructions will also be added to the SIMD instruction set as an expanded SIMD instruction.

The second method comprises the following steps: the SIMD instructions that SIMD computation unit 1081 may execute are generated by microcode read-only memory 106.

The microcode read-only memory 106 can store the step of the microinstruction corresponding to the complex instruction, and the instruction decoder 105 can query and obtain the operation code and the address code of the microinstruction forming the complex instruction from the microcode read-only memory 106 in the decoding process, and decompose the complex instruction into the SIMD instruction, thereby indicating the SIMD computing unit to complete the computation. By combining microinstructions to implement high-level instructions, the number of clock cycles in the fetch and decode stages can be reduced, the operation speed can be increased, and the hardware circuit of the SIMD calculation unit 1081 does not need to be changed. Therefore, in the hardware design stage, the decomposition mode of the instruction of the specified hierarchy can be preset in the microcode read-only memory 106 according to the time required for data processing, so that the SIMD calculation unit 1081 can process the instruction of higher hierarchy. It should be noted that, the SIMD instructions that the SIMD computation unit 1081 can execute here include existing SIMD instructions and extended SIMD instructions, which are collectively referred to as SIMD instructions in the following description for convenience of description. When the resolution of instructions at a given level is stored in microcode rom 106, or the resolution of instructions below the given level is stored in microcode rom 106, SIMD computation unit 1081 may cooperate with instruction decoder 106 to process instructions at the given level and instructions below the given level together.

Before the processor performs data processing, the hierarchy of SIMD instructions, as well as the hierarchy of supported complex instructions, may be stored by microcode read-only memory 106 as a hierarchy of instructions that SIMD compute unit 1081 may process, according to the SIMD compute unit and the microcode read-only memory.

S302, the compiler 50 generates an instruction according to the instruction hierarchy.

According to the highest value of the hierarchy of instructions that the SIMD computation unit 1081 can process, which is obtained in S201, the compiler 50 may obtain the source code of a task of data processing that needs vectorization, and compile the task into an instruction having a hierarchy not higher than the highest value, which is referred to as a first threshold value in the following description for convenience of description. There are two scenarios:

scene one: the function in the vectorized function library of the operation of the data processing is directly called in the source code of the task.

When the level of the operation of the data processing is not higher than the first threshold, the compiler 50 compiles the function into an instruction of the corresponding level. When the level of the operation of the data processing is higher than the first threshold, the compiler 50 compiles the functions of the lower-level operation layer by layer in the order from high to low according to the call relationship between the function and other functions determined in step S201 until the level of the operation corresponding to the function of the lower-level operation is not higher than the first threshold, and finally compiles the function into a plurality of instructions with the level as the first threshold.

Taking the hierarchical manner of operations in fig. 5 as an example, assuming that the first threshold is the basic computation layer, when data processing is polynomial approximation, a v _ polyapprox (x) function may be directly called in the code of the data processing, and then a compiler directly generates a polynomial approximation instruction, the hierarchy of which is the basic computation layer. When data is processed into ln (x), a function v _ ln (x) can be called directly in the code of data processing, the compiler compiles a function v _ mulreduce (x), a function v _ approx (x) and a function v _ construct (x) according to the calling relation in the function v _ ln (x), and compiles a function v _ exendex (x) and a function v _ ex (x) called by the function v _ mulreduce (x), and a function v _ approx (x) called by the function v _ approx (x), and a function op _ fade (x) and a function op _ fmul (x) called by the function v _ construct (x). Since the operation levels of the v _ index (x), v _ ex (x), v _ polyapprox (x), op _ fadd (x) function and op _ fmul (x) function are not higher than the first threshold, the compiler stops the compilation and finally generates the exponent bit instruction, the decimation bit instruction, the polynomial approximation instruction, the floating point addition instruction and the floating point multiplication instruction.

Scene two: the function in the vectorized function library of the operation of the data processing is not called in the source code of the task.

The code may be scanned using an optimization tool such as a compiler or a parallel programming model (e.g., OpenMP), and a block of the code that needs to be vectorized for data processing is identified, and the functions in the vectorized function library operated by the data processing are compiled into vector instructions by the compiler 50 according to the method of scene one. The compiler 50 then compiles the identified code blocks into a first jump instruction that points to an address of an instruction of the vector instructions that is preferentially executed. Then when the first jump instruction is executed, the first jump instruction can jump to the preferentially executed instruction in the vector instructions to complete the vectorized data processing. For example, assuming that the first threshold is the basic computation layer, when v _ ln (x) function execution data processing ln (x) is called in the original code, the GNU C compiler may be used to activate the automatic vectorization function through the free-vector compilation option, so that the compiler 50 automatically recognizes the data processing that needs vectorization, and compiles v _ ln (x) in the vectorization function library into an exponent bit extraction instruction, a digit extraction instruction, a polynomial approximation instruction, a floating point addition instruction, and a floating point multiplication instruction according to the method one. The compiler then compiles ln (x) in the source code into a first jump instruction br addr, wherein addr is an address of an instruction preferentially executed in the exponent bit instruction, the decimation bit instruction, the polynomial approximation instruction, the floating point addition instruction and the floating point multiplication instruction, namely the address of the decimation exponent bit instruction. The automatic vectorization replacement of non-vectorization data processing in the original code can be completed through the optimization tool, the vectorization acceleration of a larger proportion can be realized without code reconstruction, and the method is suitable for application of high-performance calculation developed and perfected in a large amount of time.

Optionally, in the case of scenario two, a batch data processing function may be added to the vectorization function library for preprocessing the input data. The batch data processing function may receive an address and a length of input data to be calculated in data processing, split the large block of input data into a plurality of vectors, and transfer the input data to the function in units of vectors by calling the function in the vectorization function library by the operation of data processing. In addition, the batch data processing function can also receive the calculation results of the functions operated by the data processing in the vectorization function library and aggregate the calculation results of the vectors of the plurality of input data into a final calculation result. In the compiling stage, the compiler 50 compiles the batch data processing function into a batch data processing instruction, the function called in the batch data processing function is compiled into a vector instruction, and the batch data processing instruction includes a second jump instruction for pointing to the address of the vector instruction. The compiler 50 points the first jump instruction to the address of the batch data processing instruction. Then when the instruction is executed, the instruction which is preferentially executed in the batch data processing instruction can be executed by the first jump instruction jump, and then the vector instruction is executed by the second jump instruction jump.

S303, the instruction decoder 105 decodes the instruction, and generates an SIMD control signal.

In step S302, the instruction generated by the compiler 50 is stored in the memory 20, and when the instruction is executed, the instruction is sequentially sent to the memory data register 102 and the instruction register 104 according to the address in the program counter 103, and finally the instruction decoder 105 acquires the instruction from the instruction register 104.

When the instruction level is equal to or lower than the SIMD instruction level obtained in step S301, the instruction decoder 105 independently decodes and issues a SIMD control signal to the SIMD computation unit 1081 via the operation controller 107. When the instruction level is higher than that of the SIMD instruction obtained in step S201, the instruction decoder 105 searches the microcode rom to obtain the SIMD instruction after the instruction decomposition, decodes the SIMD instruction, and sends a SIMD control signal to the SIMD calculation unit 1081 through the operation controller 107.

When the instruction is a normal instruction, the instruction decoder 105 decodes the normal instruction and sends a control signal to the remaining computing units or other components of the computing unit 108 through the operation controller 107.

S304, the SIMD computing unit 1081 receives the SIMD control signal and then executes the computation to obtain the computation result.

By the data processing method, a user can divide the boundary between software execution and hardware execution according to the data processing requirement and the capacity of the SIMD computing unit. The compiler can be used for compiling the data processing tasks into instructions which can be executed by the SIMD computing unit, the complexity of hardware is reduced, the instruction generated by the compiler can be executed in a manner of realizing the decomposition of the complex instruction by using the customized complex SIMD computing unit and the customized microcode read-only memory, and the computing speed is improved.

The method of execution of the data processing of the present application is further illustrated below in four specific computational examples. In an example one, the data processing task is to calculate the result of ln (x), and the operation layering method of fig. 5 is adopted, assuming that the SIMD computation unit 1081 of the processor supports the instructions of the basic computation layer, and the microcode rom supports the decoding of the computation step layer to the basic computation layer and the computation step layer to the existing instruction layer, according to S301 and S302, the compiler compiles the source code of the ln (x) task into a first jump instruction, and at the same time, the compiler compiles the ln (x) function in the vectorization function library into the instructions of the computation step layer, that is, the multiplication reduction instruction, the approximation instruction, and the range reconstruction instruction, and the first jump instruction points to the address of the multiplication reduction instruction. Fig. 6 is a schematic flowchart of a method for implementing data processing of ln (x) provided in an embodiment of the present application, and as shown in fig. 6, a specific method in an example one is as follows:

s601, the program counter 103 stores the address of the first jump instruction in the memory 20.

S602, as described with reference to S303, the instruction decoder 105 decodes the first jump instruction, and generates a SIMD control signal.

Since the first jump instruction is a normal instruction, the instruction decoder 105 decodes the first jump instruction and sends a jump control signal to the program counter 103 through the operation controller 107.

S603, the address stored in the program counter 103 is updated to the address pointed to by the first jump instruction, i.e. the address of the multiply-reduce instruction in the memory 20.

S604, referring to the description of S303, the instruction decoder 105 decodes the multiplication reduction instruction.

The instruction decoder 105 queries the microcode ROM 106 to generate the exponent bit and mantissa bit extraction instructions after decoding, and sends corresponding SIMD control signals to the SIMD computing unit 1081 through the operation controller 107 after decoding.

S605, as described with reference to S304, the SIMD computation unit 1081, upon receiving the SIMD control signal, performs computation and obtains a computation result of the multiply-reduce instruction.

S606, the address stored in the program counter 103 is updated to the address of the approximate instruction.

S607, as described with reference to S303, the instruction decoder 105 decodes the approximate instruction.

The instruction decoder 105 queries the microcode rom 106, decodes the instruction to generate a polynomial approximation instruction, and sends a corresponding SIMD control signal to the SIMD computation unit 1081 through the operation controller 107 after decoding.

S608, as described with reference to S304, the SIMD computation unit 1081 receives the SIMD control signal, performs the computation, and obtains the computation result of the approximate instruction.

S609, the address stored in the program counter 103 is updated to the address of the range reconfiguration instruction.

S610, as described with reference to S303, the instruction decoder 105 decodes the range restructuring instruction.

The instruction decoder 105 queries the microcode rom 106, decodes the microcode to generate a floating-point addition instruction and a floating-point multiplication instruction, decodes the floating-point addition instruction and sends corresponding SIMD control signals to the SIMD computation unit 1081 through the operation controller 107.

S611, referring to the description of S304, the SIMD computation unit 1081 performs computation after receiving the SIMD control signal, and obtains a range reconstruction instruction computation result. Because the multiplication reduction instruction, the approximation instruction and the range reconstruction instruction are executed in sequence, the calculation result of the final range reconstruction instruction is the calculation result of ln (x).

By the method, the existing SIMD instruction can be expanded, the instruction of the basic operation layer is directly realized by using a hardware circuit, the calculation speed is improved, and meanwhile, the micro instruction is combined into the complex instruction of the calculation step layer by using the microcode read-only memory, so that the calculation time consumed by instruction fetching is further reduced, and the calculation speed is improved.

Another example is another method for implementing data processing of ln (x) provided in this embodiment, and is different from the first example in fig. 6, in the second example, assuming that the SIMD computation unit 1081 of the processor only supports instructions of the basic computation layer, and the microcode rom 106 only supports decoding of instructions of the basic computation layer to the existing instruction layer, according to S201 and S202, the compiler compiles the source code of the ln (x) task into a first jump instruction, and at the same time, the compiler compiles the ln (x) function in the vectorization function library into instructions of the basic computation layer, that is, an exponent bit extracting instruction, a polynomial approximating instruction, a floating point number addition instruction, and a floating point number multiplication instruction, where the first jump instruction points to an address of the exponent bit extracting instruction. Similar to the method of data processing of fig. 6, except that after executing the jump instruction, the program counter 103 sequentially stores addresses of a decimation exponent bit instruction, a decimation bit instruction, a polynomial approximation instruction, a floating point number addition instruction, and a floating point number multiplication instruction; according to each instruction address stored by the program counter 103, the instruction decoder 105 also decodes the exponent bit extraction instruction, the digit bit extraction instruction, the polynomial approximation instruction, the floating point number addition instruction and the floating point number multiplication instruction in turn and generates corresponding SIMD control signals, which are respectively executed by the SIMD computing unit 1801 to obtain the computed result of ln (x).

By the method, the existing SIMD instruction can be expanded, the instruction of the basic operation layer can be directly realized by using a hardware circuit, and the calculation speed is improved.

Example three is another method for implementing data processing of ln (x) provided by the embodiment of the present application, and unlike the example one in fig. 6, in the example three, assuming that the SIMD computation unit 1081 of the processor only supports instructions of the existing instruction layer, that is, the existing SIMD instruction, and the microcode read-only memory supports decoding of the computation step layer to the existing instruction layer, according to S201 and S202, the compiler compiles the source code of the ln (x) task into a first jump instruction, and at the same time, the compiler compiles the ln (x) function in the vectorization function library into instructions of the computation step layer, that is, a multiplication reduction instruction, an approximation instruction, and a range reconstruction instruction, and the first jump instruction points to the address of the multiplication reduction instruction. Similar to the data processing method of fig. 6, except that after executing the jump instruction, according to each instruction address stored by the program counter 103, the instruction decoder 105 in cooperation with the microcode rom 106 sequentially decomposes the instruction at the calculation step layer into instructions at the existing instruction layer, specifically: the instruction decoder 105, in cooperation with the microcode rom 106, decomposes the multiply-reduce instruction into instructions and shift instructions and decodes them to generate corresponding SIMD control signals, decomposes the approximate instruction into FMA instructions and decodes them to generate corresponding SIMD control signals, and decomposes the range reconstruction instruction into floating point addition instructions and floating point multiplication instructions and decodes them to generate corresponding SIMD control signals. Finally, the instructions of the existing instruction layer are executed by the SIMD computation unit 1801, respectively, to obtain the computation results of ln (x).

By the method, the existing SIMD instruction can be expanded, the instruction of the basic operation layer is directly realized by using a hardware circuit, and the calculation speed is improved.

Example four is another method for implementing data processing of ln (x) provided in the embodiment of the present application, and different from the example one in fig. 6, in the example four, assuming that the SIMD computation unit 1081 of the processor only supports instructions of the existing instruction layer, and the microcode read-only memory does not support decoding, according to S201 and S202, the compiler compiles the source code of the ln (x) task into a first jump instruction, and at the same time, the compiler compiles ln (x) functions in the vectorization function library into instructions of the existing instruction layer, that is, an and instruction, a shift instruction, an FMA instruction, a floating-point addition instruction, and a floating-point multiplication instruction, where the first jump instruction points to an address of the and instruction. Similar to the method of data processing of fig. 6, except that after executing the jump instruction, the program counter 103 sequentially stores addresses of the fetch and instruction, the shift instruction, the FMA instruction, the floating-point addition instruction, and the floating-point multiplication instruction; according to each instruction address stored in the program counter 103, the instruction decoder 105 also decodes the instruction, the shift instruction, the bit instruction, the FMA instruction, the floating-point addition instruction, and the floating-point multiplication instruction in turn and generates corresponding SIMD control signals, which are respectively executed by the SIMD computation unit 1801 to obtain the computation result of ln (x).

By the method, the hardware of the processor is not optimized for data processing, and all levels of operations are realized by a compiler. The function design of the hierarchical operation not only ensures the integrity and the expansibility of the operation of each layer, but also the user can respectively control the specific flow of the operation of each layer to complete the optimization of the data processing on the details

It should be noted that, for simplicity of description, the above method embodiments are described as a series of acts or combination of acts, but those skilled in the art should understand that the present application is not limited by the order of acts or combination of acts described.

Other reasonable combinations of steps that can be conceived by one skilled in the art from the above description are also within the scope of the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.

The method for processing data provided by the embodiment of the present application is described in detail above with reference to fig. 3 to 6, and the apparatus for processing data provided by the embodiment of the present application is further described below with reference to fig. 7.

Fig. 7 is a schematic diagram of a data processing apparatus 700 according to an embodiment of the present disclosure, which includes a first storage unit 701, a compiling unit 702, a decoding unit 703, and an executing unit 704. The apparatus 700 is used to implement the functionality of the processor shown in fig. 1 or fig. 2.

The first storage unit 701 is configured to store a corresponding relationship between a first instruction and at least two sub instructions. In practical product implementation, the first storage unit 701 may be the microcode rom 106 shown in fig. 2, or may be another storage, and the embodiment does not limit the form of the first storage unit 701.

The compiling unit 702 is configured to obtain a task of data processing and compile the task into a first instruction, and the specific implementation may refer to steps S301 and S302 in fig. 3, which is not described herein again. In actual implementation of a product, the compiling unit 702 may be the compiler 50 shown in fig. 1, or may be another compiler, and the form of the compiling unit 702 is not limited in this embodiment.

The decoding unit 703 is configured to obtain a first instruction, decompose the first instruction into at least two sub-instructions according to the correspondence, and send the sub-instructions to the SIMD computing unit. The specific implementation of the function of the decoding unit 703 can refer to the step S303 in fig. 3, which is not described herein again. In practical product implementation, the decoding unit 703 may be the instruction decoder 105 shown in fig. 2, or may be another instruction decoder, and the embodiment does not limit the form of the decoding unit 703.

The execution unit 704 is configured to execute the sub-instruction to obtain a processing result of the data processing, and the specific implementation may refer to the step of S304 in fig. 3, which is not described herein again. In practical product implementation, the execution unit 704 may be the SIMD computation unit 1081 shown in fig. 2, or may be another SIMD computation unit, and the form of the execution unit 704 is not limited in this embodiment.

Alternatively, the first instruction may be a first level instruction and the sub-instructions are second level instructions, wherein the first level instruction has a higher complexity of operation than the second level instruction, the SIMD computation unit supporting execution of the second level instruction.

Optionally, the at least two sub-instructions comprise any one of a Neon instruction set and a scalable quantum expansion instruction set. The instruction decoder supports the instructions responsible for decoding the instructions into the existing instruction set, which can be extended. The two sub-instructions may be at least two instructions in a Neon instruction set, at least two instructions in an SVE instruction set, at least one instruction in a Neon instruction set, and at least one instruction in an SVE instruction set.

Optionally, the at least two sub-instructions further comprise an instruction consisting of at least two instructions in the Neon instruction set and the scalable quanta extension instruction set. The two sub-instructions may be both instructions composed of at least two instructions in the Neon instruction set, or may be instructions composed of at least two instructions in the scalable proper-amount extended instruction set, or may be instructions composed of at least two instructions in the Neon instruction set and the scalable proper-amount extended instruction set, respectively.

Optionally, the data processing apparatus further includes a second storage unit 705, configured to store a vectorization function library, where the vectorization function library includes a function corresponding to an operation of any one of the Neon instruction set and the SVE instruction set. The compiling unit 702 is further configured to obtain a function in the vectorized function library before the task of data processing is compiled into the first instruction. In practical product implementation, the second storage unit 705 may be the memory 20 shown in fig. 1 or fig. 2, or may be another memory, and the form of the second storage unit 705 is not limited in this embodiment.

Optionally, the vectorization function library further includes a function corresponding to an operation of an instruction composed of at least two instructions in the Neon instruction set and the SVE instruction set.

Optionally, when the function included in the code of the task belongs to a function in the vectorized function library, the first instruction includes a vector instruction, and the compiling unit 702 is further configured to compile the task into the vector instruction.

Alternatively, when the function included in the code of the task does not belong to a function in the vectorized function library, the first instruction includes a first jump instruction and a vector instruction, and the compiling unit 702 is further configured to compile the task as the first jump instruction and compile the function operated by the task in the vectorized function library as the vector instruction, where the jump instruction points to an address of the vector instruction.

Optionally, the first instruction further includes a batch data processing instruction, the first jump instruction points to an address of the batch data processing instruction, and the compiling unit 702 is further configured to compile the batch data processing function into the batch data processing instruction, where the batch data processing instruction includes a second jump instruction, and the second jump instruction points to an address of the vector instruction.

Optionally, the task of data processing comprises calculation of an elementary function or calculation of a non-linear function.

In summary, the data processing apparatus 700 provided in the embodiment of the present application can implement data vectorization acceleration processing of complex mathematical computation through the compiling unit and the decoding unit based on the existing SIMD instruction set, thereby improving the computation performance of the apparatus.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the procedures or functions described in accordance with the embodiments of the present application are wholly or partially generated. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a Solid State Drive (SSD).

The foregoing is only illustrative of the present application. Those skilled in the art can conceive of changes or substitutions based on the specific embodiments provided in the present application, and all such changes or substitutions are intended to be included within the scope of the present application.

Claims

1. A method for data processing, the method being applied to a processor, the processor including a Single Instruction Multiple Data (SIMD) computation unit, a compiler, an instruction decoder, and a microcode rom, the microcode rom being configured to store a correspondence between a first instruction and at least two sub-instructions, the method comprising:

a compiler acquires a task of data processing and compiles the task into a first instruction;

the instruction decoder acquires the first instruction and decomposes the first instruction into the at least two sub-instructions according to the corresponding relation;

the instruction decoder sends the sub-instructions to a SIMD compute unit;

the SIMD compute unit executes the sub-instructions to obtain processing results for the task of data processing.

2. A method of data processing according to claim 1, wherein the first instruction is a first level instruction, the at least two sub-instructions are a second level instruction, the complexity of operation of the first level instruction is higher than the complexity of operation of the second level instruction, the SIMD computation unit supports execution of the second level instruction.

3. The method of any of claims 1 or 2, wherein the at least two sub-instructions comprise any of a Neon instruction set and a Scalable Vector Extensions (SVE) instruction set.

4. The method of data processing according to claim 3, wherein the at least two sub-instructions further comprise an instruction consisting of at least two instructions of the Neon instruction set and the SVE instruction set.

5. The data processing method of any of claims 1 to 4, wherein before the compiler compiles the task into the first instruction, the method further comprises:

the compiler acquires a function in a vectorization function library, wherein the vectorization function library comprises a function corresponding to the operation of any one of the Neon instruction set and the SVE instruction set.

6. The method of claim 5, wherein the vectorized function library further comprises a function corresponding to an operation of an instruction consisting of at least two of the Neon instruction set and the SVE instruction set.

7. The data processing method according to any one of claims 5 to 6, wherein when the function included in the code of the task belongs to a function in the vectorized function library, the first instruction includes a vector instruction, and the compiler compiles the task into the first instruction, which specifically includes:

the compiler compiles the task into the vector instructions.

8. The data processing method according to any one of claims 5 to 6, wherein when the function included in the code of the task does not belong to a function in the vectorized function library, the first instruction includes a first jump instruction and a vector instruction, and the compiler compiles the task into the first instruction, specifically including:

the compiler compiles the task into the first jump instruction;

the compiler compiles a function of the operation of the task in a vectorized function library into the vector instruction, the first jump instruction pointing to an address of the vector instruction.

9. The method of data processing according to claim 8, wherein the first instruction further comprises a batch data processing instruction, the first jump instruction points to an address of the batch data processing instruction, the compiler compiles the task as a first instruction, further comprising:

the compiler compiles a batch data processing function into the batch data processing instruction, the batch data processing instruction including a second jump instruction, the second jump instruction pointing to an address of the vector instruction.

10. A method as claimed in any one of claims 1 to 9, wherein the task of data processing comprises the calculation of an elementary function or the calculation of a non-linear function.

11. An apparatus for data processing, comprising a compiling unit, a decoding unit, an executing unit, and a first storage unit:

the first storage unit is used for storing the corresponding relation between a first instruction and at least two sub instructions;

the compiling unit is used for acquiring a task of data processing and compiling the task into a first instruction;

the decoding unit is used for decomposing the first instruction into at least two sub-instructions according to the corresponding relation; the execution unit is also used for sending the sub-instruction to the execution unit;

and the execution unit is used for executing the sub-instruction to obtain a processing result processed by the data.

12. The apparatus according to claim 11, wherein the first instruction is a first level instruction, the at least two sub-instructions are a second level instruction, the first level instruction having a higher complexity of operation than the second level instruction, the execution unit hardware circuitry supporting execution of the second level instruction.

13. Apparatus for data processing according to any of claims 11 or 12, wherein said at least two sub-instructions comprise any of a Neon instruction set and a scalable vector extensions instruction Set (SVE).

14. The apparatus according to claim 13, wherein said at least two sub-instructions further comprise instructions consisting of at least two of any of said Neon instruction set and said SVE instruction set.

15. The apparatus according to any one of claims 11 to 14, wherein the apparatus further includes a second storage unit, the second storage unit is configured to store a vectorization function library, the vectorization function library includes a function corresponding to an operation of any one of the Neon instruction set and the SVE instruction set, and the compiler is further configured to obtain the function in the vectorization function library.

16. The apparatus according to claim 15, wherein the vectorized function library further comprises a function corresponding to an operation of an instruction consisting of at least two of the Neon instruction set and the SVE instruction set.

17. The data processing apparatus according to any of claims 15 to 16, wherein when the function included in the code of the task belongs to a function in the vectorized function library, the first instruction comprises a vector instruction, and the compiling unit is further configured to:

compiling the task into the first instruction.

18. The data processing apparatus according to any of claims 15 to 16, wherein when the function included in the code of the task does not belong to a function in the vectorized function library, the first instruction comprises a first jump instruction and a vector instruction, and the compiling unit is further configured to:

compiling the task into the first jump instruction;

compiling a function of the operation of the task in a vectorized function library into the vector instruction, the first jump instruction pointing to an address of the vector instruction.

19. The apparatus according to claim 18, wherein the first instruction further comprises a batch data processing instruction, wherein the first jump instruction points to an address of the batch data processing instruction, and wherein the compilation unit is further configured to:

compiling a batch data processing function into the batch data processing instruction, wherein the batch data processing instruction comprises a second jump instruction, and the second jump instruction points to the address of the vector instruction.

20. A method as claimed in any one of claims 11 to 19, wherein the task of data processing comprises the calculation of an elementary function or the calculation of a non-linear function.

21. A processor, comprising a SIMD computation unit, an instruction decoder, a microcode read-only memory, and a compiler:

the microcode read-only memory is used for storing the corresponding relation between the first instruction and at least two sub-instructions;

the compiler is used for acquiring a task of data processing and compiling the task into a first instruction;

the instruction decoder is used for acquiring a first instruction and decomposing the first instruction into the sub-instructions according to the corresponding relation; and further for sending the sub-instructions to a SIMD computation unit;

and the SIMD computing unit is used for executing the sub-instruction to obtain the processing result of the data processing.

22. The processor of claim 21, wherein the first instruction is a first level of instructions, wherein the at least two sub-instructions are a second level of instructions, wherein the first level of instructions is more complex to operate than the second level of instructions, and wherein hardware circuitry of the execution unit supports execution of the second level of instructions.

23. The processor of any one of claims 21 or 22, wherein the at least two sub-instructions comprise any one of a Neon instruction set and a Scalable Vector Extensions (SVE) instruction set.

24. The processor of claim 23, wherein the at least two sub-instructions further comprise an instruction consisting of at least two of any of the Neon instruction set and the SVE instruction set.

25. The processor of any one of claims 21 to 24, wherein the compiler is further configured to obtain a function in a vectorized function library, and the vectorized function library includes a function corresponding to an operation of any one of the Neon instruction set and the SVE instruction set.

26. The apparatus according to claim 25, wherein the vectorized function library further comprises a function corresponding to an operation of an instruction consisting of at least two of the Neon instruction set and the SVE instruction set.

27. The processor according to any one of claims 25 to 26, wherein when the function included in the code of the task belongs to a function in the vectorized function library, the first instruction comprises a vector instruction, and the compiler is further configured to:

compiling the task into the first instruction.

28. The processor according to any one of claims 25 to 26, wherein when the function included in the code of the task does not belong to a function in the vectorized function library, the first instruction comprises a first jump instruction and a vector instruction, and the compiler is further configured to:

compiling the task into the first jump instruction;

29. The processor of claim 28, wherein the first instruction further comprises a batch data processing instruction, wherein the first jump instruction points to an address of the batch data processing instruction, and wherein the compiler is further configured to:

30. A processor according to any one of claims 21 to 29, wherein the task of data processing comprises calculation of an elementary function or calculation of a non-linear function.

31. A computing device comprising a processor as claimed in any one of claims 21 to 30 and a memory for storing a library of vectorised functions.