CN116189727A - Semiconductor structure, memory and method for manufacturing semiconductor structure - Google Patents

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure, a memory and a manufacturing method of the semiconductor structure, wherein the semiconductor structure comprises: an array semiconductor layer having a plurality of memory blocks including a plurality of bit lines and a plurality of word lines; a peripheral semiconductor layer bonded to the array semiconductor layer, the peripheral semiconductor layer including a word line driving region and a sense amplifying region; a sense amplifier of the sense amplifying region is electrically connected with the bit line, and a word line driver of the word line driving region is electrically connected with the word line; the orthographic projection of the word line driving region and the sense amplifying region on the array semiconductor layer at least partially overlaps with the orthographic projection of at least one memory block on the array semiconductor layer. The embodiment of the disclosure at least improves the integration level of the semiconductor structure, and improves the production efficiency and the performance of the semiconductor structure.

Description

Semiconductor structure, memory and method for manufacturing semiconductor structure

technical field

The disclosure belongs to the field of semiconductors, and in particular relates to a semiconductor structure, a memory and a method for manufacturing the semiconductor structure.

Background technique

A memory generally includes a semiconductor layer and memory blocks and peripheral devices formed on the semiconductor layer. Specifically, the memory block is used to store data, which may include memory cells and word lines and bit lines connected to the memory cells; peripheral devices are used to control the read process of the memory block, which may include word line drivers and sense amplifiers .

However, the area occupied by peripheral devices and storage blocks on the semiconductor layer is large, and the size of the memory needs to be further reduced. In addition, the production process of the memory is relatively complicated, and the performance of the memory needs to be improved.

Contents of the invention

Embodiments of the present disclosure provide a semiconductor structure, a memory, and a method for manufacturing the semiconductor structure, which at least help reduce the size of the memory.

According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure on the one hand, wherein the semiconductor structure includes: an array semiconductor layer having a plurality of memory blocks, and the memory blocks include a plurality of bit lines and a plurality of word lines; A peripheral semiconductor layer bonded to the array semiconductor layer, the peripheral semiconductor layer includes a word line drive region and a sense amplifier region; the sense amplifier in the sense amplifier region is electrically connected to the bit line, the The word line driver in the word line drive area is electrically connected to the word line; the orthographic projection of the word line drive area and the sense amplification area on the semiconductor layer of the array is consistent with at least one of the memory blocks in the array The orthographic projections on the semiconductor layer are at least partially overlapping.

According to some embodiments of the present disclosure, another embodiment of the present disclosure further provides a memory, including the foregoing semiconductor structure.

According to some embodiments of the present disclosure, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, the method for manufacturing a semiconductor structure includes: providing an array semiconductor layer and forming a first interconnection structure on the array semiconductor layer, The array semiconductor layer has a plurality of memory blocks, the memory block includes a plurality of bit lines and a plurality of word lines; a peripheral semiconductor layer is provided and a second interconnection structure is formed on the peripheral semiconductor layer, the peripheral semiconductor layer Comprising a word line driving area and a sense amplification area; bonding the array semiconductor layer and the peripheral semiconductor layer through the first interconnection structure and the second interconnection structure, so that the word line driving area and the The orthographic projection of the sensing amplifying area on the array semiconductor layer at least partially overlaps the orthographic projection of at least one of the memory blocks on the array semiconductor layer, and the sense amplifier of the sensing amplifying area and the The bit line is electrically connected, and the word line driver in the word line driving area is electrically connected to the word line.

The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

The semiconductor structure includes a bonded array semiconductor layer and a peripheral semiconductor layer, the memory blocks are formed on the array semiconductor layer, and the peripheral devices are formed on the peripheral semiconductor layer. Since the aforementioned two semiconductor layers are stacked, it is beneficial to reduce the area of a single semiconductor layer and improve the space utilization in a direction perpendicular to the upper surface of the semiconductor layer.

In addition, since the memory block and peripheral devices can be manufactured separately, the production process is simpler, the production capacity is higher, and it is beneficial to improve the performance of the semiconductor structure.

In addition, the peripheral semiconductor layer includes a word line drive region and a sense amplification region, and the orthographic projections of the two on the array semiconductor layer at least partially overlap with the orthographic projection of at least one memory block on the array semiconductor layer, thereby facilitating shrinking The distance between the word line drive area and the sense amplification area and the memory block is improved to increase the signal transmission rate.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Apparently, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.

FIG. 1 shows a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 2 shows a schematic diagram of a bonding surface of an array semiconductor layer provided by an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of a bonding surface of a peripheral semiconductor layer provided by an embodiment of the present disclosure.

FIG. 4 shows a first partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 5 shows a second partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 6 shows a third partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 7 shows a fourth partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 8 shows a fifth partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 9 shows a sixth partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 10 shows a seventh partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 11 shows an eighth partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 12 shows a ninth partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 13 shows a tenth partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

FIG. 14 shows an eleventh partial top view of a semiconductor structure provided by an embodiment of the present disclosure.

Detailed ways

It can be seen from the background art that peripheral devices and memory blocks occupy a relatively large area on the semiconductor layer, and the size of the memory needs to be further reduced. The production process of the memory is relatively complicated, and the performance of the memory needs to be improved. After analysis, it is found that the main reason is that peripheral devices such as sense amplifiers and word line drivers and memory blocks are usually formed on the same semiconductor layer. The space utilization in the direction is low. In addition, since the key process and performance requirements of the memory block and peripheral devices are different, the process of integrating both on the same semiconductor layer is complex and may result in low yield and low performance.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes two mutually bonded semiconductor layers, an array semiconductor layer and a peripheral semiconductor layer. A memory block is formed on the array semiconductor layer, and peripheral devices are formed on the peripheral semiconductor layer. Since the two semiconductor layers are stacked, the required area of a single semiconductor layer is small, and the space utilization rate in the direction perpendicular to the upper surface of the semiconductor layer is high, so that the integration degree of the semiconductor structure can be improved. In addition, the peripheral semiconductor layer includes a word line driving region and a sensing amplification region, and the orthographic projections of the two on the array semiconductor layer at least partially overlap with the orthographic projection of at least one of the memory blocks on the array semiconductor layer, That is, the distance between the word line driving area and the sensing amplification area and the memory block is relatively close, which is beneficial to increase the signal transmission rate.

Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that, in each embodiment of the present disclosure, many technical details are provided for readers to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be realized.

As shown in FIGS. 1-14 , an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes: an array semiconductor layer 1 with a plurality of memory blocks 3 , and the memory blocks 3 include a plurality of bit lines BL and a plurality of word lines. WL; the peripheral semiconductor layer 2 bonded to the array semiconductor layer 1, the peripheral semiconductor layer 2 includes the word line driving region 42 and the sensing amplification region 41; the sense amplifier 61 of the sensing amplification region 41 is electrically connected to the bit line BL, The word line driver 62 of the word line driving area 42 is electrically connected to the word line WL; the orthographic projection of the word line driving area 42 and the sense amplification area 41 on the array semiconductor layer 1 is the same as that of at least one memory block 3 on the array semiconductor layer 1 The orthographic projections overlap at least partially.

Such a design has at least the following advantages:

First, the storage block 3 , the sense amplifier 61 , the word line driver 62 and other peripheral devices are arranged on two different semiconductor layers, which is beneficial to reduce the area of a single semiconductor layer. In addition, in the direction perpendicular to the upper surface of the semiconductor layer, the space efficiency of the semiconductor layer is improved. Since the memory block 3 and peripheral devices are manufactured separately, the process is simpler, the production efficiency is higher, and it is beneficial to improve the yield and performance of both.

Second, the orthographic projection of the word line driving region 42 and the sense amplification region 41 on the array semiconductor layer 1 at least partially overlaps the orthographic projection of at least one memory block 3 on the array semiconductor layer 1 . This helps to reduce the distance between the bit line BL of the memory block 3 and the sense amplifier 61 , and the distance between the word line WL of the memory block 3 and the word line driver 62 , thereby shortening the wiring length and shortening the delay time.

The semiconductor structure will be described in detail below with reference to the accompanying drawings.

The semiconductor structure includes a first direction X, a second direction Y and a third direction Z, the first direction X is perpendicular to the second direction Y, and the first direction X and the second direction Y are also perpendicular to the third direction Z. Wherein, the first direction X and the second direction Y may be parallel to the upper surface of the array semiconductor layer 1 , and the third direction Z may be perpendicular to the upper surface of the array semiconductor layer 1 . The word lines WL extend along the first direction X, and the bit lines BL extend along the second direction Y.

FIG. 1 shows a cross-sectional view of a semiconductor structure. Referring to FIG. 1 , both the array semiconductor layer 1 and the peripheral semiconductor layer 2 can be chip substrates or wafers. The array semiconductor layer 1 and the peripheral semiconductor layer 2 can be connected together by hybrid bonding. The array semiconductor layer 1 and the peripheral semiconductor layer 2 can be bonded front-to-back or front-to-front. Wherein, the side of the array semiconductor layer 1 on which the memory block 3 is formed is called the front side, and the side of the peripheral semiconductor layer 2 on which peripheral devices such as the sense amplifier 61 and the word line driver 62 are formed is called the front side.

The semiconductor structure further includes an interconnection structure 13 for electrically connecting the array semiconductor layer 1 and the peripheral semiconductor layer 2 . The interconnection structure 13 includes a first interconnection structure 11 on the array semiconductor layer 1 and a second interconnection structure 12 on the peripheral semiconductor layer 2 . When two semiconductor layers are bonded in a front-to-front manner, the first interconnection structure 11 can be a first pad, and the second interconnection structure 12 can be a second pad 122; In the case of backside bonding, the second interconnection structure 12 may include a second pad 122 and a conductive via 121 , and the conductive via 121 may be a through-silicon via (Through-Silicon Via, TSV). In addition, the peripheral semiconductor layer 2 is further formed with data channel pads 123 (IO pads) connected to other circuits or devices.

Fig. 2 shows the schematic diagram of the bonding surface of array semiconductor layer 1, and Fig. 3 shows the schematic diagram of the bonding surface of peripheral semiconductor layer 2, with reference to Fig. 2-Fig. 3, the bond of array semiconductor layer 1 and peripheral semiconductor layer 2 Welding pads are provided on the combined surfaces to serve as the first interconnection structure 11 and the second interconnection structure 12 respectively. In some embodiments, the range of the number of bit lines BL and the number of word lines WL of a memory block 3 may both be 900-1100, and the number of interconnection structures 13 may be equal to the sum of the numbers of bit lines BL and word lines WL. The area of one memory block 3 may range from 45µm×45µm to 55µm×55µm. Taking the number of interconnection structures 13 as 2000 and the area of memory block 3 as 50µm×50µm as an example, the pitch of interconnection structures 13 is about 1.1118µm, which meets the requirements of hybrid bonding.

Referring to FIGS. 4-12 , the storage block 3 will be described in detail below. The memory block 3 includes a plurality of memory cells arranged in an array, the memory cells may include transistors and capacitors, the word line WL may be connected to the gate of the transistor, and the bit line BL may be connected to the source or drain of the transistor. In some embodiments, the memory block 3 may be a memory array (array) or a memory bank (bank), and is electrically connected to a global sense amplifier and a global word line driver. In other embodiments, the memory block 3 may be a memory array tile (MAT), and is electrically connected to a local sense amplifier and a local word line driver.

There may be multiple word line drivers 62 in the word line driving area 42 , and the word line drivers 62 may provide the word line WL with a turn-on or turn-off voltage. There may be multiple sense amplifiers 61 in the sense amplification region 41, and the sense amplifiers 61 may amplify the data transmitted from the memory cells to the bit line BL, so as to ensure correct detection of the data stored in the memory cells. Referring to FIGS. 4-7 , each word line driver 62 may be electrically connected to a word line WL in the memory block 3 . Referring to FIGS. 8-12 , each sense amplifier 61 may be electrically connected to two bit lines BL in the memory block 3 , and the sense amplifier 61 may amplify a voltage difference on the two bit lines BL. It should be noted that the two bit lines BL electrically connected to the sense amplifier 61 may be located in the same memory block 3 or in different memory blocks 3 , which will be described in detail later.

The semiconductor structure further includes connecting wires. For example, at least part of the connecting wires may extend in a direction parallel to the upper surface of the array semiconductor layer 1 , so as to change the layout of the bit lines BL and the word lines WL. Specifically, referring to FIG. 4, FIG. 6-FIG. 7, the connection line includes a word line connection line WL0 located in the peripheral semiconductor layer 2, at least part of the word line connection line WL0 extends along the second direction Y, and the word line connection line WL0 and the word line The word line driver 62 of the driving region 42 is electrically connected, and is electrically connected to the word line WL through the interconnection structure 13 . Referring to FIGS. 8-12 , the connection lines include the bit line connection line BL0 located in the peripheral semiconductor layer 2 . At least a part of the bit line connecting line BL0 extends along the first direction X, and the bit line connecting line BL0 is electrically connected to the sense amplifier 61 of the sense amplifier region 41 , and is electrically connected to the bit line BL through the interconnection structure 13 . That is to say, at least part of the bit line connecting line BL0 is perpendicular to the bit line BL, and at least part of the word line connecting line WL0 is perpendicular to the word line WL, which can standardize the layout of the connecting lines and reduce the length of the connecting lines.

The positional relationship between the word line driving region 42 and the sense amplification region 41 will be described in detail below.

In some embodiments, referring to FIGS. 4-14 , the extending direction of the word line driving region 42 and the extending direction of the sense amplifying region 41 are parallel to each other. This is because each memory block 3 is electrically connected to the word line driver 62 in the word line drive area 42 and the sense amplifier 61 in the sense amplifier area 41. Therefore, setting the extension directions of the two areas in parallel can simplify the connection. The layout of the lines, and provide more sufficient space for other peripheral areas.

Specifically, referring to FIG. 13-FIG. 14, the word line drive region 42 and the sense amplification region 41 are arranged adjacently, and both constitute the first peripheral region 412; the peripheral semiconductor layer 2 also includes a second peripheral region 43, the second peripheral Area 43 includes an address decoding circuit or a write drive circuit. In addition, peripheral devices such as decoders, IO circuits, and clock signal generation circuits may also be included in the second peripheral area 43 . The second peripheral area 43 is at least located on opposite sides of the first peripheral area 412 . Therefore, the space of the second peripheral region 43 is larger, which facilitates the manufacturing process and reduces signal interference.

Continuing to refer to FIGS. 13-14 , there is a wiring layer 44 on the peripheral semiconductor layer 2 to electrically connect multiple second peripheral regions 43 . In some embodiments, a plurality of first peripheral regions 412 are arranged at intervals, so as to reserve positions for the wiring layer 44 between the second peripheral regions 43 . The orthographic projection of at least part of the wiring layer 44 on the array semiconductor layer 1 may overlap with the orthographic projection of the spaced area of the adjacent memory block 3 .

In some other embodiments, the word line driving region 42 and the sensing amplification region 41 may also be spaced apart from the sensing amplification region 41 . The extending direction of the word line driving region 42 may also be different from the extending direction of the sense amplifying region 41 , for example, the extending direction of the word line driving region 42 is perpendicular to the extending direction of the sensing amplifying region 41 .

In some embodiments, referring to FIG. 5-FIG. 7 and FIG. 9-FIG. 12, the extending direction of the word line drive region 42 can be inclined relative to the first direction X and the second direction Y, and the extending direction of the sense amplification region 41 can also be inclined. Can be inclined with respect to the first direction X and the second direction Y. The inclined setting is conducive to enlarging the overlapping area of the orthographic projection of the word line driving region 42 and the orthographic projection of the memory block 3, and the overlapping area of the orthographic projection of the sensing amplification area 41 and the orthographic projection of the memory block 3, which can increase the word line driver 62. A process window for structures such as the sense amplifier 61 and connecting wires, so as to reduce process difficulty. In addition, enlarging the space between the sense amplification region 41 and the word line driving region 42 is also beneficial to reduce the parasitic capacitance, thereby improving the performance of the semiconductor structure.

~60°。感测放大区域41的延伸方向分别与第一方向X和第二方向Y的夹角可以为30°~60°。在夹角处于上述范围时，可以为字线驱动区域42和感测放大区域41提供较为充足的空间，并避免挤占布线层44（参考图13-图14）的位置。For example, the included angles between the extending direction of the word line driving region 42 and the first direction X and the second direction Y may be

~60°. The included angles between the extending direction of the sensing amplification region 41 and the first direction X and the second direction Y respectively may be 30°-60°. When the included angle is within the above range, sufficient space can be provided for the word line driving region 42 and the sense amplification region 41 , and the location of the wiring layer 44 (refer to FIGS. 13-14 ) can be avoided.

In other embodiments, referring to FIG. 4 and FIG. 8 , the extending direction of the word line driving region 42 may be parallel to the first direction X or the second direction Y, and the extending direction of the sense amplification region 41 may be parallel to the first direction. X or the second direction Y is parallel.

For example, the extension directions of the word line driving region 42 and the sense amplification region 41 are set parallel to the first direction X, or the extension directions of the word line drive region 42 and the sense amplification region 41 can also be both relative to the second direction X. The direction Y is set in parallel. In this way, the consistency of the extension directions of the word line driving region 42 and the sense amplification region 41 can be ensured.

In addition, the extending direction of the word line driving region 42 can also be parallel to the second direction Y, that is, parallel to the arrangement direction of the plurality of word lines WL; and the extending direction of the sense amplification region 41 is parallel to the first direction X, that is, parallel to The arrangement direction of the plurality of bit lines BL. In this way, the orthographic projection of the word line driving region 42 on the array semiconductor layer 1 can at least partially overlap with the orthographic projections of the plurality of word lines WL on the array semiconductor layer 1, and the orthographic projection of the sensing amplification region 41 on the array semiconductor layer 1 It may at least partially overlap with the orthographic projections of the plurality of bit lines BL on the array semiconductor layer 1 , which is beneficial to shorten the length of the bit line connecting line BL0 and the word line connecting line WL0 .

Referring to FIGS. 4-7 , the orthographic relationship and the electrical connection relationship between the word line driving region 42 and the memory block 3 will be illustrated below. In order to more clearly illustrate the electrical connection relationship between the word line driver 62 and the memory block 3, FIGS. 4-7 do not illustrate the sense amplifier 61 and its electrical connection relationship with the memory block 3, and FIGS. 4-7 are all semiconductor structures. local schematic diagram. It should be noted that the following orthographic projections all refer to the orthographic projections on the array semiconductor layer 1 .

Referring to FIGS. 4-5 , Example 1: the word line driver 62 of the word line drive region 42 is electrically connected to the memory blocks 3 in one-to-one correspondence, and the orthographic projection of a word line drive region 42 on the array semiconductor layer 1 is located at the corresponding one The memory block 3 is in the orthographic projection on the semiconductor layer 1 of the array. That is, there is a one-to-one correspondence between the word line driving region 42 and the memory block 3 in the orthographic projection relationship and the electrical connection relationship. The one-to-one correspondence method is relatively simple, which is beneficial to reduce the distance between the word line WL and the word line driver 62 , thereby increasing the operating speed of the semiconductor structure.

Referring to FIG. 4 , the extending direction of the word line driving region 42 may be parallel to the first direction X or the second direction Y. Referring to FIG. Referring to FIG. 5 , the extending direction of the word line driving region 42 may also be inclined with respect to the first direction X and the second direction Y. Referring to FIG. That is to say, in Example 1, the orthographic projection of the word line driving region 42 can overlap with the orthographic projection of the memory block 3 no matter whether it is arranged in parallel or inclined. Comparing Fig. 4 to Fig. 5, it can be seen that when the oblique arrangement is made, the orthographic projections of the multiple word lines WL may overlap with the orthographic projections of the word line driving region 42, so that it is unnecessary to set the word line connecting line WL0, or it may be set shorter The word line connection line WL0. For example, the word line driving region 42 may extend along the diagonal direction of the memory block 3 , which is beneficial to expand the space of the word line driver 62 and reduce parasitic capacitance. In some embodiments, the orthographic projection of each wordline WL has an overlapping relationship with the orthographic projection of a wordline driver 62 .

Continuing to refer to FIGS. 4-5 , the orthographic projection of the word line driving region 42 on the array semiconductor layer 1 covers the central position of the orthographic projection of the memory block 3 on the array semiconductor layer 1 . In this way, the layout of the word line connecting line WL0 can be balanced and the parasitic capacitance can be reduced.

As shown in FIG. 4, the storage block 3 may include two storage sub-blocks 31 arranged in the second direction Y, and two adjacent word line drivers 62 may be electrically connected to the word lines WL of different storage sub-blocks 31, thereby Therefore, the correspondingly connected word-line connection lines WL0 of two adjacent word-line drivers 62 do not need to be arranged facing each other, which is beneficial to reduce parasitic capacitance.

In some other embodiments, referring to FIGS. 6-7 , two adjacent storage blocks 3 arranged in the first direction X form a storage group 3a, or, two adjacent storage blocks arranged in the second direction Y 3 constitutes a memory group 3a; the orthographic projection of a word line drive region 42 on the array semiconductor layer 1 overlaps at least partially the orthographic projection of two memory blocks 3 of a memory group 3a on the array semiconductor layer 1. Since the orthographic projection of the word line driving region 42 may overlap with the orthographic projections of the two memory blocks 3 , it is beneficial to provide more sufficient space for the word line driver 62 to reduce signal interference and simplify the manufacturing process.

Specifically, referring to FIG. 6, Example 2: the word line drive region 42 includes two connected first sub-regions 421, and the orthographic projections of the two first sub-regions 421 on the array semiconductor layer 1 are respectively included in the corresponding storage group 3a. The orthographic projections of two different memory blocks 3 on the array semiconductor layer 1 at least partially overlap; the word line drivers 62 of the two first sub-regions 421 are electrically connected to the two different memory blocks 3 respectively.

For example, the two first sub-areas 421 are electrically connected to the nearest memory block 3 respectively. That is to say, the first sub-region 421 may have an orthographic overlap relationship and an electrical connection relationship with a memory block 3 at the same time. This is beneficial to simplify the layout of the word line connection line WL0 and increase the signal transmission rate.

Specifically, each storage block 3 includes two storage sub-blocks 31 , and the two storage sub-blocks 31 can be arranged in the first direction X or the second direction Y. The word line drivers 62 of the two first sub-regions 421 of the word line drive region 42 are electrically connected to one of the two different memory blocks 3 respectively, and the orthographic projection of the first sub-region 421 is connected to the corresponding memory sub-block 31. The orthographic projections of block 31 overlap at least partially. That is to say, the word line driver 62 of a first sub-region 421 is electrically connected to the word line WL of a storage sub-block 31, and the orthographic projection of a first sub-region 421 has an overlapping relationship with the orthographic projection of a storage sub-block 31 .

Continuing to refer to FIG. 6, multiple word line drivers 62 in the first sub-region 421 can be arranged at equal intervals, and the lengths of multiple word line connecting lines WL0 can be the same, which can improve the uniformity of the semiconductor structure and avoid different delay times. . In addition, the multiple word line connecting lines WL0 can also be arranged in a staggered manner, that is, the multiple word line connecting lines WL0 are not facing each other in the first direction X, so as to reduce parasitic capacitance.

Referring to FIG. 7 , Example 3: the word line drive region 42 includes two connected first sub-regions 421, and the orthographic projections of the two first sub-regions 421 on the array semiconductor layer 1 are respectively the same as the two sub-regions included in the corresponding storage group 3a. The orthographic projections of different memory blocks 3 on the array semiconductor layer 1 are at least partially overlapped; the word line drivers 62 of the two first sub-regions 421 are electrically connected to one memory block 3 in the corresponding memory group 3a. That is, although the orthographic projection of the word line driving region 42 may overlap with the orthographic projections of the two memory blocks 3 , the word line driver 62 of the word line driving region 42 may only be electrically connected to one of the memory blocks 3 .

It should be noted that, in Example 2 and Example 3, the extending direction of the word line driving region 42 may be inclined relative to the first direction X and the second direction Y, that is, the extending direction of the word line driving region 42 is different from the first direction X and the second direction Y, so as to ensure that the word line driving region 42 can straddle two memory blocks 3 .

Comparing Example 2 and Example 3, it can be seen that when the word line drive region 42 is electrically connected to the word lines WL of the two memory blocks 3, the length of the word line connection line WL0 is shorter, and the length of the word line connection line WL0 is shorter. The positive facing area is smaller, which can shorten the delay time and reduce the parasitic capacitance.

Referring to FIGS. 8-12 , the projection relationship and electrical connection relationship between the sensing amplification region 41 and the memory block 3 will be illustrated below. In order to illustrate the electrical connection relationship between the sense amplification region 41 and the memory block 3 more clearly, FIGS. 8-12 do not illustrate the word line driver 62 and its electrical connection relationship with the memory block 3 . 8-12 are partial schematic diagrams of semiconductor structures.

Referring to FIGS. 8-9 , Example 4: The sense amplifiers 61 of the sense amplification region 41 are electrically connected to the memory blocks 3 in one-to-one correspondence, and the orthographic projection of a sense amplification region 41 on the array semiconductor layer 1 is located in a corresponding The memory block 3 is in the orthographic projection on the semiconductor layer 1 of the array. That is, the orthographic projection relationship and electrical connection relationship between the sensing amplification area 41 and the memory block 3 are in one-to-one correspondence. The one-to-one connection method is relatively simple, and it is beneficial to reduce the distance between the bit line BL and the sense amplifier 61, thereby increasing the operating speed of the semiconductor structure.

Referring to FIG. 8 , the extending direction of the sensing amplification region 41 may be parallel to the first direction X or the second direction Y. Referring to FIG. Referring to FIG. 9 , the extension direction of the sensing amplification region 41 may be inclined with respect to the first direction X and the second direction Y. Referring to FIG. For example, the sense amplification region 41 may extend along the diagonal direction of the memory block 3 , which is beneficial to expand the space of the sense amplification region 41 to reduce parasitic capacitance. In addition, the orthographic projections of more bit lines BL may overlap with the orthographic projections of the sense amplification region 41 , so as to simplify the layout of the bit line connecting line BL0 .

Continuing to refer to FIGS. 8-9 , the orthographic projection of the sensing amplification region 41 on the array semiconductor layer 1 covers the central position of the orthographic projection of the memory block 3 on the array semiconductor layer 1 . In this way, the layout of the bit line connecting line BL0 can be balanced and the parasitic capacitance can be reduced.

Referring to FIG. 8 , the orthographic projection of the sense amplifier 61 may be located between the orthographic projections of the two bit lines BL electrically connected thereto, which is beneficial to reduce the length of the bit line connecting line BL0 . In addition, referring to FIG. 9 , the sense amplifier 61 may also be located on the same side of the two bit lines BL electrically connected thereto.

In some other embodiments, referring to FIGS. 10-12 , two adjacent storage blocks 3 arranged in the first direction X form a storage group 3 a, or, two adjacent storage blocks arranged in the second direction Y 3 constitutes a memory group 3a; the orthographic projection of a sensing amplification region 41 on the array semiconductor layer 1 overlaps at least partially the orthographic projection of two memory blocks 3 of a memory group 3a on the array semiconductor layer 1. Since the orthographic projection of the sensing amplifying region 41 may overlap with the orthographic projections of the two memory blocks 3 , it is beneficial to provide a more sufficient spatial location for the sensing amplifying region 41 to reduce signal interference and simplify the manufacturing process.

Specifically, referring to FIG. 10 , example five: the sensing amplification region 41 includes two connected second sub-regions 411, and the orthographic projections of the two second sub-regions 411 on the array semiconductor layer 1 are respectively included in the corresponding storage group 3a. Orthographic projections of two different memory blocks 3 on the array semiconductor layer 1 are at least partially overlapped, and the sense amplifiers 61 of the two second sub-regions 411 are respectively electrically connected to the two different memory blocks 3 .

For example, the two second sub-regions 411 are electrically connected to the nearest memory block 3 respectively. That is to say, the second sub-region 411 may have an orthographic overlap relationship and an electrical connection relationship with a memory block 3 at the same time. This is beneficial to simplify the layout of the bit line connecting line BL0 and increase the signal transmission rate.

Specifically, each storage block 3 includes two storage sub-blocks 31 , and the two storage sub-blocks 31 can be arranged in the first direction X or the second direction Y. The two second sub-areas 411 of the sensing amplification area 41 are electrically connected to one of the two different memory blocks 3 respectively, and the orthographic projections of the second sub-areas 411 and the orthographic projections of the corresponding memory sub-blocks 31 overlap at least partially. That is to say, the sense amplifier 61 of a second sub-area 411 is electrically connected to the bit line BL of a memory sub-block 31, and the orthographic projection of a second sub-area 411 and the orthographic projection of a corresponding memory sub-block 31 have an overlapping relationship.

Referring to FIG. 11, example six: the sense amplification region 41 includes two connected second sub-regions 411, and the orthographic projections of the two second sub-regions 411 on the array semiconductor layer 1 are respectively the same as the two included in the corresponding storage group 3a. Orthographic projections of different memory blocks 3 on the array semiconductor layer 1 are at least partially overlapped, and the sense amplifiers 61 of the two second sub-regions 411 are electrically connected to one memory block 3 in the corresponding memory group 3 . That is, although the orthographic projection of the sensing amplification area 41 may have an overlapping relationship with the orthographic projections of the two memory blocks 3 , the sense amplifier 61 of the sensing amplification area 41 may be electrically connected to only one of the memory blocks 3 .

Comparing Example 5 and Example 6, it can be seen that when the sense amplification region 41 is electrically connected to the bit lines BL of the two memory blocks 3, the length of the bit line connection line BL0 is shorter, and the length of the bit line connection line BL0 is shorter. The positive facing area is smaller, which can shorten the delay time and reduce the parasitic capacitance.

Referring to FIG. 12 , example seven: the sense amplifier 61 of one sense amplification region 41 is electrically connected to two memory blocks 3 in the corresponding memory group 3 a. That is, one sense amplification region 41 is electrically connected to all the bit lines BL in the two memory blocks 3 that have an overlapping relationship with it in orthographic projection.

For example, two storage blocks 3 of the storage group 3a are arranged in the second direction Y. Each sense amplifier 61 is electrically connected to bit lines BL of two different memory blocks 3 , and the two bit lines BL electrically connected to the same sense amplifier 61 are aligned in the second direction Y. In this way, the number of sense amplifiers 61 can be reduced, thereby providing more sufficient space for structures such as peripheral devices in the second peripheral region 43 and the wiring layer 44 (refer to FIG. 13 - FIG. 14 ).

It should be noted that, in Example 5 to Example 7, the extension direction of the sensing amplification region 41 may be inclined relative to the first direction X and the second direction Y, that is, the extension direction of the sensing amplification region 41 is different from the first direction X and the second direction Y to ensure that the sense amplification region 41 can straddle two memory blocks 3 .

It is worth noting that, under the premise of no contradiction, "the orthographic relationship and electrical connection relationship between the word line driving region 42 and the memory block 3" can be compared with "the orthographic relationship and the electrical connection relationship between the sensing amplification region 41 and the memory block 3." relationship" to each other.

For example, both a word line driving region 42 and a sensing amplification region 41 have an orthographic overlapping relationship and an electrical connection relationship with a memory block 3 . Alternatively, both a word line drive region 42 and a sense amplification region 41 have an orthographic overlapping relationship and an electrical connection relationship with the two memory blocks 3 . This is beneficial to improving the uniformity of the semiconductor structure and reducing the length of the connection lines, so as to provide more sufficient space for the second peripheral region 43 . It should be noted that the embodiments of the present disclosure are not limited to the above two combination schemes. That is, each solution of Example 1 to Example 3 can be combined with each solution of Example 4 to Example 7 in pairs.

To sum up, in the embodiment of the present disclosure, the memory block 3 and peripheral devices are arranged on two different semiconductor layers and bonded, which is conducive to reducing the area of the semiconductor layer, and is conducive to improving production efficiency and semiconductor structure. performance. The orthographic projection of the word line drive region 42 and the sense amplification region 41 on the array semiconductor layer 1 overlaps at least partially the orthographic projection of at least one memory block 3 on the array semiconductor layer 1, which is beneficial to reduce the length of the connecting line and shorten delay.

An embodiment of the present disclosure further provides a memory, and the memory includes the semiconductor structure provided in the foregoing embodiments. For detailed descriptions of the semiconductor structure, reference may be made to the foregoing embodiments. The memory may be a memory such as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random-Access Memory, SRAM), a high bandwidth memory (High Bandwidth Memory, HBM), and the like.

Embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure. The manufacturing method can manufacture the semiconductor structure provided in the foregoing embodiments. For detailed descriptions of the semiconductor structure, reference can be made to the foregoing embodiments.

Referring to FIG. 1 , the manufacturing method includes: providing an array semiconductor layer 1 and forming a first interconnection structure 11 on the array semiconductor layer 1 . Exemplarily, the first pad is formed by a patterning process and a deposition process as the first interconnection structure 11 . The array semiconductor layer 1 may also have a dielectric layer, and the upper surface of the first interconnection structure 11 may be flush with the upper surface of the dielectric layer. The array semiconductor layer also has multiple memory blocks 3 (refer to FIGS. 4-14 ), and the memory blocks 3 include multiple bit lines BL and multiple word lines WL.

A peripheral semiconductor layer 2 is provided and a second interconnection structure 12 is formed on the peripheral semiconductor layer 2 . Exemplarily, the second pad 122 and the conductive via 121 are formed as the second interconnection structure 12 through a patterning process and a deposition process. In other embodiments, only the second pad 122 may be formed as the second interconnection structure 12 . The peripheral semiconductor layer 2 may also have a dielectric layer, and the upper surface of the second interconnection structure 12 may be flush with the upper surface of the dielectric layer. The peripheral semiconductor layer 2 also includes a word line drive region 42 and a sense amplification region 41 .

The array semiconductor layer 1 and the peripheral semiconductor layer 2 are bonded through the first interconnection structure 11 and the second interconnection structure 12, so that the orthographic projection of the word line drive region 42 and the sense amplification region 41 on the array semiconductor layer 1 is at least the same as The orthographic projection of a storage block 3 on the array semiconductor layer 1 is at least partially overlapped, and the sense amplifier 61 in the sense amplification area 41 is electrically connected to the bit line BL, and the word line driver 62 in the word line drive area 42 is electrically connected to the word line WL. electrical connection. For example, a hybrid bonding method is adopted, so that the first interconnection structure 11 and the second interconnection structure 12 are aligned and bonded, so that the dielectric layer on the array semiconductor layer 1 is aligned with the dielectric layer on the peripheral semiconductor layer 2 And bonded.

In some other embodiments, the bonding of the two semiconductor layers can also be achieved by means of fusion bonding. That is, both the first interconnection structure 11 and the second interconnection structure 12 may be solder balls protruding from the surface of the semiconductor layer.

In the description of this specification, descriptions with reference to the terms "some embodiments", "exemplarily" and the like mean that specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or embodiment of the present disclosure. example. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limitations on the present disclosure, and those skilled in the art can understand the above-mentioned embodiments within the scope of the present disclosure. The embodiments are changed, modified, replaced and modified, so any changes or modifications made according to the claims and description of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims (15)

1. A semiconductor structure, comprising:

an array semiconductor layer having a plurality of memory blocks including a plurality of bit lines and a plurality of word lines;

a peripheral semiconductor layer bonded to the array semiconductor layer, the peripheral semiconductor layer including a word line driving region and a sense amplifying region; a sense amplifier of the sense amplifying region is electrically connected with the bit line, and a word line driver of the word line driving region is electrically connected with the word line;

the orthographic projection of the word line driving region and the sense amplifying region on the array semiconductor layer at least partially overlaps with the orthographic projection of at least one memory block on the array semiconductor layer.

2. The semiconductor structure of claim 1, wherein,

the word line drivers of the word line driving areas are electrically connected with the memory blocks in a one-to-one correspondence, and the orthographic projection of one word line driving area on the array semiconductor layer is positioned in the orthographic projection of the corresponding memory block on the array semiconductor layer; and/or the number of the groups of groups,

the sense amplifiers of the sense amplifying regions are electrically connected with the memory blocks in a one-to-one correspondence, and the orthographic projection of one sense amplifying region on the array semiconductor layer is positioned in the orthographic projection of the corresponding memory block on the array semiconductor layer.

3. The semiconductor structure of claim 2, wherein the word line extends in a first direction and the bit line extends in a second direction, the first direction being perpendicular to the second direction;

an extending direction of the word line driving region is inclined with respect to the first direction and the second direction; and/or the number of the groups of groups,

the extending direction of the sense amplifying region is inclined with respect to the first direction and the second direction.

4. The semiconductor structure of claim 3, wherein,

the included angle between the extending direction of the word line driving area and the first direction and the second direction is 30-60 degrees; and/or the number of the groups of groups,

the extending direction of the sensing amplifying region and the included angle between the first direction and the second direction are 30-60 degrees respectively.

5. The semiconductor structure of claim 4, wherein an orthographic projection of the word line driving region and/or the sense amplifying region on the array semiconductor layer covers a center position of an orthographic projection of the memory block on the array semiconductor layer.

6. The semiconductor structure of claim 2, wherein,

the word lines extend in a first direction, the bit lines extend in a second direction, and the first direction is perpendicular to the second direction;

the extending direction of the word line driving region is parallel to the first direction or the second direction, and/or the extending direction of the sense amplifying region is parallel to the first direction or the second direction.

7. The semiconductor structure of claim 1, wherein,

two adjacent storage blocks arranged in a first direction form a storage group, or two adjacent storage blocks arranged in a second direction form a storage group;

the orthographic projection of one said word line driving region on said array semiconductor layer at least partially overlaps with orthographic projections of two said memory blocks of one said memory group on said array semiconductor layer; and/or the number of the groups of groups,

the front projection of one sensing amplifying region on the array semiconductor layer is at least partially overlapped with the front projection of two memory blocks of one memory group on the array semiconductor layer.

8. The semiconductor structure of claim 7, wherein,

the word lines extend in the first direction, the bit lines extend in the second direction, and the first direction is perpendicular to the second direction;

an extending direction of the word line driving region is inclined with respect to the first direction and the second direction; and/or the number of the groups of groups,

the extending direction of the sense amplifying region is inclined with respect to the first direction and the second direction.

9. The semiconductor structure of claim 8, wherein,

the word line driving area comprises two connected first subareas, and the orthographic projections of the two first subareas on the array semiconductor layer are respectively overlapped with orthographic projections of two different memory blocks included in the corresponding memory group on the array semiconductor layer at least partially;

the word line drivers of the two first sub-regions are electrically connected to two different memory blocks, respectively, or the word line drivers of the two first sub-regions are electrically connected to one memory block in the corresponding memory group.

10. The semiconductor structure of claim 8, wherein,

the sensing amplifying region comprises two connected second sub-regions, and the orthographic projections of the two second sub-regions on the array semiconductor layer are respectively overlapped with orthographic projections of two different memory blocks included in the corresponding memory group on the array semiconductor layer at least partially;

the sense amplifiers of the two second sub-regions are electrically connected to two different memory blocks, respectively, or the sense amplifiers of the two second sub-regions are electrically connected to a corresponding one of the memory blocks in the memory group.

11. The semiconductor structure of any of claims 1-10, wherein,

the extending direction of the word line driving region and the extending direction of the sense amplifying region are parallel to each other.

12. The semiconductor structure of claim 11, wherein,

the word line driving area and the sensing amplifying area are adjacently arranged, and the word line driving area and the sensing amplifying area form a first peripheral area; the peripheral semiconductor layer further includes a second peripheral region including an address decoding circuit or a write driving circuit therein, the second peripheral region being located at least on opposite sides of the first peripheral region.

13. The semiconductor structure of any of claims 1-10, wherein the semiconductor structure further comprises:

an interconnect structure for electrically connecting the array semiconductor layer and the peripheral semiconductor layer;

a bit line connection line located at the peripheral semiconductor layer, at least a portion of the bit line connection line extending in a first direction, the bit line connection line being electrically connected to the sense amplifier of the sense amplifying region and electrically connected to the bit line through the interconnection structure;

and a word line connection line positioned on the peripheral semiconductor layer, at least part of the word line connection line extending along the second direction, the word line connection line being electrically connected with the word line driver of the word line driving region and electrically connected with the word line through the interconnection structure.

14. A memory, comprising: the semiconductor structure of any one of claims 1-13.

15. A method of forming a semiconductor structure, comprising:

providing an array semiconductor layer and forming a first interconnection structure on the array semiconductor layer, wherein the array semiconductor layer is provided with a plurality of memory blocks, and the memory blocks comprise a plurality of bit lines and a plurality of word lines;

providing a peripheral semiconductor layer and forming a second interconnection structure on the peripheral semiconductor layer, the peripheral semiconductor layer including a word line driving region and a sense amplifying region;

bonding the array semiconductor layer and the peripheral semiconductor layer through the first interconnect structure and the second interconnect structure such that orthographic projections of the word line driving region and the sense amplifying region on the array semiconductor layer at least partially overlap orthographic projections of at least one of the memory blocks on the array semiconductor layer, and electrically connecting sense amplifiers of the sense amplifying region with the bit lines, and word line drivers of the word line driving region are electrically connected with the word lines.

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