CN116209010B - A system and method for parsing downlink messages - Google Patents

A system and method for parsing downlink messages

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Publication number
CN116209010B
CN116209010B CN202310107305.1A CN202310107305A CN116209010B CN 116209010 B CN116209010 B CN 116209010B CN 202310107305 A CN202310107305 A CN 202310107305A CN 116209010 B CN116209010 B CN 116209010B
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module
data
memory
control layer
link control
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CN116209010A (en
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胡森
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Nanjing Xinjixun Communication Technology Co ltd
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Nanjing Xinjixun Communication Technology Co ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W28/00Network traffic management; Network resource management
    • H04W28/02Traffic management, e.g. flow control or congestion control
    • H04W28/06Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12Protocol engines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22Parsing or analysis of headers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

The invention relates to the technical field of mobile network access, in particular to a system and a method for analyzing downlink messages, comprising a receiving module for receiving downlink data code streams, a hardware accelerator for analyzing the downlink data code streams to obtain a plurality of message heads and protocol data units corresponding to the message heads, wherein the hardware accelerator also screens the protocol data units to obtain wireless link control layer fragment data, the hardware accelerator writes the wireless link control layer fragment data into a memory, and a processing module analyzes the wireless link control layer fragment data to obtain analysis results. The method has the advantages that the corresponding protocol data units are directly analyzed and extracted from the message header in the hardware accelerator, and then the hardware accelerator screens the fragmented data in the protocol data units and directly writes the fragmented data into the memory to be processed by the processing module, so that the processing flow of interaction with RLC software and a direct memory access controller is reduced, and the overall delay of the system is reduced.

Description

System and method for analyzing downlink message
Technical Field
The invention relates to the technical field of mobile network access, in particular to a system and a method for analyzing downlink messages.
Background
In the prior art, in order to achieve better receiving efficiency, a hardware accelerator is generally adopted to analyze the downlink data stream. Specifically, when the downlink data code stream needs to be analyzed, the processing is performed by the hardware accelerator, including the processing such as fourier transform and decoding, to obtain the part of the message header, then the part is output to the processing module, the RLC software in the processing module identifies the message header, and determines the type of the protocol data unit corresponding to each message header, if the type of the protocol data unit is the unacknowledged mode data or acknowledged mode data that needs to be further processed, the direct memory access controller (DMA) needs to be triggered by the software request to write the corresponding fragment data into the memory, and then the RLC software processes the fragment data.
However, in practical implementation, the inventor finds that the above scheme generally needs to generate multiple data exchange processes between the hardware accelerator, the processor, the direct memory access controller and the memory, which results in a lengthy overall processing flow and a large delay.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a system for analyzing the downlink message, and on the other hand, a method for analyzing the system is also provided.
The specific technical scheme is as follows:
a system for parsing a downstream message, comprising:
the receiving module receives the downlink data code stream;
The hardware accelerator is connected with the receiving module and analyzes the downlink data code stream to obtain a plurality of message heads and protocol data units corresponding to the message heads;
The hardware accelerator also screens the protocol data unit to obtain wireless link control layer fragment data;
the wireless link control layer slicing data comprises acknowledgement mode slicing data and non-acknowledgement mode slicing data;
the processing module is connected with the memory, the hardware accelerator writes the wireless link control layer slicing data into the memory, and the processing module analyzes the wireless link control layer slicing data to obtain an analysis result.
In another aspect, the hardware accelerator includes:
the analysis module acquires the downlink data code stream, matches pre-constructed configuration information in the downlink data code stream and outputs the configuration information;
The data extraction module is connected with the analysis module, and extracts the message header and the protocol data unit corresponding to each message header from the downlink data code stream according to the configuration information;
And the slicing copy module is connected with the data extraction module, screens the wireless link control layer slicing data from the protocol data unit, and writes the wireless link control layer slicing data into the memory.
In another aspect, the parsing module includes:
A subframe extraction module, which extracts data frame heads of a plurality of media access control frames from the downlink data code stream;
The identification acquisition module is connected with the subframe extraction module and acquires a logic channel identification from the data frame header;
The configuration searching module is connected with the identifier acquisition module and searches the configuration information according to the logic channel identifier.
In another aspect, the sharded copy module includes:
The judging module acquires the protocol data unit and screens the protocol data unit to obtain the wireless link control layer fragment data;
The memory selection module is connected with the judging module and is used for selecting the address of the memory according to the pre-acquired memory information to obtain a memory address;
the writing module is respectively connected with the memory selection module, the judging module and the processing module, and writes the wireless link control layer fragment data into the memory according to the memory address.
On the other hand, the analysis system further comprises a configuration module, wherein the configuration module is respectively connected with the receiving module and the hardware accelerator and is used for generating the configuration information;
the configuration module comprises:
The message acquisition module acquires a network configuration message from the receiving module;
The logic channel analysis module is connected with the message acquisition module and generates channel attributes corresponding to a plurality of logic channels according to the network configuration message;
and the information generation module is connected with the logic channel analysis module and generates the configuration information according to the channel attribute.
The method for analyzing the downlink message is suitable for the analysis system and comprises the following steps:
s1, a receiving module is adopted to receive a downlink data code stream;
S2, analyzing the downlink data code stream by adopting a hardware accelerator to obtain a plurality of message heads and protocol data units corresponding to the message heads;
Step S3, adopting the hardware accelerator to screen the protocol data unit to obtain wireless link control layer fragment data;
s4, adopting the hardware accelerator to write the wireless link control layer fragment data into a memory of a processing module;
and S5, adopting the processing module to process the wireless link control layer fragment data to obtain an analysis result.
On the other hand, the step S2 includes:
Step S21, matching configuration information corresponding to the downlink data code stream according to the downlink data code stream;
S22, extracting a message header from the downlink data code stream according to the configuration information;
Step S23, generating a plurality of protocol data units according to the message header.
On the other hand, the step S21 includes:
step S211, extracting data frame heads of a plurality of media access control frames from the downlink data code stream;
Step S212, obtaining a logic channel identification from the data frame header;
And step S213, searching the configuration information according to the logic channel identification.
On the other hand, the step S4 includes:
Step S41, address selection is carried out on the memory by pre-acquired memory information to obtain a memory address;
And step S42, writing the wireless link control layer slicing data into the memory according to the memory address.
On the other hand, before executing step S1, a configuration process is further included, where the configuration process is used to generate the configuration information;
the configuration process comprises the following steps:
A1, acquiring a network configuration message from the receiving module;
A2, generating channel attributes corresponding to a plurality of logical channels according to the network configuration message;
and A3, generating the configuration information according to the channel attribute.
The technical scheme has the following advantages or beneficial effects:
aiming at the problem that the processing flow of the fragmented data in the prior art is relatively lengthy, the scheme directly analyzes the message header in the hardware accelerator, extracts the corresponding protocol data unit, and then screens the fragmented data in the protocol data unit through the hardware accelerator and directly writes the fragmented data into the memory to be processed by the processing module, thereby reducing the processing flow of interaction with RLC software and a direct memory access controller and reducing the overall delay of the system.
Drawings
Embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The drawings, however, are for illustration and description only and are not intended as a definition of the limits of the invention.
FIG. 1 is an overall schematic of an embodiment of the present invention;
FIG. 2 is a schematic diagram of a hardware accelerator according to an embodiment of the invention;
FIG. 3 is a schematic diagram of an analysis module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a sliced copy module in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a configuration module according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an analysis method according to an embodiment of the present invention;
FIG. 7 is a schematic diagram showing the substep of step S2 in the embodiment of the invention;
FIG. 8 is a schematic diagram showing the substep of step S21 in an embodiment of the present invention;
FIG. 9 is a schematic diagram of the substep of step S4 in the embodiment of the invention;
fig. 10 is a schematic diagram of a configuration process in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The invention comprises the following steps:
a system for parsing a downlink message, as shown in fig. 1, includes:
the receiving module 1, the receiving module 1 receives the downstream data code stream;
the hardware accelerator 2 is connected with the receiving module 1, and the hardware accelerator 2 analyzes the downlink data stream to obtain a plurality of message heads and protocol data units corresponding to the message heads;
The hardware accelerator 2 also screens out the wireless link control layer fragment data from the protocol data unit;
The radio link control layer fragmentation data comprises acknowledged mode fragmentation data and unacknowledged mode fragmentation data;
The processing module 3 is connected with the memory 4, the hardware accelerator 2 writes the wireless link control layer slicing data into the memory 4, and the processing module 3 analyzes the wireless link control layer slicing data to obtain an analysis result.
Specifically, in order to solve the problem that the processing flow of the radio link control layer fragment data is relatively lengthy in the prior art, the scheme improves the hardware accelerator 2, and after the receiving module 1 receives the downlink data code stream, the message header is directly analyzed in the hardware accelerator 2, and the corresponding protocol data unit is extracted. And then, the hardware accelerator 2 screens the wireless link control layer fragment data contained in the protocol data unit, and the wireless link control layer fragment data obtained by screening is directly written into the memory to be processed by the processing module 3, so that the processing flow of interaction with RLC software and a direct memory access controller is reduced, and the overall delay of the system is reduced.
In one embodiment, as shown in fig. 2, the hardware accelerator 2 includes:
The analysis module 21, the analysis module 21 obtains the downstream data stream and matches the pre-constructed configuration information in the downstream data stream and outputs the configuration information;
the data extraction module 22, the data extraction module 22 is connected with the analysis module 21, the data extraction module 22 extracts message heads from the downlink data code stream according to the configuration information, and protocol data units corresponding to each message head;
the slicing copy module 23, the slicing copy module 23 is connected with the data extraction module 22, the slicing copy module 23 screens out the wireless link control layer slicing data from the protocol data unit, and writes the wireless link control layer slicing data into the memory 4.
Specifically, to implement the process of directly writing the radio link control layer slice data into the memory 4, in this embodiment, the slice copy module 23 is further disposed in the hardware accelerator 2 by modifying the hardware accelerator. When receiving the downlink data code stream, the parsing module 21 matches configuration information configured in advance according to the network according to the downlink data code stream, thereby obtaining configuration information corresponding to the current network. The data extraction module 22 then further processes the downstream data stream according to the configuration information to obtain protocol data units corresponding to the respective layers, including a medium access control layer, a radio link control layer, a packet data convergence control layer, a service discovery application specification layer, and the like. The protocol data unit of the radio link control layer is a protocol data unit possibly containing the slicing data of the radio link control layer. For the part of the protocol data unit, the data extraction module 22 is modified in this embodiment, so that the extraction of the protocol data unit is realized while the header message is parsed. Then, the slicing copy module 23 writes the part containing the slicing data of the radio link control layer in the protocol data unit obtained by analysis into the memory, so as to realize the direct writing process of the memory, and simplify the original processes of message processing and DMA hardware interaction.
In one embodiment, as shown in fig. 3, the parsing module 21 includes:
The sub-frame extraction module 211, the sub-frame extraction module 211 extracts the data frame heads of a plurality of media access control frames from the downlink data code stream;
The identification acquisition module 212 is connected with the subframe extraction module 211, and the identification acquisition module 212 acquires the logic channel identification from the data frame header;
the configuration searching module 213 is connected with the identifier obtaining module 212, and the configuration searching module 213 searches the configuration information according to the logic channel identifier.
Specifically, in order to implement the process of searching the configuration information, in this embodiment, after the downlink data stream is acquired, the subframe extraction module 211 analyzes the downlink data stream, so as to acquire data frames of a plurality of media access control frames, and then, extracts a data frame header for each data frame. After the data frame header is extracted, the identifier obtaining module 212 may analyze the data frame header, thereby obtaining a logical channel identifier (lcid), so that the configuration searching module 213 may find the configuration information corresponding to the logical channel according to the logical channel identifier, and implement a searching process for the configuration information.
In one embodiment, as shown in FIG. 4, the sharded copy module 23 includes:
The judging module 231, the judging module 231 obtains the protocol data unit, and screens out the wireless link control layer slicing data from the protocol data unit;
the memory selection module 232, the memory selection module 232 is connected with the judging module 231, and the memory selection module 232 performs address selection on the memory according to the pre-acquired memory information to obtain a memory address;
The writing module 233, the writing module 233 is respectively connected to the memory selecting module 232, the judging module 231 and the processing module 3, and the writing module 233 writes the radio link control layer slice data into the memory according to the memory address.
Specifically, in the embodiment, by setting the slicing copy module 23 in the hardware accelerator 2, the slicing copy module 23 includes the discriminating module 231, and the matching can be performed according to a preconfigured rule, so that the corresponding slicing data of the radio link control layer can be found in the protocol data unit. Then, the memory selection module 232 selects the memory location where the segmented data of each radio link control layer can be written according to the preconfigured memory information, including the RLC memory segmentation situation, so as to generate a corresponding memory address, and the writing module 233 directly writes the memory according to the memory address, so that the process of resolving through RLC software and triggering the writing of the request by the DMA hardware in the prior art is replaced, and the processing flow is simplified.
In one embodiment, the parsing system further includes a configuration module 5, where the configuration module 5 is connected to the receiving module 1 and the hardware accelerator 2, and the configuration module 5 is used to generate configuration information;
as shown in fig. 5, the configuration module 5 includes:
A message obtaining module 51, where the message obtaining module 51 obtains a network configuration message from the receiving module 1;
The logic channel analysis module 52, the logic channel analysis module 52 is connected with the message acquisition module 51, and the logic channel analysis module 52 generates channel attributes corresponding to a plurality of logic channels according to the network configuration message;
The information generating module 53, the information generating module 53 connects the logical channel analyzing module 52, the information generating module generates configuration information according to the channel attribute.
Specifically, in order to generate the configuration information, in this embodiment, a configuration module 5 is further provided in the parsing system, where the configuration module 5 can configure channel attributes of each logical channel in the hardware accelerator 2 through the acquired network configuration message, including characteristics such as a logical channel ID, a downlink rl mode, a downlink pdcp mode, whether to configure sdap bits, and the like, and construct configuration information to store in the hardware accelerator 2 for processing by a subsequent hardware accelerator.
The method for analyzing the downlink message is suitable for the analysis system, as shown in fig. 6, and includes:
s1, a receiving module is adopted to receive a downlink data code stream;
s2, analyzing the downlink data code stream by adopting a hardware accelerator to obtain a plurality of message heads and protocol data units corresponding to the message heads;
step S3, adopting a hardware accelerator to screen the protocol data unit to obtain the wireless link control layer fragment data;
S4, adopting a hardware accelerator to write the wireless link control layer fragment data into a memory of the processing module;
and S5, processing the wireless link control layer fragment data by adopting a processing module to obtain an analysis result.
Specifically, the method aims at the problem that the wireless link control layer slicing data processing flow is relatively lengthy in the prior art, and the scheme is characterized in that a hardware accelerator is improved, and after a receiving module receives a downlink data code stream, a message header is directly analyzed in the hardware accelerator to extract a corresponding protocol data unit. And then, the hardware accelerator screens the wireless link control layer fragment data contained in the protocol data unit, and the wireless link control layer fragment data obtained by screening is directly written into the memory to be processed by the processing module, so that the processing flow of interaction with RLC software and a direct memory access controller is reduced, and the overall delay of the system is reduced.
In one embodiment, as shown in fig. 7, step S2 includes:
step S21, matching configuration information corresponding to the downlink data code stream according to the downlink data code stream;
s22, extracting a message header from the downlink data code stream according to the configuration information;
step S23, generating a plurality of protocol data units according to the message header.
Specifically, in order to implement the process of directly writing the radio link control layer fragment data into the memory 4, in this embodiment, when the downlink data code stream is received, configuration information configured in advance according to the network is matched according to the downlink data code stream, so as to obtain configuration information corresponding to the current network. And then, further processing the downlink data code stream according to the configuration information, thereby obtaining protocol data units corresponding to each layer, including a media access control layer, a radio link control layer, a packet data convergence control layer, a service discovery application specification layer and the like. The protocol data unit of the radio link control layer is a protocol data unit possibly containing the slicing data of the radio link control layer. For the partial protocol data unit, in this embodiment, the data extraction module is modified to parse the header message and simultaneously realize extraction of the protocol data unit. And then, writing the part containing the radio link control layer fragment data in the analyzed protocol data unit into the memory so as to realize the direct writing process of the memory, and simplifying the original processes of message processing and DMA hardware interaction.
In one embodiment, as shown in fig. 8, step S21 includes:
step S211, extracting data frame heads of a plurality of media access control frames from the downlink data code stream;
Step S212, obtaining logic channel identification from the data frame head;
Step S213, searching configuration information according to the logic channel identification.
Specifically, in order to implement the process of searching the configuration information, in this embodiment, after the downlink data stream is obtained, the downlink data stream is parsed, so as to obtain data frames of a plurality of media access control frames, and then, for each data frame, a data frame header is extracted respectively. After the data frame header is extracted, the data frame header can be further analyzed, so that a logic channel identifier (lcid) is obtained, and further, the configuration information corresponding to the logic channel is detected according to the logic channel identifier, so that the searching process of the configuration information is realized.
In one embodiment, as shown in fig. 9, step S4 includes:
step S41, address selection is carried out on the memory by the pre-acquired memory information to obtain a memory address;
And step S42, the wireless link control layer slicing data are written into the memory according to the memory address.
Specifically, in this embodiment, after searching for the protocol data unit and rule matching are completed to obtain the radio link control layer slicing data, the memory location where each radio link control layer slicing data can be written is selected according to the preconfigured memory information including RLC memory slicing condition, so as to generate a corresponding memory address, and the memory is written according to the memory address, thereby replacing the process of resolving and triggering the request to write by DMA hardware through RLC software in the prior art, and simplifying the processing flow.
In one embodiment, before executing step S1, the method further includes a configuration process for generating configuration information;
As shown in fig. 10, the configuration process includes:
A1, acquiring a network configuration message from a receiving module;
a2, generating channel attributes corresponding to a plurality of logical channels according to the network configuration message;
and A3, generating configuration information according to the channel attribute.
Specifically, in order to generate the configuration information, in this embodiment, a configuration process is further set before the parsing is actually performed, and in this configuration process, the channel attribute of each logical channel in the hardware accelerator is configured through the acquired network configuration message, including the characteristics of the logical channel ID, the downlink rl mode, the downlink pdcp mode, whether to configure sdap bits, and the like, and the configuration information is constructed and stored in the hardware accelerator for processing by the subsequent hardware accelerator.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included in the scope of the present invention.

Claims (8)

1. A system for parsing a downstream message, comprising:
the receiving module receives the downlink data code stream;
The hardware accelerator is connected with the receiving module and analyzes the downlink data code stream to obtain a plurality of message heads and protocol data units corresponding to the message heads;
The hardware accelerator also screens the protocol data unit to obtain wireless link control layer fragment data;
the wireless link control layer slicing data comprises acknowledgement mode slicing data and non-acknowledgement mode slicing data;
the processing module is connected with the memory, the hardware accelerator writes the wireless link control layer slicing data into the memory, and the processing module analyzes the wireless link control layer slicing data to obtain an analysis result;
The hardware accelerator includes:
the analysis module acquires the downlink data code stream, matches pre-constructed configuration information in the downlink data code stream and outputs the configuration information;
The data extraction module is connected with the analysis module, and extracts the message header and the protocol data unit corresponding to each message header from the downlink data code stream according to the configuration information;
The slicing copy module is connected with the data extraction module, screens the protocol data units to obtain the wireless link control layer slicing data, and writes the wireless link control layer slicing data into the memory;
the sliced copy module comprises:
The judging module acquires the protocol data unit and screens the protocol data unit to obtain the wireless link control layer fragment data;
The memory selection module is connected with the judging module and is used for selecting the address of the memory according to the pre-acquired memory information to obtain a memory address;
the writing module is respectively connected with the memory selection module, the judging module and the processing module, and writes the wireless link control layer fragment data into the memory according to the memory address;
The judging module searches the corresponding wireless link control layer fragment data according to a preset rule;
the memory selection module selects memory positions where the segmented data of each radio link control layer can be written according to the RLC memory segmentation condition, so as to generate corresponding memory addresses.
2. The parsing system of claim 1, wherein the parsing module comprises:
A subframe extraction module, which extracts data frame heads of a plurality of media access control frames from the downlink data code stream;
The identification acquisition module is connected with the subframe extraction module and acquires a logic channel identification from the data frame header;
The configuration searching module is connected with the identifier acquisition module and searches the configuration information according to the logic channel identifier.
3. The parsing system of claim 2 further comprising a configuration module, the configuration module being coupled to the receiving module and the hardware accelerator, respectively, the configuration module being configured to generate the configuration information;
the configuration module comprises:
The message acquisition module acquires a network configuration message from the receiving module;
The logic channel analysis module is connected with the message acquisition module and generates channel attributes corresponding to a plurality of logic channels according to the network configuration message;
and the information generation module is connected with the logic channel analysis module and generates the configuration information according to the channel attribute.
4. A method for parsing a downlink message, which is applicable to the parsing system according to any one of claims 1 to 3, and includes:
s1, a receiving module is adopted to receive a downlink data code stream;
S2, analyzing the downlink data code stream by adopting a hardware accelerator to obtain a plurality of message heads and protocol data units corresponding to the message heads;
Step S3, adopting the hardware accelerator to screen the protocol data unit to obtain wireless link control layer fragment data;
s4, adopting the hardware accelerator to write the wireless link control layer fragment data into a memory of a processing module;
and S5, adopting the processing module to process the wireless link control layer fragment data to obtain an analysis result.
5. The parsing method according to claim 4, wherein the step S2 includes:
Step S21, matching configuration information corresponding to the downlink data code stream according to the downlink data code stream;
S22, extracting a message header from the downlink data code stream according to the configuration information;
Step S23, generating a plurality of protocol data units according to the message header.
6. The parsing method according to claim 5, wherein the step S21 includes:
step S211, extracting data frame heads of a plurality of media access control frames from the downlink data code stream;
Step S212, obtaining a logic channel identification from the data frame header;
And step S213, searching the configuration information according to the logic channel identification.
7. The parsing method according to claim 5, wherein the step S4 includes:
Step S41, address selection is carried out on the memory by pre-acquired memory information to obtain a memory address;
And step S42, writing the wireless link control layer slicing data into the memory according to the memory address.
8. The parsing method according to claim 5, further comprising a configuration process for generating the configuration information before performing step S1;
the configuration process comprises the following steps:
A1, acquiring a network configuration message from the receiving module;
A2, generating channel attributes corresponding to a plurality of logical channels according to the network configuration message;
and A3, generating the configuration information according to the channel attribute.
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