CN116317543B - Charge pump circuit - Google Patents
Charge pump circuitInfo
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- CN116317543B CN116317543B CN202310341188.5A CN202310341188A CN116317543B CN 116317543 B CN116317543 B CN 116317543B CN 202310341188 A CN202310341188 A CN 202310341188A CN 116317543 B CN116317543 B CN 116317543B
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- charge pump
- voltage
- power supply
- supply voltage
- circuit
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Abstract
The invention discloses a charge pump circuit, which comprises an auxiliary charge pump and a main charge pump. The power end of the auxiliary charge pump is connected with the first power voltage, and the output end outputs the first output voltage. The grid electrode of the first NMOS tube is connected with a first output voltage, the drain electrode of the first NMOS tube is connected with a second power supply voltage, the source electrode of the first NMOS tube outputs a third power supply voltage, and the first NMOS tube has a first threshold voltage. The power end of the main charge pump is connected with the third power voltage, and the output end outputs the second output voltage. The second power supply voltage is larger than the first power supply voltage, and the second power supply voltage has a first variation range. The first output voltage is in the first variation range, and when the second power supply voltage is larger than the first output voltage, the third power supply voltage is clamped at the first output voltage minus the first threshold voltage. The third power supply voltage has a second variation range, and the second variation range is reduced from an upper limit value of the first variation range. The invention can prevent the ripple defect of the output voltage and improve the area efficiency.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a charge pump circuit.
Background
With the development of semiconductor technology, the operating voltage of the device is lower and lower, and the power supply voltage required for the operation of the memory is continuously reduced to be lower than 2.5V, 1.8V or 1V. The program and erase voltages of the memory, however, can be much greater than the supply voltage, i.e., the program and erase voltages of the memory are high relative to the supply voltage, and charge pump circuitry is typically required to convert the supply voltage to the desired program or erase voltage, and in integrated circuits, both positive and negative voltages are often required.
As shown in fig. 1, which is a structural diagram of a conventional first charge pump circuit, a power supply terminal of the charge pump 101 is connected to a lower power supply voltage VDD1, and fig. 1 also shows that the power supply voltage VDD1 is 0.9v to 1.1v, which can be different from 0.9v to 1.1v according to practical applications. When the capacitor stores charges, when the voltage of one electrode is suddenly changed, the voltage of the other electrode is suddenly changed, so that the voltage difference between the two electrodes is kept unchanged, when the voltage of one electrode is the power supply voltage VDD1, the voltage of the other electrode is larger than the power supply voltage VDD1, so that the voltage is increased, and a high voltage HV which is much larger than the power supply voltage VDD1 can be obtained at the output end through cascading of a plurality of charge pump units. The size of the high voltage HV is determined by the needs of the chip, such as a memory, including flash memory.
As shown in fig. 2, which is a structural diagram of a conventional second charge pump circuit, a power supply terminal of the charge pump 201 is connected to a lower power supply voltage VDD2, and fig. 1 also shows that the power supply voltage VDD2 is 1.35v to 5.5v, which can be different from 1.35v to 5.5v according to practical applications. The difference between the prior art second charge pump circuit shown in fig. 2 and the prior art first charge pump circuit shown in fig. 1 is that the power supply voltage VDD2 is greater than the power supply voltage VDD1, so that when the high voltage HV of the same size is obtained, the ratio between the high voltage HV and the power supply voltage VDD2 is smaller than the ratio between the high voltage HV and the power supply voltage VDD1, so that the number of cascaded charge pump cells required by the prior art second charge pump circuit is reduced, the capacitance area is reduced, and the area efficiency is improved and the area of the whole charge pump is reduced.
However, although the area of the conventional charge pump circuit of the second type shown in fig. 2 can be reduced, the power supply voltage VDD2 has a larger variation range, and when the power supply voltage VDD2 is higher, for example, close to 5.5V, the output high voltage HV generates larger ripple, that is, the high voltage HV is not very stable, but the high voltage HV is fluctuated up and down, that is, has larger jitter, which is unfavorable for performing corresponding erasing or writing operations on the memory. In the conventional first charge pump circuit shown in fig. 1, the value of the power supply voltage VDD1 is smaller than the lower limit value of the power supply voltage VDD2, and finally the value of the high voltage HV is very stable, so that jitter is not generated.
Therefore, the conventional first type charge pump circuit and the conventional second type charge pump circuit have advantages and disadvantages, respectively, in that the conventional first type charge pump circuit can generate stable output voltage, but has low area efficiency, and when the same high voltage HV is output, the conventional first type charge pump circuit has larger area than the conventional second type charge pump circuit, and the increase of the area increases the cost. While the area efficiency of the conventional second charge pump circuit is improved, the output high voltage HV is liable to be dithered, and the reliability is affected by the increase of the dithering of the high voltage HV.
Disclosure of Invention
The invention aims to solve the technical problem of providing a charge pump circuit which can prevent ripple defects of output voltage and improve area efficiency at the same time so as to reduce circuit area.
In order to solve the technical problems, the charge pump circuit provided by the invention comprises an auxiliary charge pump and a main charge pump.
The power end of the auxiliary charge pump is connected with a first power voltage, and the output end of the auxiliary charge pump outputs a first output voltage.
The grid electrode of the first NMOS tube is connected with the first output voltage, the drain electrode of the first NMOS tube is connected with the second power supply voltage, the source electrode of the first NMOS tube outputs the third power supply voltage, and the threshold voltage of the first NMOS tube is the first threshold voltage.
The power end of the main charge pump is connected with the third power voltage, and the output end of the main charge pump outputs a second output voltage.
The second power supply voltage is larger than the first power supply voltage, the second power supply voltage has a first variation range, the lower limit value of the first variation range is a first voltage value, and the upper limit value of the first variation range is a second voltage value.
The first output voltage is within the first variation range, and the third power supply voltage is clamped at the first output voltage minus the first threshold voltage when the second power supply voltage is greater than the first output voltage.
The third power supply voltage has a second variation range, a lower limit value of the second variation range is a first voltage value, and an upper limit value of the second variation range is a difference value between the first output voltage and the first threshold voltage.
The auxiliary charge pump ensures the stability of the first output voltage and thus the stability of the upper limit value of the second variation range, the second variation range eliminates the ripple defect of the second output voltage caused by the second power supply voltage which is above the upper limit value of the second variation range in the first variation range, and the voltage of the second variation range is larger than the first power supply voltage, so that the area efficiency of the main charge pump is increased.
A further improvement is that the second power supply voltage is an internal voltage of the chip.
A further improvement is that the chip comprises a flash memory chip.
The chip is a dual-power chip, and the first power supply voltage is also the internal voltage of the chip.
The chip is a single power supply chip, the first power supply voltage is the output voltage of a low dropout linear regulator (LDO) circuit, and the power supply end of the LDO circuit is connected with the second power supply voltage.
The first NMOS tube adopts an intrinsic NMOS tube, and the first threshold voltage is equal to 0V.
In a further improvement, the auxiliary charge pump comprises a multi-stage auxiliary charge pump unit, wherein the auxiliary charge pump unit comprises a first switch circuit and a first capacitor, the first switch circuit is controlled by a first clock signal, and the high level of the first clock signal is the first power supply voltage.
In a further improvement, the main charge pump comprises a multi-stage main charge pump unit, wherein the main charge pump unit comprises a second switch circuit and a second capacitor, the second switch circuit is controlled by a second clock signal, and the high level of the second clock signal is the third power supply voltage.
The input end of the auxiliary charge pump unit of the first stage is also connected with the first power supply voltage, and the input end of the auxiliary charge pump unit of each stage above the second stage is connected with the output end of the auxiliary charge pump unit of the previous stage.
The main charge pump comprises a positive-pressure main voltage pump, wherein in the positive-pressure main voltage pump, the input end of a first-stage main charge pump unit is connected with the second power supply voltage, and the input end of each stage above the second stage is connected with the output end of a previous-stage main charge pump unit.
The main charge pump comprises a negative-pressure main voltage pump, wherein in the negative-pressure main voltage pump, the input end of a main charge pump unit of a first stage is connected with the ground, and the input end of each stage of the main charge pump unit above a second stage is connected with the output end of a main charge pump unit of a previous stage.
The first variation range of the second power supply voltage is 1.35V-5.5V.
The variation range of the first power supply voltage is 0.9V-1.1V.
The second output voltage is 8V or more.
The further improvement is that the first output voltage takes a value in 1.5V-1.8V.
The first variation range of the second power supply voltage is 1.35V-5.5V;
The second output voltage is 8V or more.
The further improvement is that the first power supply voltage takes 1.35V, and the first output voltage takes a value in 1.5V-1.8V.
The charge pump circuit of the invention is not a charge pump structure adopting single power supply voltage, but a charge pump structure with double power supply voltages, which is an auxiliary charge pump adopting first power supply voltage and a main charge pump adopting second power supply voltage respectively, because the second power supply voltage is larger, the area efficiency is higher, namely, when the same high voltage is obtained, the larger the power supply voltage is, the smaller the required level and the capacitance area are, the area efficiency is higher, and finally, the circuit area can be reduced, namely, compared with the charge pump structure adopting the prior single power supply voltage with lower first power supply voltage, the area of the charge pump circuit of the invention is smaller, and the area reduction can reduce the cost of a chip.
Meanwhile, because the change range of the second power supply voltage is larger, the invention does not directly connect the second power supply voltage to the power supply end of the main charge pump, but clamps the upper limit value of the second power supply voltage by utilizing the auxiliary charge pump, so that the change range of the third power supply voltage actually connected to the power supply end of the main charge pump, namely the second change range, is smaller and the upper limit value is stable, and the output voltage ripple is different from that of the charge pump adopting the existing single power supply voltage of the second power supply voltage.
Therefore, the invention can prevent the ripple defect of the output voltage, and can improve the area efficiency and reduce the circuit area.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a block diagram of a prior art first charge pump circuit;
FIG. 2 is a block diagram of a second prior art charge pump circuit;
fig. 3 is a block diagram of a charge pump circuit according to a first embodiment of the present invention;
fig. 4 is a block diagram of a charge pump circuit according to a second embodiment of the present invention.
Detailed Description
As shown in fig. 3, which is a block diagram of a charge pump circuit according to a first embodiment of the present invention, the charge pump circuit according to the first embodiment of the present invention includes an auxiliary charge pump 201 and a main charge pump.
In the first embodiment of the present invention, the main charge pump includes a positive-voltage main voltage pump 202a and a negative-voltage main voltage pump 202b. In fig. 2, the auxiliary charge pump 201 is also denoted by charge pump1, the positive-voltage main voltage pump 202a is also denoted by charge pump2, and the negative-voltage main voltage pump 202b is also denoted by charge pump 3.
The power end of the auxiliary charge pump 201 is connected to the first power voltage VDD1, and the output end of the auxiliary charge pump 201 outputs the first output voltage Vout1.
The grid electrode of the first NMOS tube is connected with the first output voltage Vout1, the drain electrode of the first NMOS tube is connected with the second power supply voltage VDD2, the source electrode of the first NMOS tube outputs the third power supply voltage VDD3, and the threshold voltage of the first NMOS tube is the first threshold voltage.
In some embodiments, the first NMOS transistor is an intrinsic NMOS transistor, and the first threshold voltage is equal to 0V.
The power end of the main charge pump is connected with the third power voltage VDD3, and the output end of the main charge pump outputs a second output voltage. In the first embodiment of the present invention, the second output voltage outputted by the positive voltage main voltage pump 202a is a positive high voltage HV, and the second output voltage outputted by the negative voltage main voltage pump 202b is a negative high voltage VNEG.
The second power supply voltage VDD2 is larger than the first power supply voltage VDD1, the second power supply voltage VDD2 has a first variation range, the lower limit value of the first variation range is a first voltage value, and the upper limit value of the first variation range is a second voltage value.
The first output voltage Vout1 is within the first variation range, and when the second power voltage VDD2 is greater than the first output voltage Vout1, the third power voltage VDD3 is clamped at the first output voltage Vout1 minus the first threshold voltage.
The third power supply voltage VDD3 has a second variation range, a lower limit value of the second variation range is a first voltage value, and an upper limit value of the second variation range is a difference value between the first output voltage Vout1 and the first threshold voltage.
The auxiliary charge pump 201 ensures the stability of the first output voltage Vout1 and thus the upper limit value of the second variation range, which eliminates the ripple defect of the second output voltage caused by the second power supply voltage VDD2 located above the upper limit value of the second variation range in the first variation range, and the voltage of the second variation range is greater than the first power supply voltage VDD1 while increasing the area efficiency of the main charge pump.
In the first embodiment of the present invention, the auxiliary charge pump 201 includes a multi-stage auxiliary charge pump unit, where the auxiliary charge pump unit includes a first switch circuit and a first capacitor, the first switch circuit is controlled by a first clock signal, and a high level of the first clock signal is the first power supply voltage VDD1.
The input end of the auxiliary charge pump unit of the first stage is also connected with the first power supply voltage VDD1, and the input end of the auxiliary charge pump unit of each stage above the second stage is connected with the output end of the auxiliary charge pump unit of the previous stage.
In a first embodiment of the present invention, the main charge pump includes a multi-stage main charge pump unit, where the main charge pump unit includes a second switch circuit and a second capacitor, the second switch circuit is controlled by a second clock signal, and a high level of the second clock signal is the third power supply voltage VDD3.
In the first embodiment of the present invention, in the positive-voltage main voltage pump 202a, the input end of the main charge pump unit of the first stage is connected to the second power supply voltage VDD2, and the input end of the main charge pump unit of each stage above the second stage is connected to the output end of the main charge pump unit of the previous stage, so that on the basis of the second power supply voltage VDD2, the output voltage of the main charge pump unit of each stage is gradually increased and finally positive high voltage HV is output.
The main charge pump includes a negative-pressure main voltage pump 202b, in the negative-pressure main voltage pump 202b, an input end of the main charge pump unit of a first stage is connected to the ground, an input end of the main charge pump unit of each stage above a second stage is connected to an output end of the main charge pump unit of a previous stage, so that on the basis of the ground, an output voltage of the main charge pump unit of each stage is gradually reduced and finally negative high voltage VNEG is output.
In the first embodiment of the present invention, the chip applied by the charge pump circuit is a dual power chip. The first power supply voltage VDD1 and the second power supply voltage VDD2 are internal voltages of the chip.
The chip includes a flash memory chip.
In some embodiments, the first variation range of the second power supply voltage VDD2 is 1.35V to 5.5V, the first voltage value is 1.35V, and the second voltage value is 5.5V. The variation range of the first power supply voltage VDD1 is 0.9v to 1.1v. The second output voltage is 8V or more. The first output voltage Vout1 takes a value in 1.5v to 1.8 v.
In other embodiments, the variation range of the first power supply voltage VDD1 can also be changed according to the actual process requirement, and the first variation range of the second power supply voltage VDD2 can also be changed according to the actual process requirement. The magnitude of the first output voltage Vout1 can be changed correspondingly, and only the second output voltage is ensured not to have ripple defects.
The charge pump circuit of the first embodiment of the present invention is not a charge pump structure with a single power supply voltage, but a charge pump structure with a dual power supply voltage, which is an auxiliary charge pump 201 with a first power supply voltage VDD1 and a main charge pump with a second power supply voltage VDD2 respectively, and the area efficiency is higher because the second power supply voltage VDD2 is larger, i.e. when the same high voltage is obtained, the larger the power supply voltage is, the smaller the required number of stages and the capacitance area is, so the area efficiency is higher, and finally the circuit area can be reduced, i.e. compared with the charge pump structure with the existing single power supply voltage with the lower first power supply voltage VDD1, the area of the charge pump circuit of the first embodiment of the present invention is smaller, and the cost of the chip can be reduced due to the area reduction.
Meanwhile, since the variation range of the second power supply voltage VDD2 is larger, the first embodiment of the present invention does not directly connect the second power supply voltage VDD2 to the power supply terminal of the main charge pump, but clamps the upper limit value of the second power supply voltage VDD2 by using the auxiliary charge pump 201, so that the variation range of the third power supply voltage VDD3 actually connected to the power supply terminal of the main charge pump, that is, the second variation range becomes smaller and the upper limit value is stable, and thus, the output voltage ripple is different from that of the existing charge pump adopting the single power supply voltage of the second power supply voltage VDD2, and the first embodiment of the present invention can eliminate the ripple defect of the output voltage of the whole charge pump circuit, that is, the second output voltage.
Therefore, the first embodiment of the present invention can prevent ripple defect of the output voltage, and can also improve the area efficiency to reduce the circuit area.
As shown in fig. 4, which is a structural diagram of a charge pump circuit according to a second embodiment of the present invention, the charge pump circuit according to the second embodiment of the present invention is different from the charge pump circuit according to the first embodiment of the present invention in that:
The chip is a single power supply chip, and only one internal power supply voltage of the chip is the second power supply voltage VDD2. Since the first power supply voltage VDD1 is not present, the LDO circuit 203 is required in the second embodiment of the present invention, the first power supply voltage VDD1 is the output voltage of the LDO circuit 203, and the power terminal of the LDO circuit 203 is connected to the second power supply voltage VDD2.
In some embodiments, the first variation range of the second power supply voltage VDD2 is 1.35v to 5.5v. The second output voltage is 8V or more. The LDO circuit 203 can obtain the first power voltage VDD1 more accurately, for example, the first power voltage VDD1 takes 1.35V, and the first output voltage Vout1 takes a value in 1.5V to 1.8V. In other embodiments, the value of the first power supply voltage VDD1 can also be changed according to the actual process requirement, and the first variation range of the second power supply voltage VDD2 can also be changed according to the actual process requirement. The magnitude of the first output voltage Vout1 can be changed correspondingly, and only the second output voltage is ensured not to have ripple defects.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310341188.5A CN116317543B (en) | 2023-03-31 | Charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310341188.5A CN116317543B (en) | 2023-03-31 | Charge pump circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116317543A CN116317543A (en) | 2023-06-23 |
| CN116317543B true CN116317543B (en) | 2026-03-31 |
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