CN116830241A

CN116830241A - Integrated approach for low-cost wide-bandgap semiconductor device fabrication

Info

Publication number: CN116830241A
Application number: CN202180080102.7A
Authority: CN
Inventors: T·S·拉维; B·P·戈戈伊
Original assignee: Ultra Thin Silicon Carbide Co
Current assignee: Ultra Thin Silicon Carbide Co
Priority date: 2020-11-30
Filing date: 2021-11-29
Publication date: 2023-09-29

Abstract

A method for manufacturing a wide band gap semiconductor device using a substrate of a SiC wafer is disclosed. The method includes coating a substrate with a hard mask material, performing photolithography to define patterned openings in the hard mask material of the substrate, etching the substrate to form patterned trenches from the defined patterned openings, removing the hard mask from the substrate using a chemical process, cleaning the substrate with the patterned trenches, performing epitaxy on the substrate to form a uniform monocrystalline layer over the patterned trenches to create a plurality of micro-voids, performing another epitaxy on the substrate using a rapid epitaxial growth process to provide an active device epitaxial layer suitable for manufacturing SiC devices, and, after manufacture of the SiC devices, cutting the plurality of micro-voids to extract the SiC devices from the substrate of the SiC wafer.

Description

Integrated method for low cost wide bandgap semiconductor device fabrication

Cross reference

The present application claims priority from provisional patent application filed on 11/119,541 in 2020, having application number 63/119,541 as an integrated process for manufacturing low cost wide bandgap semiconductor devices. Said application is incorporated herein by reference in its entirety.

Technical Field

The present application relates to a method for manufacturing semiconductors in power electronics and, in particular, to a method for manufacturing wide bandgap semiconductors with reduced substrate costs.

Background

In recent years, the use of Wide Bandgap (WBG) semiconductors in power electronics has increased significantly. Their ability to operate efficiently at higher voltages, power, temperature, and switching frequencies has enabled reduced cooling requirements, reduced parts count, and the use of smaller passive components. WBG-based power electronics can further reduce the footprint and potential system costs of various renewable energy electrical devices such as motor drives and inverters.

Among WBG semiconductors for power electronics, silicon carbide (SiC) has now been increasingly used for high voltage drivers (> 1200V), while gallium nitride (GaN) has undergone increasing use in both higher power applications and higher frequency applications. However, unlike silicon, the cost of the final device for WBG semiconductor devices is dominated by the cost of the material. The material includes a substrate and an active layer grown by epitaxy. The substrate itself contributes more than half the cost of the completed WBG semiconductor device.

From a substrate perspective, 4H-silicon carbide (SiC) single crystal substrates have been used for both SiC devices and GaN devices, since SiC epitaxial layers and GaN epitaxial layers can be grown on SiC substrates with reduced defects. On the other hand, gaN substrates grow defect-free and are very expensive and do not keep pace with the growth in scale provided by SiC substrates. Although SiC substrate quality has been significantly improved in recent years, since substrate fabrication is a complex process that begins with ingot growth, followed by ingot slicing, then wire saw of individual wafers, and finally grinding and polishing of the substrate, and up to now, there is no proven practical method of eliminating any of these foregoing steps, the cost has not been reduced.

As semiconductor substrates for WBG semiconductors are produced and devices using high currents are manufactured, defects play a greater role and are amplified because die sizes are larger and any defects will result in more significant yield loss and potentially lower reliability. Therefore, in order to maximize die yield, any cost reduction activity with respect to the substrate is critical, while also maintaining a low defect density in the active epitaxial layer. To date, there have been two main approaches to reduce the contribution of the substrate to die cost while maintaining low defect densities.

The first method is to grow larger substrates. Many companies have commercialized 150mm SiC substrates with reduced defects and are also striving to further increase the substrate size to 200mm. However, 200mm SiC is expected to take years before it can be commercialized. The majority of the increase in wafer size depends on the development and deployment of next generation crystal growth systems.

The second method is to extract the substrate from the ingot without saw grooves (kerflingty). There are several processes currently being explored and implemented. The first process involves using a femtosecond laser to generate a subsurface damage layer and using the subsurface damage layer as a cleavage plane for extracting a wafer thereon by a method such as cold-splitting, whereby abrupt thermal shock will allow cleavage. The second process is known as SmartCut for wafer splitting ^TM Is known from SOITEC, whereby hydrogen is implanted into the substrate to create a damaged area and a thermal shock is applied to extract the wafer remaining over the damaged area.

However, since yield loss increases during the lysis process, none of these methods is yet far from easily commercialized. In addition, the treatment of creating a damaged layer below the surface by femtosecond laser or H2 ion implantation may result in a damaged layer not deeper than 150 microns, limiting extraction of wafers greater than 150 microns. Despite the 150 micron limit, it has not been clear so far whether meaningful semiconductor devices can be made with such thin SiC wafers.

It is therefore desirable to provide a method for manufacturing WBG semiconductors that overcomes the limitations of thin substrates, and reduces the contribution of the substrate to the final die with minimal impact on the yield or performance parameters of the final WBG semiconductor.

Disclosure of Invention

According to an embodiment of the present application, a method for manufacturing a wide band gap semiconductor device using a substrate of a SiC wafer is disclosed. The method steps include coating a substrate with a hard mask material, performing photolithography to define a patterned opening in the hard mask material of the substrate, etching the substrate to form a patterned trench having a reentrant profile from the defined patterned opening, removing the hard mask from the substrate using a chemical process, cleaning the substrate with the patterned trench, performing epitaxy on the substrate to form a uniform monocrystalline layer over the patterned trench to create a plurality of micro-voids, performing another epitaxy on the substrate using a rapid epitaxial growth process to provide an active device epitaxial layer suitable for fabricating a SiC device, and cutting off the two epitaxial layers with the device layer at the plurality of micro-voids after fabrication of the SiC device.

According to another embodiment of the application, the hard mask material is a layer of silicon nitride and the coating step comprises chemical vapor deposition.

According to another embodiment of the application, the step of performing photolithography comprises the steps of: a photoresist is used for transferring the patterned opening pattern to the substrate.

According to yet another embodiment of the present application, the step of etching the substrate includes the steps of: reactive ion etching is performed to etch the hard mask and the patterned opening to form a reentrant trench. The reactive ion etch may be isotropic to achieve a reentrant profile after the first anisotropic etch. This ensures micro-voids after epitaxial growth.

According to a further embodiment of the application, the step of performing epitaxy comprises the steps of: a uniform monocrystalline layer is formed over the patterned trenches using Merged Epitaxial Lateral Overgrowth (MELO), thereby creating a plurality of micro-voids.

According to yet another embodiment of the present application, the step of using a MELO comprises the steps of: and (3) epitaxial growth of the rapid buffer layer to an epitaxial layer thickness of 5-20 microns.

Drawings

The foregoing and other objects, aspects and advantages of the application will be more fully understood from the following detailed description of the preferred embodiments of the application when taken in conjunction with the accompanying drawings, in which:

FIG. 1A illustrates a 4H-silicon carbide (SiC) single crystal substrate according to the application;

FIG. 1B illustrates a side view of a 4H-SiC single crystal substrate according to the application;

FIG. 2A illustrates an opening in a SiC substrate defined by a photolithographic step in accordance with the present application;

FIG. 2B illustrates a patterned SiC substrate with epitaxial side overgrown layers in accordance with the application;

fig. 3A-3F illustrate a general processing example for fabricating SiC schottky barrier diodes on a prepared substrate;

FIGS. 4A-4G illustrate a continuation of a general process for fabricating a SiC Schottky barrier diode and severing the exfoliation layers for extracting the diode in accordance with the present application;

FIG. 5A illustrates a thick layer of epitaxially grown GaN on a SiC substrate according to the present application;

FIG. 5B illustrates a thick layer of GaN coated with a hard mask material on a GaN substrate in accordance with the application;

fig. 5C illustrates a pattern for forming a exfoliation layer on a GaN substrate according to the present application;

FIG. 6A illustrates deposition of a conformal material over the formation of an exfoliation layer according to the present application;

FIG. 6B illustrates etching the conformal layer to form spacers on sidewalls of the patterned trenches in accordance with the application;

FIG. 6C illustrates isotropically etching the exposed GaN layer to form a spherical opening under the spacer on the sidewall in accordance with the present application;

FIG. 7A illustrates the GaN layer after removal of the protective hard mask and spacers on the sidewalls in accordance with the present application;

fig. 7B illustrates epitaxial growth of GaN from a substrate to form a continuous epitaxial layer in accordance with the present application;

fig. 7C illustrates the growth of a device epitaxial layer over a continuous epitaxial layer in accordance with the present application;

fig. 8A illustrates the formation of a semiconductor device on a device epitaxial layer in accordance with the present application; and

fig. 8B illustrates a semiconductor device exfoliated at an array of voids in accordance with the present application.

Detailed Description

One aspect of the application is an integrated method for partially fabricating devices on thin epitaxially grown wide band gap substrate material loosely attached to a nanopatterned SiC substrate, and extracting individual die or dies from the substrate, followed by completion of the final device method steps with the thin devices attached to the handle substrate. Another aspect of the application describes a method for patterning a surface layer on a SiC substrate that can be used as a cleavage layer for extracting the fabricated device. Yet another aspect of the application is a method for growing a thin lateral epitaxial overgrowth layer on a surface patterned layer to present a defect-free surface for growing a device epitaxial layer. Another aspect of the application is to use the nanopatterned silicon carbide wafer as a template for SiC crystal and GaN crystal growth and use a weakened nanopatterned layer to extract the entire SiC and GaN wafers from the SiC substrate without saw grooves, which is then subsequently reused.

Fig. 1A illustrates an example 4H-silicon carbide (SiC) single crystal substrate or SiC wafer 12. The 4H-SiC substrate is then patterned with an array of openings, which may have different shapes: square, rectangular, bar, etc. The openings may be made to optimize a subsequent lateral epitaxial growth for the orientation of the crystal structure, which is performed in a subsequent step in the formation of the substrate according to the application. As an example, the pattern etch may occur as a triangular or hexagonal exposure (1120) or an equivalent crystal plane of 4H-SiC. These orientations provide for the formation of rapid lateral epitaxial overgrowth to achieve subsequent high quality vertical epitaxy on the (0001) crystal plane while creating subsurface voids underneath. Furthermore, the spacing between the openings may be optimized to promote high quality epitaxial growth and to minimize the force required to peel off the substrate in a subsequent step of the fabrication process according to the present application. The spacing of the openings may be in the range of 20nm to a few microns. In an example embodiment, the 4H-SiC single crystal substrate includes a plurality of hard mask 100nm squares with 50nm gaps between the hard mask squares. Fig. 1A illustrates, not to scale.

FIG. 1B illustrates a side view of a 4H-SiC single crystal substrate having a thickness of 300-350 microns. A plurality of 100nm hard mask squares 15 with 50nm gaps over a 4H-SiC single crystal substrate 12 are shown. According to the application, the substrate is a polished 4H-SiC wafer cut at 4 degrees or 8 degrees. As shown in fig. 1A and 1B, siC wafer 12 is first coated with hard mask 15 for subsequent photolithography and etching steps. Those skilled in the art will appreciate that the choice of material for the hard mask 15 is determined by the etching process incorporated during the process. According to the application, the material used for the hard mask is a layer of silicon nitride or aluminum oxide or similar material. The deposition method may be Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD) or the like.

The next step in the present application is a photolithographic step for defining openings in the hard mask 15 and subsequently in the SiC substrate. Transfer is accomplished using photoresist and conventional optical lithography or by non-conventional lithography such as electron beam or nanoimprint lithography. The openings may be of different shapes, such as lines and spaces forming a gate structure. According to another embodiment, the opening in the hard mask may be square or rectangular. In yet another embodiment, the openings in the hard mask may be hexagonal or triangular or diamond shaped in shape positioned in a plane and patterned in such a way that the exposed vertical plane after vertical Reactive Ion Etch (RIE) etch will be of the type (1120). In any event, the size and shape of the openings in the hard mask and in the subsequent substrate will provide lateral overgrowth of the crystalline structure in the subsequent processing steps. The size of the opening defined by the photolithography step may be between 10 nanometers and 1 micrometer.

Fig. 2A illustrates an opening defined by a photolithography step. Once the opening is defined by the photolithographic process, a Reactive Ion Etch (RIE) is used to etch the hard mask. In accordance with the present application, if the hard mask is silicon nitride, a fluorine chemical RIE process can be used to etch the hard mask. Thus, compounds such as SF6, CHF3, CF4, and the like may be used to etch the hard mask. Once the hard mask is etched, an etching process is used to etch through the open areas to form trenches in the underlying SiC substrate. RIE etching processes may be used with Inductively Coupled Plasma (ICP) to form a reentrant profile having columnar walls. In another embodiment of the application, electrochemical or anodic etching may be used to complete trench formation in the underlying SiC substrate. As will be apparent to those skilled in the art, the method of electrochemical etching may be used to change the geometry of the trench opening by varying the current density, bias voltage, spacing between electrodes, power, or a number of parameters simultaneously. Thus, it is possible to define a trench that is narrower in the top and wider at the bottom, similar to the reentrant profile achieved with the RIE process. It is also possible to combine the RIE step with anodic oxidation to achieve trenches with narrower openings on the top and wider openings on the bottom. According to embodiments of the application, the depth of the trench may be between 1-3 microns.

In a next step of the application, a chemical treatment is used to remove the hard mask 15. If the hard mask material is silicon nitride, the chemical process used to remove the hard mask is fuming phosphoric acid.

After removing the hard mask from the surface of the wafer, the next step is to clean the substrate prior to epitaxial growth. The cleaned substrate with the array of patterned trenches on the surface is placed in an epitaxial growth reactor for deposition of SiC.

Referring to fig. 2B, after cleaning of patterned SiC substrate 12, an epitaxial process of crystal growth is used to form a uniform monocrystalline layer 24 over the patterned substrate. According to an embodiment of the present application, the monocrystalline layer 24 or the buffer epitaxial layer 24 is thick n+ grown between 5-20 microns thick. Epitaxial side overgrowth (ELO) or merged epitaxial side overgrowth (MELO) methods may be used by adjusting the growth conditions of the epitaxial front end to merge or form a uniform monocrystalline layer over the trenches that were previously formed and now sealed below the surface of the merged epitaxial layer. The sealed trench forms a region of intentionally formed micro-voids 26, the micro-voids 26 being used to exfoliate the top epitaxial layer from the substrate in a subsequent processing step. The substrate may then be reused multiple times. It will be apparent to those skilled in the art that by adjusting the growth conditions, a low defect layer of ELO can be formed, which then serves as a template for subsequent epitaxial growth of the die substrate and devices formed in subsequent fabrication steps.

After forming the buffer epitaxial layer 24 and the array of micro-voids 26 that act as an under-surface exfoliation or separation layer, another layer of device epitaxial SiC 28 is grown using an epitaxial active layer growth process. Buffer epitaxial layer 24 is a thick N + fast Epi 4HSiC Epi layer, according to an embodiment of the present application. Device epitaxial SiC layer 28 is typically an N-active layer Epi 4HSiC Epi growth. The thickness of the buffer epitaxial layer 24 is intended to provide a means of ohmic contact to the final device structure. The thickness of the buffer epitaxial layer 24 is about 5-20 microns. A finish polishing (light polishing) step known as flick polishing (kiss polishing) may be required to prepare the surface of the substrate with the buffer epitaxial layer 24 prior to the growth of the device epitaxial layer 28.

In accordance with an embodiment of the present application, thick buffer epitaxial layer 24 is grown using a standard CVD epitaxial growth process or a modified bulk crystal (bulk crystal) growth process such as high temperature CVD or by physical vapor deposition (PVT). The epitaxial growth of another layer suitable for the formation of SiC devices may be after the formation of device epitaxial layer 28. The thickness of device epitaxial layer 28 is determined by the breakdown voltage of the devices formed in this layer. For the example 1200V device, the thickness of the device epitaxial layer is about 10-12 microns.

The formation of device epitaxial layer 28 over buffer epitaxial layer 24 completes the preparation of substrate 12 prior to the formation of the semiconductor device, in accordance with embodiments of the present application. Any device manufactured may use standard manufacturing processes and designs.

Fig. 3A-3F illustrate a general process for fabricating SiC schottky barrier diodes on a prepared substrate. All processing steps are performed on active device epitaxial layer 28 on substrate 12. In fig. 3B, a resist is deposited and baked on the substrate film stack. Next, in fig. 3C, the resist is patterned and developed using a photolithographic mask, followed by p+ ion implantation and performing an active anneal to drive dopants from the implantation. Fig. 3D cleans the resist and deposits schottky barrier metal. In fig. 3E, photoresist patterning and development are used to pattern the deposition, exposure, and development of resist for metal contacts on the top side of the device. Fig. 3F performs a selective metal etch.

Fig. 4A-4G continue the general process described in fig. 3A-3F for fabricating SiC schottky barrier diodes. In fig. 4A, thick silicon oxide is deposited onto a substrate. In fig. 4B, resist patterning for lift-off is performed. In fig. 4C, a metal deposition is deposited to form the front end contact. Fig. 4D performs multi-die singulation by laser to separate individual dies from the substrate. Alternatively, the entire partially completed device layer may be released from the substrate. In fig. 4E, mechanical separation of the substrate from the die or the entire partially completed device layer is performed along the axis depicted by arrow 42. The entire device layer or individual die with the schottky device is separated from the substrate by first attaching it to a separation structure such as a portable electrostatic chuck or attaching it to a rigid handle using an adhesive. In fig. 4F, the entire device layer or die is separated from the substrate and is now ready for final back side metal deposition (back metal deposition) and ohmic contact formation. Since the peeled device layer or die is now attached to the rigid handle, the backside of the device layer or individual die can be cleaned and prepared for backside metal ohmic contact formation and backside metal deposition. Once the backside metallization is complete, the device is fully completed. At this point, the entire device layer or individual die is attached to a so-called blue dicing tape. With the entire device layer attached to the blue dicing tape, the dicing of individual dies may then occur. The die is now ready for testing and screening. In fig. 4G, the remaining substrate is retrieved and reused.

Referring to fig. 4D-4G, a die or dies or a substantially finished device is singulated or cut from SiC substrate 12 just before the device is finished on device epitaxial layer 28. Arrow 42 shows a patterned layer along the array of microvias 26 created under the ELO, the array of microvias 26 acting as a release or shedding layer for extracting the die from the substrate 12. Since the depth of the dicing cut is 15-80 microns, the edge release peel layer can be accomplished by using a laser or dicing saw. The singulation process for accomplishing the release of the die or collection of dies or the entire wafer may be accomplished using a vacuum chuck, an electrostatic chuck, or by using a water jet separator that impinges on the edge of the wafer in the plane of the exfoliation layer formed by the array of micro-gaps 26 beneath the ELO epitaxial layer.

The next step in the process, according to an embodiment of the present application, is to clean the top wafer or die or collection of dies using a simple chemical process. The backside metal ohmic contact is formed by metal deposition followed by annealing (such as laser annealing). This is followed by the deposition of a thicker metal that effectively becomes the back metal contact. Thicker metals may be formed by sputtering, evaporation, electroplating, or the like. Details of the fabrication process for the device are defined by the particular semiconductor device formed in the device epitaxial layer. The specific steps required to form diodes, MOSFETs and similar devices are known to those skilled in the art. The completed devices are then tested and screened based on their performance.

After the device is completed and the die or wafer is extracted from the completed substrate, the severed or peeled substrate is re-polished and retrieved for subsequent use. The severed substrate remaining after extraction of the completed semiconductor device using the exfoliation process utilizing micro-voids may be reused multiple times for subsequent device fabrication. Chemical mechanical polishing or electrochemical polishing is performed to prepare the retrieved substrate for reuse. The ability to retrieve wafers for forming multiple devices using the exfoliation method described in this embodiment reduces the cost of SiC device formation by a significant amount, in addition to improving the heat dissipation capability of the device, while improving performance by reducing the drain-to-source on-Resistance (RDSON) contribution from the bulk epitaxial thickness layer, thereby improving overall reliability.

According to another embodiment of the present application, a patterned substrate with a micro-voided exfoliation layer may be used as a seed surface for thick SiC epi/wafer growth. After growing SiC on the order of 200-400 microns, the edge may be released to separate the epitaxial wafer from the substrate. Since bulk crystal growth can be used on patterned seed surfaces, the cost of such bulk grown wafers with almost zero kerf loss (kerf loss) is significantly lower than conventional methods. Bulk growth for SiC includes physical vapor deposition (PVT) and High Temperature Chemical Vapor Deposition (HTCVD).

According to yet another embodiment of the application, the device layer may be a GaN layer grown directly on patterned silicon carbide and processed into the final device before being singulated and exfoliated from the SiC substrate. In the case where a thin GaN layer needs to be transferred to a high thermal conductivity substrate, the use of this method helps to facilitate layer transfer. By incorporating a GaN epitaxial side overgrowth process, dislocation density in the final structure can be further reduced.

According to an embodiment of the application with reference to fig. 5A, the substrate layer may be a 40-50 micron thick layer 52 of GaN (gallium nitride), the layer 52 of GaN being epitaxially grown on SiC 12, and then the layer 52 of GaN becoming the starting substrate for forming patterned exfoliation layers for the GaN device. The advantage is that as the GaN 52 layer grows thicker, the dislocation thickness on the surface is reduced and the subsequent patterning further reduces the dislocation density to the-1E 4/cm2 level.

Referring to fig. 5B, the starting substrate of GaN 52 on SiC 12 of fig. 5A is cleaned and then coated with hard mask material 15. The hard mask material 15 is silicon nitride deposited using a Chemical Vapor Deposition (CVD) process, such as Low Pressure Chemical Vapor Deposition (LPCVD), in accordance with an embodiment of the present application.

Referring to fig. 5C, a pattern for forming the exfoliation layer is made in a subsequent processing step. Patterning for forming the exfoliation layers is accomplished using photoresist and conventional optical lithography or non-conventional lithography (such as electron beam lithography) or by nanoimprint lithography. Once the pattern is transferred to the photoresist, a Reactive Ion Etch (RIE) is used to etch the hard mask 15. Fluorine chemistry (such as SF 6) may be used to etch the hard mask. The underlying substrate of GaN on SiC is then etched to form trenches 54, which may be 1000-5000 angstroms in depth. The transferred pattern may be in the form of lines, hexagons, squares or other shapes that facilitate subsequent processing of Epitaxial Lateral Overgrowth (ELO). The size of the opening may be in the range of 500-5000 angstroms. The width and depth of the trenches formed in the GaN layer may be adjusted based on the requirements of the subsequent ELO process.

Once the array of trenches 54 has been formed in the GaN substrate 52, fig. 6 illustrates the deposition of the conformal material 56 over the GaN substrate 52. The deposited conformal material 56 is an LPCVD silicon nitride layer. Other materials such as LPCVD oxide, high Temperature Oxide (HTO), low Temperature Oxide (LTO), tetraethyl silicate (TEOS) may be used for conformal material 56. An important aspect is that the conformal material coats the sidewalls of the array of trenches in a conformal manner. In addition, atomic Layer Deposition (ALD) may be used to deposit the conformal layer. ALD layers such as AlN, al2O3 may be used for the conformal layer. In an exemplary embodiment, the conformal material 56 is an LPCVD silicon nitride layer. The LPCVD silicon nitride layer has a thickness between 500-1000 angstroms and may be determined by a process designer based on the relevant process steps.

Referring to fig. 6B, conformal material 56 is etched to form spacers 58 on the sidewalls of the patterned trenches. Removal of the conformal material 56 to form the spacers may be accomplished by Reactive Ion Etching (RIE), ion milling, or similar processes. In accordance with an embodiment of the present application, a RIE using a suitable gas (such as SF6, CHF3, or the like) is used to etch the conformal material of the silicon nitride. The etching process forms silicon nitride spacers 58 in the sidewalls of the trenches, but removes the conformal material 56 that consists of the silicon nitride layer on the top surface of the substrate and the silicon nitride layer on the bottom surface of the trenches. Essentially, only the silicon nitride spacers 58 in the sidewalls remain. It should be noted that if the first hard mask layer is also comprised of silicon nitride, it is important to maintain the thickness of the first silicon nitride layer to be a sufficient thickness to withstand the spacer etch process. The completion of the spacer deposition and etching process protects the sidewalls of the array of trenches while exposing the substrate material GaN at the bottom surfaces of the trenches. In addition, the top and back surfaces (not shown) of the GaN on the SiC substrate are protected by a first hard mask layer of silicon nitride. Thus, gaN on a SiC substrate includes a patterned array of trenches with sidewalls and top and bottom surfaces protected by a layer of silicon nitride.

Referring to FIG. 6C, cl-based is used ₂ To construct GaN layer 52 or to immerse GaN layer 52 in a solution comprising a KOH solution in a bath. The concentration and temperature of KOH is suitable for etching the exposed GaN surface at the bottom of the array of trenches having sidewalls protected by spacers 58 of silicon nitride. The KOH isotropically etches the exposed GaN to form a spherical opening 60 under the spacer protected trench. Other etching techniques, such as electrochemical etching (ECE) or Photoelectrochemical Etching (PEC), may be used to etch the GaN substrate to form a ball-shaped array of openings.

According to the application, the isotropic etching of the substrate GaN on SiC forms an array of spherical openings 60 under the narrow necks formed by the trenches and the sidewalls of which are protected by the layer of silicon nitride spacers 58. The next step is to remove the protective hard mask and sidewall spacer material 58. Since the hard mask 15 and silicon nitride spacers 58 are silicon nitride, the silicon nitride on the top surface and sidewalls of the substrate is removed by immersing the substrate in hot phosphoric acid, leaving the spherical openings 60 of the trenches illustrated in fig. 7A.

The next step, according to an embodiment of the present application, is to epitaxially grow GaN from the substrate and sidewalls to a thickness sufficient to merge the growth fronts, thereby forming a continuous epitaxial layer 62 as shown in fig. 7B. The growth conditions may be adjusted to ensure epitaxial front-end incorporation. The incorporation of the epitaxial front end minimizes defect formation of epitaxial layer 62. The formation of the combined epitaxial layer 62 overgrowth provides for the formation of an array of subsurface spherical openings or voids 60 and creates a exfoliation layer.

Referring to fig. 7C, the next step after overgrowth of lateral epitaxial layer 62 is formed is to grow device epitaxial layer 64. The thickness, doping type and concentration are determined by the type of semiconductor device to be formed in device epitaxial layer 64. In some cases, multiple layers of epitaxial semiconductor may be grown for device epitaxial layer 64.

Referring to fig. 8A, the next step after forming device epitaxial layer 64 is to fabricate various semiconductor devices 66 using designs and processes well known in the art. Devices such as diodes, transistors, light emitting diodes, etc. may be formed in the device epitaxial layer 64. Other devices for RF, power management, optical, optoelectronic, etc. devices may also be formed in the device epitaxial layer 64.

After the semiconductor device is formed, the device 68 is peeled or severed from the substrate along the array of voids 60 formed beneath the substrate, as illustrated in fig. 8A and 8B. Various mechanical and thermal methods may be used for peeling or severing from the substrate. One technique is multi-die singulation using a laser to separate individual dies from a substrate. Once separated, the surface of the device is polished and metallized as needed. The surface of the remaining substrate is polished and reused to form other devices.

Once the GaN device layer is extracted, the substrate with GaN on SiC can be repolished to repeat the device process steps described above. If GaN on SiC is on the order of 40-50 microns and the array of nanovoids is on the order of 2 microns deep, then reuse of the remaining substrate can occur more than 20 iterations. Once the GaN layer has been thinned to about 10 microns, it can again be thickened to a thickness of 40-50 microns and the entire process cycle can be repeated. Thus, the underlying SiC substrate can be essentially reused again and again. To grow 40-50 microns of GaN, methods such as hydride vapor phase epitaxy can be used in a cost effective manner.

While the application has been described with reference to certain preferred embodiments or methods, it is to be understood that the application is not limited to these specific embodiments or methods. Rather, the inventors have argued that the application should be understood and interpreted in its broadest sense, as reflected by the appended claims. Accordingly, these claims should be understood to include not only the preferred methods described herein, but all such other and further changes and modifications as would be apparent to one skilled in the art.

Claims

1. A method for manufacturing a wide bandgap semiconductor device using a substrate of a SiC wafer, comprising the steps of:

coating the substrate with a hard mask material;

performing photolithography to define patterned openings in the hard mask material of the substrate;

etching the substrate to form patterned trenches from the defined patterned openings;

removing the hard mask from the substrate using a chemical process;

cleaning the substrate having the patterned trenches;

performing epitaxy on the substrate to form a uniform single crystal layer over the patterned trenches thereby creating a plurality of microvoids;

Perform another epitaxy on the substrate using a rapid epitaxial growth process to provide an active device epitaxial layer suitable for fabricating SiC devices; and

After fabrication of the SiC device, the plurality of microvoids are cut to extract the SiC device from the substrate of the SiC wafer.

2. The method for manufacturing a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 1, wherein the substrate is a reused polished 4H-SiC wafer.

3. The method for manufacturing a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 1, wherein the hard mask material is a layer of silicon nitride and the coating step includes chemical vapor deposition .

4. The method for manufacturing a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 1, wherein performing photolithography includes the step of using photoresist for transferring the patterned opening pattern to the substrate.

5. The method for fabricating a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 4, wherein the patterned openings can be triangular or hexagonal exposing (1120) crystal planes.

6. The method for manufacturing a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 5, wherein the patterned openings are between 10 nanometers and 1 micron.

7. The method for manufacturing a wide band gap semiconductor device using a substrate of a SiC wafer according to claim 1, wherein etching the substrate includes the step of: reactive ion etching to etch the hard mask material and the patterned openings, thereby forming recessed corner trenches.

8. The method for manufacturing a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 1, wherein said etching the substrate includes the steps of: reactive ion etching and electrochemical or anodic etching to A trench is formed with a narrower opening on the top and a wider opening on the bottom.

9. The method for fabricating a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 1, wherein performing epitaxy includes the step of: using merged epitaxial lateral overgrowth (MELO) in the patterned trench The uniform single crystal layer is formed thereon, thereby generating the plurality of microvoids.

10. A method for fabricating a wide bandgap semiconductor device using a substrate of a SiC wafer according to claim 9, wherein said using MELO includes the step of fast buffer layer epitaxial growth to an epitaxial layer thickness of 3-20 microns.

11. A method for fabricating a wide bandgap semiconductor device using a GaN substrate on a SiC wafer, comprising the steps of:

Coating the substrate with a hard mask material of silicon nitride;

depositing a conformal layer over the substrate and sidewalls of the patterned trench;

removing the conformal layer from the top surface of the substrate, leaving spacers of the conformal layer above the sidewalls of the patterned trenches;

etching the patterned trenches not covered by the spacers of the conformal layer to form spherical openings under the spacers;

removing the hard mask and the spacer from the substrate;

performing epitaxy on the substrate to deposit GaN onto the substrate including the patterned trenches, thereby forming an array of voids;

perform at least one other epitaxy on the substrate to deposit at least one device epitaxial layer;

forming a GaN semiconductor device in the at least one device epitaxial layer; and

The array of voids is cut to extract the GaN semiconductor device from the GaN substrate of the SiC wafer.

12. The method for manufacturing a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 1, wherein etching the substrate includes the step of etching the patterned openings to form 1000- 10,000 angstrom depth trench.

13. The method for fabricating a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein the patterned openings are in the range of 500-5000 Angstroms.

14. The method for fabricating a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein said substrate is deposited over said substrate and said sidewalls of said patterned trenches. The conformal layer includes the step of using low pressure chemical vapor deposition (LPCVD) of a layer of silicon nitride.

15. The method for fabricating a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein removing the conformal layer from a top surface of the substrate includes the step of reactive ion etching Etch to form the spacers in the patterned trenches.

16. The method for manufacturing a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein etching the patterned trenches includes the step of: immersing the substrate in a KOH solution solution to etch the patterned trenches not covered by the spacers of the conformal layer, thereby forming the spherical openings under the spacers.

17. The method for manufacturing a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein removing the hard mask and the spacer includes the step of soaking the substrate in hot phosphoric acid.

18. The method for manufacturing a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein performing epitaxy on the substrate to deposit GaN includes the step of depositing a thickness of GaN to A continuous epitaxial layer is formed over the array of voids.

19. The method for fabricating a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein performing at least another epitaxy on the substrate to deposit at least one epitaxial layer includes the step of: Diodes, transistors, RF, power management, optical devices, or optoelectronic devices are formed on the at least one epitaxial layer.

20. The method for fabricating a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 11, wherein severing the array of voids to extract the GaN device includes the step of using mechanical techniques and thermal techniques. The device is severed from the substrate on the SiC wafer.

21. The method for manufacturing a wide bandgap semiconductor device using a GaN substrate on a SiC wafer according to claim 1, further comprising the step of reusing the GaN substrate on the SiC wafer.