CN118069578B - Data processing method, data transmission system, electronic device and storage medium - Google Patents
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Abstract
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a data processing method, a data transmission system, an electronic device, and a storage medium, where the method includes: under the condition that the writing condition is met, in response to receiving a first data packet comprising a flag bit, a data field and a type field, removing data with invalid flag bits in the data field, so as to extract valid data fields and type fields with valid flag bits in the data field from the first data packet, wherein the first data packet is a type data packet obtained after bandwidth conversion of a channel type data packet, and the channel type data packet is received by a transmitting interface from an AXI interface; and generating a slope data unit according to the valid data field and the type field, and sequentially writing the generated slope data unit into a first-in first-out storage matrix comprising a plurality of first-in first-out storage structures, wherein the slope data unit comprises the valid data field and the type field. Thus, the bandwidth utilization can be effectively improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a data processing method, a data transmission system, an electronic device, and a storage medium.
Background
In the cross-device interconnection, a standard high-speed peripheral component interconnect (PERIPHERAL COMPONENT INTERFACE EXPRESS, PCIE) protocol stack is mainly used to complete end-to-end general data transmission.
In the inter-chip interconnect, a high-speed generic-die interconnect (Universal Chiplet Interconnect Express, UCIE) protocol standard is typically employed. UCIE provide a series of standard interface specifications, and use PCIE or CXL (Compute Express Link) protocols at the protocol layer to enable universal interconnection between Die (Die) of different vendors/processes.
Standard protocol stacks such as PCIE and CXL have a multi-level protocol transmission structure and a perfect functional design. In a chip-to-chip (D2D) interconnect, the chip typically has an advanced bus interface (Advanced eXtensible Interface, AXI) bus interface as the data source transmit/receive end. And carrying out multi-level encapsulation and analysis on the data through a PCIE or CXL protocol stack, and then transmitting the data through a physical layer to realize interconnection communication so as to transmit the data. However, the multi-layer structure and perfect functional design of the standard protocol often have a certain bandwidth utilization limitation problem.
Disclosure of Invention
In view of this, the present disclosure proposes a data processing method, a data transmission system, an electronic device, and a storage medium, so that the bandwidth utilization can be effectively improved.
According to a first aspect of the present disclosure, there is provided a data processing method comprising: an extracting step, under the condition that writing conditions are met, in response to receiving a first data packet comprising a flag bit, a data field and a type field, removing data with the flag bit in the data field invalid to extract a valid data field and a type field with the flag bit in the data field valid from the first data packet, wherein the first data packet is a type data packet obtained after bandwidth conversion of a channel type data packet, the channel type data packet is received from an AXI interface by a transmitting interface from a chip to a chip D2D interface, the flag bit is used for identifying whether each bit of data of the data field is valid type data, and the type field represents the type of the first data packet; and a writing step of generating a slope data unit according to the extracted effective data field and the type field, and sequentially writing the generated slope data unit into a first-in first-out storage matrix, wherein the first-in first-out storage matrix comprises a plurality of first-in first-out storage structures, and the slope data unit comprises the effective data field and the type field.
In one possible implementation, the write condition includes invalidating a full signal for all first-in-first-out memory structures in the first-in-first-out memory matrix.
In one possible implementation, after the writing step, the data processing method further includes: a reading step, in the case of meeting the reading condition, sequentially reading the respective stored slope data units from the selected first-in first-out storage structure in the first-in first-out storage matrix; a generation step, converting a plurality of slope data units read in sequence into Flit data packets; and a sending step, sending the Flit data packet.
In a possible implementation, the reading condition includes that at least 7 consecutive first-in-first-out memory structures in the first-in-first-out memory matrix are null in null signals, and accordingly, the at least 7 consecutive first-in-first-out memory structures are selected, the reading step includes: sequentially reading the slope data units stored in each first-in first-out storage structure from 7 continuous first-in first-out storage structures, wherein the generating step comprises the following steps: the 7 slope data units read sequentially are sequentially combined into 1 Flit data packet.
In one possible implementation, the reading condition includes that the number of first-in first-out memory structures in the first-in first-out memory matrix, in which the null signal is invalid, is smaller than 7, and accordingly, the first-in first-out memory structures in which the null signal is invalid are selected, and the reading step includes: sequentially reading the slope data units stored in each first-in first-out storage structure from the selected first-in first-out storage structure, wherein the generating step comprises the following steps: sequentially combining the plurality of slope data units and invalid data which are sequentially read into 1 Flit data packet.
In one possible implementation, before the extracting step, the method further includes: receiving each channel data packet transmitted by the AXI interface through the transmitting interface; converting the data packets of each channel into AXI protocol data packets of each channel; converting the AXI protocol data packets of each channel into various types of data packets with the lengths being preset values, wherein the various types of data packets comprise a data field, a type field for representing the type of the data packet and a flag bit for representing whether each bit of data of the data field is valid type data or not; and arbitrating the data packets of the various types to transmit the data packets of the various types according to the arbitrated sequence, wherein the data packets of the various types transmitted according to the arbitrated sequence are the first data packets.
In one possible implementation manner, the channel data packets include a write address AW channel data packet, a read address AR channel data packet, a write response B channel data packet, a write data W channel data packet, and a read data R channel data packet, and correspondingly, the channel AXI protocol data packets include an AW channel AXI protocol data packet, an AR channel AXI protocol data packet, a B channel AXI protocol data packet, a W channel AXI protocol data packet, and an R channel AXI protocol data packet; correspondingly, converting the AXI protocol data packets of each channel into various types of data packets with the lengths being preset values comprises the following steps: according to the AW channel AXI protocol data packet, at least one of the AR channel AXI protocol data packet and the B channel AXI protocol data packet and invalid data, an AW_AR_B data packet with the length of the preset value is generated; generating a W data packet with the length of the preset value according to the W channel AXI protocol data packet; and generating an R data packet with the length of the preset value according to the R channel AXI protocol data packet.
In one possible implementation, after the sending step, the data processing method further includes: receiving the Flit data packet; analyzing the received Flit data packet, and carrying out parallel classification processing on a plurality of analyzed effective slot data units according to the analyzed type field; and according to the sequence of converting the plurality of slope data units into Flit data packets in the generating step, writing the classified effective slope data units of various types into a corresponding type of first-in first-out storage matrix.
In one possible implementation manner, after writing the classified valid slope data units of each type into the corresponding type of first-in-first-out memory matrix, the data processing method further includes: reading a predetermined number of effective slope data units from each type of first-in first-out memory matrix; checking whether the read effective slope data unit of each type is complete or not; if the type of valid slope data unit is complete, the type of valid slope data unit is restored to the type of AXI protocol data packet according to the AXI format; and transmitting the AXI protocol data packets of each type to the AXI interface through a receiving interface of the D2D interface.
According to a second aspect of the present disclosure, there is provided a data transmission system comprising: a sending side buffer control module, configured to: under the condition that writing conditions are met, in response to receiving a first data packet comprising a flag bit, a data field and a type field, removing data with the flag bit in the data field invalid to extract a valid data field and a type field with the flag bit in the data field valid from the first data packet, wherein the first data packet is a type data packet obtained after bandwidth conversion of a channel type data packet, the channel type data packet is received from an AXI interface by a chip-to-chip D2D interface, the flag bit is used for identifying whether each bit of data in the data field is valid type data, and the type field represents the type of the first data packet; generating a slope data unit according to the extracted effective data field and the type field, and sequentially writing the generated slope data unit into a first-in first-out storage matrix, wherein the first-in first-out storage matrix comprises a plurality of first-in first-out storage structures, and the slope data unit comprises the effective data field and the type field.
In one possible implementation, the write condition includes invalidating a full signal for all first-in-first-out memory structures in the first-in-first-out memory matrix.
In one possible implementation manner, the sending-side buffer control module is further configured to: sequentially reading the respective stored slope data units from the selected first-in first-out memory structure in the first-in first-out memory matrix under the condition that the reading condition is met; converting the plurality of slope data units read sequentially into Flit data packets; and sending the Flit data packet.
In one possible implementation manner, the reading condition includes that at least 7 consecutive first-in first-out memory structures in the first-in first-out memory matrix are null in null signals, and accordingly, the at least 7 consecutive first-in first-out memory structures are selected, and the sending-side buffer control module is configured to: sequentially reading the slope data units stored in each first-in first-out storage structure from 7 continuous first-in first-out storage structures, and sequentially combining the 7 sequentially read slope data units into 1 Flit data packet.
In one possible implementation manner, the reading condition includes that the number of first-in first-out storage structures with invalid null signals in the first-in first-out storage matrix is smaller than 7, and accordingly, the first-in first-out storage structures with invalid null signals are selected, and the sending side buffer control module is configured to: sequentially reading the slope data units stored in each first-in first-out storage structure from the selected first-in first-out storage structure, and sequentially combining a plurality of sequentially read slope data units and invalid data into 1 Flit data packet.
In one possible implementation, the data transmission system further includes: the sending interface is used for receiving each channel data packet transmitted by the AXI interface; a format generator, configured to convert the data packets of each channel into AXI protocol data packets of each channel, and convert the AXI protocol data packets of each channel into various types of data packets with lengths each being a predetermined value, where the various types of data packets include a data field, a type field that indicates a type of the data packet, and a flag bit that indicates whether each bit of data of the data field is valid type data; and the arbiter is used for arbitrating the data packets of the various types to transmit the data packets of the various types according to the arbitrated sequence, wherein the data packets of the various types transmitted according to the arbitrated sequence are the first data packets.
In one possible implementation manner, the channel data packets include a write address AW channel data packet, a read address AR channel data packet, a write response B channel data packet, a write data W channel data packet, and a read data R channel data packet, and correspondingly, the channel AXI protocol data packets include an AW channel AXI protocol data packet, an AR channel AXI protocol data packet, a B channel AXI protocol data packet, a W channel AXI protocol data packet, and an R channel AXI protocol data packet; accordingly, the format generator is configured to: according to the AW channel AXI protocol data packet, at least one of the AR channel AXI protocol data packet and the B channel AXI protocol data packet and invalid data, an AW_AR_B data packet with the length of the preset value is generated; generating a W data packet with the length of the preset value according to the W channel AXI protocol data packet; and generating an R data packet with the length of the preset value according to the R channel AXI protocol data packet.
In one possible implementation, the data transmission system further includes: the analysis module is used for receiving the Flit data packet, analyzing the received Flit data packet, and carrying out parallel classification processing on a plurality of analyzed effective slot data units according to the analyzed type field; and the receiving side buffer control module is used for writing the classified effective slope data units into the corresponding type first-in first-out storage matrix according to the sequence of converting the plurality of slope data units into the Flit data packets by the sending side buffer control module.
In one possible implementation, the data transmission system further includes: a type generator for reading a predetermined number of valid slope data units from each type of first-in first-out memory matrix, and checking whether the valid slope data units of the type are complete for each type of valid slope data units read; if the type of valid slope data unit is complete, the type of valid slope data unit is restored to the type of AXI protocol data packet according to the AXI format; and the receiving interface of the D2D interface is used for transmitting the AXI protocol data packets of all types to the AXI interface.
According to a third aspect of the present disclosure, there is provided an electronic device comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the data processing method described above when executing the instructions stored by the memory.
According to a fourth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer program instructions, wherein the computer program instructions, when executed by a processor, implement the above-described data processing method.
According to a fifth aspect of the present disclosure, there is provided a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above-described data processing method.
The data processing method and the data transmission system provided by the present disclosure, for a type data packet received by performing bandwidth conversion on a channel type data packet received from an AXI interface via a transmission interface of a D2D interface, write only valid data fields and type fields in the type data packet into a FIFO matrix, and not write invalid data (i.e. "bubble") into the FIFO matrix, and therefore, although the data packet input into the FIFO matrix is bubble-free, the data written into the FIFO matrix is bubble-free, whereby not only waste of the FIFO matrix can be avoided, but also bandwidth utilization can be improved.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a block diagram of a data transmission system of an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of an AXI packet format.
Fig. 3 is a schematic diagram of a slope data unit format.
FIG. 4 is a flow chart of a data processing method of an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a fixed format packet.
Fig. 6 is a schematic diagram of the FIFO matrix read-write control principle.
Fig. 7 is a flow chart of a data processing method of an embodiment of the present disclosure.
Fig. 8 is a flow chart of a data processing method of an embodiment of the present disclosure.
Fig. 9 is a flow chart of a data processing method of an embodiment of the present disclosure.
Fig. 10 is a schematic diagram of Flit unpacker unpacking and sorting.
Fig. 11 is a schematic diagram of the data format of a type FIFO matrix buffer.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
Fig. 1 is a block diagram of a data transmission system of an embodiment of the present disclosure. As shown in fig. 1, the data transmission system may be applied to an application scenario of an inter-chip interconnect, and the data transmission system may include a transmit channel and a receive channel. The transmit channel is used to convert the five types of channel data from the AXI interface into data between interface protocols and to transmit the converted data to the receive channel by serial data transmission by means of a physical layer (PHY layer) as an underlying transmission medium. The receiving channel is used for receiving the data sent by the sending channel through serial data transmission by means of the PHY layer, carrying out data inverse transformation among interface protocols on the received data, and then transmitting the data after inverse transformation to the AXI interface. For example, the data transmission system may be employed to implement interconnect communication between chip a and chip B. The chip A (corresponding to a transmitting interface) receives channel data from the AXI interface, performs data conversion between interface protocols on the channel data through the transmitting channel, transmits the converted data to the receiving channel through the PHY layer, performs data inverse transformation between the interface protocols on the data through the receiving channel, and transmits the inversely transformed data to the chip B (corresponding to the receiving interface), and the chip B transmits the data to the AXI interface.
In one implementation, the AXI interfaces may include an AXI4 interface or an AXI5 interface, which may include 5 different channels as follows: a read address channel (READ ADDRESS CHANNEL, AR), a write address channel (WRITE ADDRESS CHANNEL, AW), a read data channel (READ DATA CHANNEL, R), a write data channel (WRITE DATA CHANNEL, W), a write response channel (Write response channel, B). Each channel is a separate AXI handshake protocol. Accordingly, the channel type packets transmitted by the AXI interface may include an AW channel packet, an AR channel packet, a B channel packet, a W channel packet, and an R channel packet. Chip a may receive these channel type data packets from the AXI interface via a handshake mechanism and chip B may send corresponding data packets to the AXI interface via the handshake mechanism.
As shown in fig. 1, the transmission channel may include a Flit first-in first-Out (FRIST IN FRIST Out, FIF 0) control module, and the input data packet of the Flit FIFO control module is a data packet packed by an aw_ar_b_hybrid packer in the format generator, a data packet packed by a W packer in the format generator, and a data packet packed by an R packer in the format generator, where the data packets packed by the three packers are all 9 slots (slots) of data, each slot transmits 8 bytes of data, and thus the lengths of the data packets packed by the three packers are all 72 bytes, i.e., the data lengths of the data packets are the same. The aw_ar_b_hybrid packer randomly combines three data packets, namely an AW channel AXI protocol data packet converted from an AW channel data packet (aw_pkt) of the aw_fifo buffer, an AR channel AXI protocol data packet converted from an AR channel data packet (ar_pkt) of the ar_fifo buffer, and a B channel AXI protocol data packet converted from a B channel data packet (b_pkt) of the b_fifo buffer to form a packed data packet; the W packer packs the independent data packet, namely the W channel AXI protocol data packet converted by the W channel data packet (W_PKT) of the W_FIFO buffer; the R packer packs the R channel AXI protocol data packet converted by the R channel data packet (R_PKT) of the R_FIFO buffer.
As shown in fig. 1 and 2, the AW channel AXI protocol packet and the AR channel AXI protocol packet are both 2-slot data, and thus the length of the AW channel AXI protocol packet and the AR channel AXI protocol packet is 16 Byte. The B-channel AXI protocol packet is 1 slot data, so the length of the B-channel AXI protocol packet is 8 Byte. The W-channel AXI protocol packet is 10-slot data, so the length of the W-channel AXI protocol packet is 80 Byte. The R-channel AXI protocol packet is 9-slot data, so the length of the R-channel AXI protocol packet is 72 Byte.
That is, the aw_ar_b_hybrid packer, the W packer, and the R packer respectively pack AXI protocol packets with different data lengths, and the data lengths of the three packets are the same (8 slope units), where the aw_ar_b_hybrid packer randomly mixes the AW channel AXI protocol packets, the AR channel AXI protocol packets, and the B channel AXI protocol packets, which are packets with shorter lengths, and the W packer and the R packer respectively pack the actually received W channel AXI protocol packets and R channel AXI protocol packets. It should be noted that the 1 st slot unit of the W-channel AXI protocol packet is only useful for WL information, and is not individually packed into 1 slot. But the WL information will be packed into 1 slot (W8 or W9) along with the last 1 slot unit, the WL information being carried by the W8/W9 type field. Therefore, the bandwidth can be pulled to the maximum bandwidth meeting the design requirement, and a fixed-length fixed-Format data packet (Fix Format data packet) is formed. For example, the data length is extended by padding null data (e.g., "0", also called invalid data) in a packet whose data length does not reach the fixed length, and the padded "0" is the invalid data, i.e., a bubble. The AXI packet format shown in fig. 2 is a format specified by the AXI protocol, and will not be described herein.
For data type equalization, the present embodiment converts each data packet into a fixed-format data packet with a fixed length. Meanwhile, considering that the lengths of the three types of packets aw_pkt, ar_pkt, and b_pkt are short, if the three types of packets are respectively packed into fixed format packets, the three packets having the short lengths each need to consume one clock period, and thus transmission efficiency may be reduced. For this, the aw_ar_b_hybrid wrapper performs any combination of aw_pkt, ar_pkt and b_pkt, and a specific combination manner may be seen in fig. 5. If the mixed data length has not yet reached the fixed length, null data may be added to extend the data length to the fixed length. Therefore, compared with the method that the three types of data packets are respectively packed into the fixed format data packets and are subjected to subsequent processing, the method and the device for processing the data packets in the mixed mode can improve data transmission efficiency.
In addition, if only one type of data packet of aw_pkt, ar_pkt, and b_pkt is given priority in polling arbitration, it is possible to convert the one type of data packet into a fixed format data packet and transmit it without waiting for the other type of data packet, and to improve data transmission efficiency as compared with a manner of waiting for the other type of data packet all the time, considering that there may not be as much valid data to be transmitted in actual transmission.
When the data packet packed by the aw_ar_b_hybrid packer, the data packet packed by the W packer, and the data packet packed by the R packer are input to the FIFO Matrix, if the writing condition is met, the Flit FIFO control module reassembles the fixed format data packets according to the custom data unit slope (69 bits) of the embodiment shown in fig. 3, and writes the fixed format data packets into the FIFO Matrix (Matrix) in a bubble-free sequential cycle by adopting a sliding window writing mode with variable length. Wherein the Flit FIFO control module is used as the sender-side buffer control module of the present disclosure.
The FIFO matrix is actually a combination of FIFOs. A single FIFO is used as granularity to form parallel arrangement combination, serial numbers are carried out according to sequence, and FIFO read/write signals are enabled by circulating movement in a sliding window mode with variable length, so that a buffer storage component capable of flexibly supporting variable-length effective data input and effective data output is formed. In one possible implementation, the FIFO matrix is composed of 9 FIFO combinations for implementing buffering of active slope elements of fixed format data packets. The data bit width of each FIFO is 69bits, for storing 1 complete slope data unit, namely: "Data (slot unit) +type (Type), see fig. 3 for a specific format, the slot Data unit includes a 64bits Data field and a 5bits Type field. The data field is valid data extracted from a fixed format data packet, and the type field is internally generated according to the data field.
Considering that a fixed-length fixed-format packet is a type packet obtained after bandwidth conversion of 5 channel type packets aw_pkt, w_pkt, ar_pkt, r_pkt, b_pkt, as described above, for a packet whose data length does not reach the fixed length, null data is filled into the packet to expand its data length to the fixed length, and thus bubbles are introduced into a channel type packet whose data length does not reach the fixed length when the bandwidth conversion is performed. If these bubbles are not removed, they are buffered and transferred, which results in a waste of buffering and a reduction in bandwidth utilization.
For this purpose, the Flit FIFO control module performs steps S401 and S402 shown in fig. 4.
In step S401, in response to receiving a first data packet including a flag bit (STRB), a data field (e.g. WO-W8), and a TYPE field (TYPE), the Flit FIFO control module rejects data in which the flag bit in the data field is invalid, so as to extract, from the first data packet, a valid data field and a TYPE field in which the flag bit in the data field is valid, where the first data packet is a TYPE data packet obtained by performing bandwidth conversion on a channel TYPE data packet, where the channel TYPE data packet is received by a transmission interface of a D2D interface from an AXI interface, and the flag bit is used to identify whether each bit of data in the data field is valid TYPE data, and the TYPE field indicates a TYPE of the first data packet. The flag bit is generated in the module, the flag bit is STRB [8:0], each bit represents whether the corresponding data unit is valid type data, if valid, the flag bit is set to be 1, otherwise, the flag bit is set to be 0.
In this embodiment, the first data packet is a fixed format data packet and a corresponding flag bit as described above. Wherein the first data packet includes 10 types of data packets shown in fig. 5, as shown in fig. 5, the fixed format data packet may include: a W-type fixed-format data packet, an R-type fixed-format data packet, a B-type fixed-format data packet, an AW-type fixed-format data packet, an AR-type fixed-format data packet, AWAR-type fixed-format data packet, an AWB-type fixed-format data packet, an ARB-type fixed-format data packet, and a AWARB-type fixed-format data packet, wherein blast represents "null", the data is invalid data, and the corresponding flag bit STRB is 0. The fixed format data packets of the type B, the type AW, the type AR, the type AWAR, the type AWB, the type ARB and the type AWARB are fixed format data packets obtained by any combination of the AW_AR_B_hybrid packer to the AW_PKT, the AR_PKT and the B_PKT.
Since the AXI protocol specifies whether it is required to identify the last write data, the W-type fixed-format packet of this embodiment includes a WL packet and an L packet, which are different in that the WL packet does not have a type word for identifying W9 as the last write data, and the L packet includes a type word of W9. This indicates that the WL packet is any write data before the last write data, and the L packet is the last write data.
Taking WL data packet as an example, 5bits in the type field represent that the type of the data packet is w_wo, and each STRB of W0 to W8 is "1", which indicates that W0 to W8 are valid data. Taking an L-class data packet as an example, the type of the data packet is represented by 5bits in a type field, wherein the type of the data packet is W_ wW, and STRBs of each of W0-W8 are 1, which indicates that W0-W8 are valid data. Taking an R data packet as an example, the type of the data packet is represented by 5bits in a type field, wherein the type of the data packet is R, and STRBs of R0-R8 are all 1, which indicates that R0-R8 are all effective data. Taking a B data packet as an example, 5bits in the type field of the B data packet represent that the type of the data packet is B, the STRB of B is "1", which indicates that B is valid data, and the STRBs of the remaining bits are "0", which indicates that all are invalid data. And so on, it should be understood that the meaning of the other packets in fig. 5.
As shown in fig. 5, the fixed format data packets of the type B, AW, AR, AWAR, AWB, ARB, AWARB are all provided with bubbles, so that the Flit FIFO control module needs to remove the bubbles in the first data packet when receiving the first data packet, and thus, the first data packet is the valid data and type. For example, the B-TYPE fixed format packet is left after the rejection processing to be B-data and TYPE.
In step S402, the Flit FIFO control module generates a slice data unit according to the extracted valid data field and type field, and sequentially writes the generated slice data unit into a first FIFO memory matrix, where the first FIFO memory matrix includes a plurality of FIFO memory structures, and the slice data unit includes the valid data field and the type field.
In this embodiment, the Flit FIFO control module combines the valid data and the type into a slice data unit according to the format shown in fig. 3, so that the slice data unit does not carry bubbles, and the slice without bubbles can be sequentially written into the FIFO matrix. As shown in fig. 6 and table 1 below, the slope data unit and STRB (acting as write enable) are cyclically shifted to implement a sliding window operation according to the identified Type. The cyclic shift value depends on the start value of the sliding window, and 9 pairs of slope data units/STRB after the sliding window shift are allocated to wdata/wr_en input ports of 9 FIFOs, and the STRB respectively controls whether the FIFO writing operation is effective or not. Wherein the start point of the sliding window is obtained from the current write start pointer pointing position (wr_start_ptr). The sliding window effective length is obtained by adding the field STRB effective bit lengths. Next write start pointer: the current start point of the sliding window and the effective length of the sliding window are added, and then N (the total number of FIFOs) is modulo, to generate the next write start pointer position.
Write operation of the FIFO matrix of Table 1
For example, if one data is written in each clock cycle, as shown in fig. 6, the 0 th pen continuously writes AWARB valid data from FIFO 0, the pointer becomes 5 for writing data in order, the 1 st pen continuously writes 9 valid data of W type from FIFO 5, the pointer becomes 5 for writing data in order, the 2 nd pen continuously writes 1 valid data of DLLP type from FIFO 5, the pointer becomes 6 for writing data in order, and the 3 rd pen continuously writes 9 valid data of R type from FIFO 6. It can be seen that all valid data is written.
Therefore, the Flit FIFO control module adopts a sliding window writing mode with variable length, and bubble-free sequence circularly writes slope data units into the FIFO matrix. Wherein a FIFO matrix may be used as a first-in-first-out memory matrix of the present disclosure.
According to the present embodiment, for a type data packet received by bandwidth-converting a channel type data packet received from an AXI interface via a transmission interface of a D2D interface, only valid data fields and type fields in the type data packet are written in the FIFO matrix, and bubbles are not written in the FIFO matrix, so that although a data packet input to the FIFO matrix is bubble-free, data written in the FIFO matrix is bubble-free, whereby not only waste of the FIFO matrix can be avoided, but also bandwidth utilization can be improved.
In addition, according to the embodiment, compared with the protocol packet of the protocol packet such as the PCIE protocol packet in the prior art, the custom slope data unit has a complex package and an insufficient utilization rate of the valid data of the packet, the embodiment can simplify the package of the packet and can improve the utilization rate of the valid data in the packet.
In one possible implementation, the write condition may include invalidating the full signal for all first-in-first-out memory structures in the first-in-first-out memory matrix.
Here, the full signal (afull) is effectively indicated that the amount of data buffered in the corresponding FIFO memory structure is greater than a preset full threshold, for example, when the amount of data contained in the FIFO is greater than or equal to the preset full threshold, the full signal is effective (for example, afull is 1), the full signal is transmitted to the upstream module, and the upstream module is notified to stop sending data, so as to prevent the FIFO from overflowing. And the data quantity cached in the first-in first-out storage structure corresponding to the full signal invalidation indication is smaller than a preset full threshold value, and the data can be continuously written into the first-in first-out storage structure.
In this embodiment, if all FIFO memory structures in the FIFO matrix are not to be full, the writing condition is met, otherwise, the writing condition is not met. Thus, writing to the FIFO matrix is controlled according to such writing conditions, and it is possible to ensure that the maximum input bit width data is accommodated.
In one possible implementation, as shown in fig. 7, the data processing method further includes steps S701, S702, and S703.
In step S701, if the reading condition is met, the respective stored slope data units are sequentially read from the selected fifo memory structure in the first fifo memory matrix.
In step S702, a plurality of slope data units read sequentially are converted into Flit data packets.
In step S703, the Flit packet is transmitted.
In one possible implementation, the reading condition includes that at least 7 consecutive first-in-first-out memory structures in the first-in-first-out memory matrix are null, and accordingly, the at least 7 consecutive first-in-first-out memory structures are selected, step S701 includes: sequentially reading the slope data units stored in each fifo memory structure from the 7 consecutive fifo memory structures, step S702 includes: the 7 slope data units read sequentially are sequentially combined into 1 Flit data packet.
In this embodiment, as shown in fig. 6 and table 2 below, the Flit FIFO control module performs a cyclic shift operation on the STRB (serving as a read enable) according to the current read start pointer position (rd_start_ptr), and in the case that the read condition is satisfied, the rd_en input port of the selected FIFO is set to be effective, the corresponding rdata output port performs data output, and no selected FIFO or an empty FIFO does not perform a read data operation. The read valid rdata may be formed into a complete Flit packet in Flit format and output the Flit packet. Wherein the start point of the sliding window is obtained from the current write start pointer pointing position (wr_start_ptr). The sliding window effective length is obtained by adding the set STRB field effective bit length. Next read start pointer: the same way as the write start pointer is generated, i.e. the current start point of the sliding window and the effective length of the sliding window are added, and then N (the total number of FIFOs) is modulo, to generate the next read start pointer position.
TABLE 2 FIFO read operation of matrix
Reading one data per clock cycle, as shown in fig. 6, the 0 th pen continuously reads 7 valid data from FIFO 0, and for data transmission, the pointer becomes 7; the 1 st pen continuously reads 7 effective data from the FIFO 7, and the pointer becomes 5 for data transmission order preservation; the 2 nd stroke reads 7 valid data consecutively from FIFO 5, and so on. It can be seen that the read data are valid data.
Therefore, the Flit FIFO control module reads the slope data units cached in the FIFO matrix in a bubble-free sequence, so that the effective data utilization rate of the data packet can be improved.
In one possible implementation manner, the reading condition includes that the number of first-in first-out storage structures where the null signal is invalid in the first-in first-out storage matrix is smaller than 7, and accordingly, the first-in first-out storage structures where the null signal is invalid are selected, and step S701 includes: sequentially reading the slope data units stored in each fifo memory structure from the selected fifo memory structure, step S702 includes: sequentially combining the plurality of slope data units and invalid data which are sequentially read into 1 Flit data packet.
In this embodiment, if the number of data read in one clock cycle is less than 7, the data can be waited until 7 data are obtained for data transmission, so that the transmitted data are all valid data, and the utilization rate of the valid data of the data packet can be improved. Of course, data having less than 7 valid data may be directly transmitted without waiting, and thus, although an empty packet is mixed, it is not necessary to wait for other valid data all the time, and valid data can be transmitted to the opposite end in time. Obviously, the bandwidth waste is automatically introduced by the actual application scene under the condition of enough design bandwidth, and does not belong to the bandwidth waste caused by unreasonable design. And thus data transmission efficiency can be improved. It should be appreciated that these empty packets will be rejected during the parsing process described below.
In one possible implementation, as shown in fig. 8, the data processing method may further include steps S801, S802, S803, and S804.
In step S801, each channel packet transmitted by the AXI interface is received via the transmission interface.
In this embodiment, as shown in fig. 1, the transmission channel of the data transmission system may further include a transmission interface. The transmit interface acts as a slave (slave) end to the interface of the HBF bus AXI and acts as a transmit end to the D2D interconnect. The sending interface and the AXI interface can obtain each channel (channel) data packet of AXI4 through a handshake mechanism, wherein each channel data packet can comprise an AW channel data packet, an AR channel data packet, a B channel data packet, a W channel data packet and an R channel data packet. The transmit interface may buffer each channel packet in a FIFO of the corresponding type, respectively. For example, the transmitting interface buffers AW channel packets, AR channel packets, B channel packets, W channel packets, and R channel packets in aw_fifo, ar_fifo, b_fifo, w_fifo, r_fifo, respectively. Main configuration parameters of each AXI channel type FIFO: the FIFO data bit width is equal to the AXI protocol data packet format bit width. For example, the AW_FIFO, AR_FIFO, B_FIFO, W_FIFO, R_FIFO are 16Byte, 8Byte, 80Byte, 72Byte, respectively.
In step S802, the channel data packet is converted into an AXI protocol data packet of each channel.
In step S803, the AXI protocol data packets of each channel are converted into various types of data packets with a predetermined length, where the various types of data packets include a data field, a type field indicating a type of the data packet, and a flag bit indicating whether each bit of data of the data field is valid type data.
In this embodiment, as shown in fig. 1, the transmitting channel of the data transmission system may further include a format generator, where the format generator converts the AW channel data packet, the AR channel data packet, the B channel data packet, the W channel data packet, and the R channel data packet into an AW channel AXI protocol data packet, an AR channel AXI protocol data packet, a B channel AXI protocol data packet, a W channel AXI protocol data packet, and an R channel AXI protocol data packet, respectively.
Then, the aw_ar_b_hybrid packetizer of the format generator performs any combination on the AW channel AXI protocol packet, the AR channel AXI protocol packet, and the B channel AXI protocol packet according to the foregoing packetizing manner to convert them into aw_ar_b packets of a fixed length, and the W packetizer and the R packetizer of the format generator respectively packetize the W channel AXI protocol packet and the R channel AXI protocol packet according to the foregoing packetizing manner to convert them into W packets and R packets of a fixed length, respectively. Wherein the fixed length is the predetermined value, such as 72Byte. The formats of the fixed length aw_ar_b packet, W packet and R packet can be described with reference to fig. 5 and the foregoing description.
In step S804, the packets of the types are arbitrated to transmit the packets of the types in the arbitrated order, wherein the packets of the types transmitted in the arbitrated order are the first packets.
In this embodiment, as shown in fig. 1, the transmission channel of the data transmission system may further include an arbiter, where the arbiter may perform arbitration selection of the aw_ar_b packet, the W packet, and the R packet in a polling priority manner, so as to ensure balanced transmission of various types of packets.
In one possible implementation, as shown in fig. 9, the data processing method may further include steps S901, S902, S903, S904, S905, S906.
In step S901, the Flit packet is received.
In step S902, the received Flit packet is parsed, and the parsed valid slop data units are classified in parallel according to the parsed type field.
In this embodiment, as shown in fig. 1, the receiving channel of the data transmission system may include a Flit depacketizer, and the Flit depacketizer receives, via the PHY layer, flit data packets sent by the sending channel, and as shown in fig. 10, the Flit depacketizer may perform depacketizing and type data classification on the received Flit data packets. The Flit unpacker judges specific types of each slot effective data unit (slots 0-6) according to types [6:0] of Flit data packets, and restores and generates 7 slot data units according to a format shown in fig. 3. Furthermore, the Flit unpacker can perform parallel Type classification processing on 7 slope data units generated by analysis, so that the maximum received data rate can be matched.
In step S903, the plurality of slope data units are converted into Flit data packets in the order of step S702, and the classified valid slope data units of each type are written into the corresponding type of fifo memory matrix.
In this embodiment, as shown in fig. 1, the receiving channel of the data transmission system may further include a type FIFO control module, which, similar to the FIFO control module of the transmitting channel, also adopts a sliding window writing mode with a variable length, and buffers the bubble-free sequence of the various types of slope data units in the corresponding type FIFO matrix according to the format shown in fig. 11. That is, the type FIFO control module sequentially registers the same type of slope data units to the corresponding type FIFO matrix (data_out [6:0] [68:0 ]) in the original order in the Flit data packets, respectively. The type FIFO matrix is also referred to as a type data register set.
As shown in fig. 1, the type FIFO matrix may include an AW FIFO matrix, a W FIFO matrix, an AR FIFO matrix, an R FIFO matrix, a B FIFO matrix. The type FIFO control module may continuously register a slice data unit of type AW, a slice data unit of W, a slice data unit of AR, a slice data unit of R, a slice data unit of B to an AW FIFO matrix, a W FIFO matrix, an AR FIFO matrix, an R FIFO matrix, a B FIFO matrix, respectively, in accordance with an order set in Flit packets. The FIFO matrices of each type can operate independently of each other. Since the type FIFO matrices are not necessarily registered full, all the type FIFO matrices for which there is no valid type data are defaulted to empty (blast), and the corresponding "valid data flag" STRB is 0.
The format of the input data in each type of FIFO matrix is data [69 XN-1:0 ]. Wherein n=9 in the W/R FIFO matrix and n=7 in the b/AW/AR FIFO matrix. STRB [ N-1:0] is a valid data flag bit register set. The slice data unit in the STRB indicates whether or not the FIFO is valid type data. The input data format corresponding to each type of FIFO matrix data can be seen in fig. 11.
In step S904, a predetermined number of active slope data units are read from each type of first-in first-out memory matrix.
In this embodiment, as shown in fig. 1, for each type of FIFO matrix, the type FIFO control module may read a predetermined number of active slope data units by using a fixed-length sliding window reading manner, so as to restore the active slope data units to an AXI protocol data packet.
In step S905, for each type of valid slope data unit read, checking whether the type of valid slope data unit is complete; if the type of active slope data unit is complete, the type of active slope data unit is restored to the type of AXI protocol data packet according to the AXI format.
In this embodiment, as shown in fig. 1, the receiving channel of the data transmission system may further include a type generator, where the type generator checks whether the type field of each type of valid slot data unit is complete, and reassembles and restores the type of valid slot data unit into an AXI protocol data packet of the type according to an AXI format.
In step S906, the AXI protocol data packets of each type are transmitted to the AXI interface via the receiving interface of the D2D interface.
In this embodiment, as shown in fig. 1, the receiving channel of the data transmission system may further include a receiving Interface (RX Interface), where the receiving Interface is responsible for receiving and buffering all types of complete data packets output by the type generator, and transmitting the all types of data packets to the HBF bus through a handshake mechanism according to an AXI Interface protocol format.
The receive interface acts as the master (master) end of the docking HBF bus AXI interface and as the receive end of the D2D interconnect. The receiving interface and the AXI interface can transmit the data packets of each channel of AXI to the AXI interface through a handshake mechanism. Similar to the transmitting interface, the receiving interface may buffer each type of complete packet in a corresponding type of FIFO, respectively. For example, the receiving interface buffers aw_pkt, ar_pkt, b_pkt, w_pkt, r_pkt in aw_fifo, ar_fifo, b_fifo, w_fifo, r_fifo, respectively.
It can be seen that the sending channel of the data transmission system may include a sending interface of the D2D interface, a format generator, an arbiter, and a Flit FIFO control module, where the sending interface receives 5 channel data packets from the AXI interface through a handshake mechanism, and performs a first level buffering on the data packets, the format generator converts each buffered channel data packet into each channel AXI protocol data packet, and then processes each channel AXI protocol data packet into a fixed format data packet, the Flit FIFO control module applies a variable length sliding window write mode to the fixed format data packets, writes the fixed format data packets into the FIFO matrix in a bubble-free sequence, reads the slope data units buffered in the FIFO matrix in a bubble-free sequence, and sends the slope data units to the receiving channel through the PHY layer.
The receiving channel of the data transmission system may include a receiving interface of the D2D interface, a type generator, a type FIFO control module, and a Flit unpacker, where the Flit unpacker receives the above-mentioned slice data units sent by the sending channel via the PHY layer, parses the slice data units and classifies the slice data units according to a type field, the type FIFO control module uses a variable-length sliding window write mode to buffer each type of slice data unit in a corresponding type FIFO matrix in a bubble-free sequence, reads a specific number of slice data units from each type FIFO matrix in a sliding window mode, the type generator restores each type of slice data units to an AXI protocol data packet of the type, restores each type of AXI protocol data packet to each type of channel data packet, and the receiving interface sends each type of channel data packet to the AXI interface through a handshake mechanism.
Therefore, compared with the prior art that a multi-level protocol transmission structure and a perfect function and control mechanism design are required, the data transmission system of the embodiment eliminates some unnecessary additional functions, such as a power management function; some control mechanisms, such as a credit and other flow control designs, are simplified, so that protocol transmission hierarchical structures can be reduced, and control processes are simplified, thereby improving the effective utilization rate of design bandwidth and reducing data transmission delay.
Compared with the prior art, the data processing method of the embodiment self-defines the slope data unit and adopts the self-defined protocol packet format, thereby improving the utilization rate of the effective data of the data packet. In addition, the FIFO matrix is adopted to realize the data bit width matching and bubble-free caching among protocols, so that the maximum design bandwidth utilization rate can be ensured. In this way, D2D interconnect communication between chips can be achieved at a greater effective data rate.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform the data processing method described in the foregoing method embodiments, and specific implementation of the method may refer to the description of the foregoing method embodiments, which is not repeated herein for brevity.
The disclosed embodiments also provide a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the above-described data processing method. The computer readable storage medium may be a volatile or nonvolatile computer readable storage medium.
The embodiment of the disclosure also provides an electronic device, which comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the data processing method described above when executing the instructions stored by the memory.
Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when run in a processor of an electronic device, performs the above-described data processing method.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvements in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (20)
1. A method of data processing, comprising:
An extracting step, under the condition that writing conditions are met, in response to receiving a first data packet comprising a flag bit, a data field and a type field, removing data with the flag bit in the data field invalid, so as to extract a valid data field and a type field with the flag bit in the data field valid from the first data packet, wherein the first data packet is a fixed-length type data packet obtained after bandwidth conversion of a channel type data packet, and when bandwidth conversion is carried out on the channel type data packet with the data length not reaching the fixed length, the first data packet is obtained by filling invalid data into the channel type data packet with the data length not reaching the fixed length, the channel type data packet is received from an AXI interface by a transmitting interface of a chip-to-chip D2D interface, and the flag bit is used for identifying whether each bit data of the data field is valid type data, and the type field indicates the type of the first data packet;
And a writing step of generating a slope data unit according to the extracted effective data field and the type field, and sequentially writing the generated slope data unit into a first-in first-out storage matrix, wherein the first-in first-out storage matrix comprises a plurality of first-in first-out storage structures, and the slope data unit comprises the effective data field and the type field.
2. The data processing method of claim 1, wherein the write condition comprises invalidating a full signal of all fifo memory structures in the first fifo memory matrix.
3. The data processing method according to claim 1, characterized in that after the writing step, the data processing method further comprises:
A reading step, in the case of meeting the reading condition, sequentially reading the respective stored slope data units from the selected first-in first-out storage structure in the first-in first-out storage matrix;
A generation step, converting a plurality of slope data units read in sequence into Flit data packets;
and a sending step, sending the Flit data packet.
4. A data processing method according to claim 3, wherein,
The read condition includes that at least 7 consecutive first-in-first-out memory structures in the first-in-first-out memory matrix have null signals that are not valid, and, correspondingly,
The at least 7 consecutive first-in-first-out memory structures are selected,
The reading step includes: the slope data units stored in each fifo memory structure are sequentially read from the consecutive 7 fifo memory structures,
The generating step comprises the following steps: the 7 slope data units read sequentially are sequentially combined into 1 Flit data packet.
5. A data processing method according to claim 3, wherein,
The read condition includes that the number of first-in first-out memory structures in the first-in first-out memory matrix where null signals are invalid is less than 7, and correspondingly,
The fifo memory structure with null signals inactive is selected,
The reading step includes: sequentially reading the slope data units stored in each first-in first-out storage structure from the selected first-in first-out storage structure,
The generating step comprises the following steps: sequentially combining the plurality of slope data units and invalid data which are sequentially read into 1 Flit data packet.
6. The data processing method according to any one of claims 1 to 5, characterized in that before the extraction step, the data processing method further comprises:
receiving each channel data packet transmitted by the AXI interface through the transmitting interface;
converting the data packets of each channel into AXI protocol data packets of each channel;
Converting the AXI protocol data packets of each channel into various types of data packets with the lengths being preset values, wherein the various types of data packets comprise a data field, a type field for representing the type of the data packet and a flag bit for representing whether each bit of data of the data field is valid type data or not;
and arbitrating the data packets of the various types to transmit the data packets of the various types according to the arbitrated sequence, wherein the data packets of the various types transmitted according to the arbitrated sequence are the first data packets.
7. The method for data processing according to claim 6, wherein,
Each channel data packet comprises a write address AW channel data packet, a read address AR channel data packet, a write response B channel data packet, a write data W channel data packet and a read data R channel data packet, and correspondingly, each channel AXI protocol data packet comprises an AW channel AXI protocol data packet, an AR channel AXI protocol data packet, a B channel AXI protocol data packet, a W channel AXI protocol data packet and an R channel AXI protocol data packet; accordingly, it is
The converting the AXI protocol data packets of each channel into various data packets with the length being a preset value comprises the following steps:
According to the AW channel AXI protocol data packet, at least one of the AR channel AXI protocol data packet and the B channel AXI protocol data packet and invalid data, an AW_AR_B data packet with the length of the preset value is generated;
generating a W data packet with the length of the preset value according to the W channel AXI protocol data packet;
and generating an R data packet with the length of the preset value according to the R channel AXI protocol data packet.
8. The data processing method according to any one of claims 3 to 5, characterized in that after the transmitting step, the data processing method further comprises:
Receiving the Flit data packet;
analyzing the received Flit data packet, and carrying out parallel classification processing on a plurality of analyzed effective slot data units according to the analyzed type field;
and according to the sequence of converting the plurality of slope data units into Flit data packets in the generating step, writing the classified effective slope data units of various types into a corresponding type of first-in first-out storage matrix.
9. The data processing method according to claim 8, wherein after writing the classified valid slope data units of each type into the corresponding type of first-in-first-out memory matrix, the data processing method further comprises:
reading a predetermined number of effective slope data units from each type of first-in first-out memory matrix;
for each type of active slope data unit read,
Checking whether the valid slope data unit of the type is complete;
if the type of valid slope data unit is complete, the type of valid slope data unit is restored to the type of AXI protocol data packet according to the AXI format;
and transmitting the AXI protocol data packets of each type to the AXI interface through a receiving interface of the D2D interface.
10. A data transmission system, comprising:
A sending side buffer control module, configured to:
Under the condition that writing conditions are met, in response to receiving a first data packet comprising a flag bit, a data field and a type field, removing data with the flag bit in the data field invalid to extract the valid data field and the type field with the flag bit in the data field valid from the first data packet, wherein the first data packet is a fixed-length type data packet obtained after bandwidth conversion of a channel type data packet, and when the bandwidth conversion of the channel type data packet with the data length not reaching the fixed length is carried out, the first data packet is obtained by filling invalid data into the channel type data packet with the data length not reaching the fixed length, wherein the channel type data packet is received by a transmitting interface of a chip-to-chip (D2D) interface from an AXI interface, and the flag bit is used for identifying whether each bit data of the data field is valid type data or not, and the type field indicates the type of the first data packet;
Generating a slope data unit according to the extracted effective data field and the type field, and sequentially writing the generated slope data unit into a first-in first-out storage matrix, wherein the first-in first-out storage matrix comprises a plurality of first-in first-out storage structures, and the slope data unit comprises the effective data field and the type field.
11. The data transmission system of claim 10, wherein the write condition includes invalidating a full signal of all fifo memory structures in the first fifo memory matrix.
12. The data transmission system of claim 10, wherein the sender-side buffer control module is further configured to:
sequentially reading the respective stored slope data units from the selected first-in first-out memory structure in the first-in first-out memory matrix under the condition that the reading condition is met;
Converting the plurality of slope data units read sequentially into Flit data packets;
And sending the Flit data packet.
13. The data transmission system of claim 12, wherein,
The read condition includes that at least 7 consecutive first-in-first-out memory structures in the first-in-first-out memory matrix have null signals that are not valid, and, correspondingly,
The at least 7 consecutive first-in-first-out memory structures are selected,
The sending side cache control module is used for:
the slope data units stored in each fifo memory structure are sequentially read from the consecutive 7 fifo memory structures,
The 7 slope data units read sequentially are sequentially combined into 1 Flit data packet.
14. The data transmission system of claim 12, wherein,
The read condition includes that the number of first-in first-out memory structures in the first-in first-out memory matrix where null signals are invalid is less than 7, and correspondingly,
The fifo memory structure with null signals inactive is selected,
The sending side cache control module is used for:
Sequentially reading the slope data units stored in each first-in first-out storage structure from the selected first-in first-out storage structure,
Sequentially combining the plurality of slope data units and invalid data which are sequentially read into 1 Flit data packet.
15. The data transmission system according to any one of claims 10 to 14, further comprising:
the sending interface is used for receiving each channel data packet transmitted by the AXI interface;
A format generator, configured to convert the data packets of each channel into AXI protocol data packets of each channel, and convert the AXI protocol data packets of each channel into various types of data packets with lengths each being a predetermined value, where the various types of data packets include a data field, a type field that indicates a type of the data packet, and a flag bit that indicates whether each bit of data of the data field is valid type data;
And the arbiter is used for arbitrating the data packets of the various types to transmit the data packets of the various types according to the arbitrated sequence, wherein the data packets of the various types transmitted according to the arbitrated sequence are the first data packets.
16. The data transmission system of claim 15, wherein,
Each channel data packet comprises a write address AW channel data packet, a read address AR channel data packet, a write response B channel data packet, a write data W channel data packet and a read data R channel data packet, and correspondingly, each channel AXI protocol data packet comprises an AW channel AXI protocol data packet, an AR channel AXI protocol data packet, a B channel AXI protocol data packet, a W channel AXI protocol data packet and an R channel AXI protocol data packet; accordingly, it is
The format generator is used for:
According to the AW channel AXI protocol data packet, at least one of the AR channel AXI protocol data packet and the B channel AXI protocol data packet and invalid data, an AW_AR_B data packet with the length of the preset value is generated;
generating a W data packet with the length of the preset value according to the W channel AXI protocol data packet;
and generating an R data packet with the length of the preset value according to the R channel AXI protocol data packet.
17. The data transmission system according to any one of claims 12 to 14, further comprising:
The analysis module is used for receiving the Flit data packet, analyzing the received Flit data packet, and carrying out parallel classification processing on a plurality of analyzed effective slot data units according to the analyzed type field;
And the receiving side buffer control module is used for writing the classified effective slope data units into the corresponding type first-in first-out storage matrix according to the sequence of converting the plurality of slope data units into the Flit data packets by the sending side buffer control module.
18. The data transmission system of claim 17, further comprising:
A type generator for reading a predetermined number of active slope data units from the first-in first-out memory matrices of each type, for each type of active slope data unit read,
Checking whether the valid slope data unit of the type is complete;
if the type of valid slope data unit is complete, the type of valid slope data unit is restored to the type of AXI protocol data packet according to the AXI format;
and the receiving interface of the D2D interface is used for transmitting the AXI protocol data packets of all types to the AXI interface.
19. An electronic device, comprising:
A processor;
a memory for storing processor-executable instructions;
Wherein the processor is configured to implement the data processing method of any of claims 1-9 when executing the instructions stored by the memory.
20. A non-transitory computer readable storage medium having stored thereon computer program instructions, which when executed by a processor, implement the data processing method of any of claims 1-9.
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| CN116795763A (en) * | 2023-07-31 | 2023-09-22 | 摩尔线程智能科技(北京)有限责任公司 | Method, system on chip and chip for data packet transmission based on AXI protocol |
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