CN119051663A - Digital circuit of multichannel JESD 204B receiving end - Google Patents
Digital circuit of multichannel JESD 204B receiving end Download PDFInfo
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
本申请提供一种多通道JESD 204B接收端的数字电路，该电路包括：启动模块、数据流处理模块，通过启动模块产生启动信号，基于外部输入的预设配置信息将数字电路的信息进行配置，启动数字电路，通过数据流处理模块接收JESD 204B发送端发送的第一预设多通道的待传输数字信号，基于预设配置信息通道连接关系传输待传输数字信号，将传输的数字信号进行信号同步后在根据数字电路的工作模式进行映射输出，得到第二预设多通道的数字信号。本申请提供的多通道JESD 204B接收端的数字电路，实现JESD 204B协议中规定的数据链路层，传输层数字信号处理功能，通过增加数字逻辑的方式，减少电路板走线，达到提升数字信号的传输速率。
The present application provides a digital circuit of a multi-channel JESD 204B receiving end, and the circuit includes: a startup module and a data stream processing module, wherein a startup signal is generated by the startup module, and the information of the digital circuit is configured based on the preset configuration information input externally, and the digital circuit is started, and the first preset multi-channel digital signal to be transmitted sent by the JESD 204B transmitting end is received by the data stream processing module, and the digital signal to be transmitted is transmitted based on the preset configuration information channel connection relationship, and the digital signal to be transmitted is synchronized and then mapped and output according to the working mode of the digital circuit to obtain the second preset multi-channel digital signal. The digital circuit of the multi-channel JESD 204B receiving end provided by the present application implements the data link layer and the transmission layer digital signal processing functions specified in the JESD 204B protocol, and reduces the circuit board routing by adding digital logic, so as to improve the transmission rate of the digital signal.
Description
Technical Field
The invention relates to the field of digital circuits, in particular to a digital circuit of a multichannel JESD204B receiving end.
Background
Digital-to-analog converters (DACs) are used to convert digital signals to analog signals, with the inputs being digital signals and the outputs being analog signals. The digital signal input interface of the early Low-speed digital-to-analog converter uses a CMOS interface (Complementary MetalOxide Semiconductor), and the digital signal input interface of the later digital-to-analog converter starts to use an LVDS differential interface (Low Voltage DIFFERENTIAL SIGNALING, i.e., a Low Voltage differential signal) along with the increase of the sampling speed. However, the CMOS interface has a certain problem in data transmission, the number of wires on the circuit board is greatly increased along with the increase of the bit width of the digital-to-analog converter, the length of each wire is consistent to achieve wire delay matching, a large number of wires on the circuit board are easy to be interfered to influence the effective transmission of data, and the CMOS interface cannot complete the high-speed transmission of multi-bit digital signals along with the further increase of the sampling speed of the digital-to-analog converter.
Therefore, how to provide a digital circuit capable of satisfying the signal input of the digital signal input interface of the high-speed digital-to-analog converter is a technical problem to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a digital circuit of a multi-channel JESD 204B receiver to solve at least one of the above-mentioned problems.
In order to achieve the above and other related objects, the present application provides the following technical solutions.
According to an aspect of an embodiment of the present application, there is provided a digital circuit of a receiving end of a multi-channel JESD 204B, including:
The starting module is used for generating a starting signal and carrying out information configuration on the digital circuit based on preset configuration information so as to start the digital circuit;
The data stream processing module is used for receiving a first preset multi-channel digital signal to be transmitted sent by a JESD 204B sending end, carrying out signal transmission on the digital signal to be transmitted based on a preset channel connection relation in the preset configuration information, carrying out signal synchronization processing on the transmitted digital signal, and carrying out mapping output according to a working mode in the preset configuration information to obtain a second preset multi-channel digital signal;
The signal transmission rate of the output end of the data stream processing module is matched with the signal transmission rate of the input end of the data stream processing module.
In an embodiment of the invention, the data stream processing module comprises a signal input unit, a data synchronization unit and a data output unit, wherein the signal input unit is used for receiving the digital signals to be transmitted, respectively storing each digital signal to be transmitted, and transmitting the stored digital signals to output a plurality of first intermediate signals, the data synchronization unit is used for respectively carrying out signal synchronization processing and data decoding on the plurality of first intermediate signals to obtain a plurality of second intermediate signals, and the data output unit is used for carrying out mapping transmission on the plurality of second intermediate signals based on the working mode in the preset configuration information to obtain the second preset multichannel digital signals.
In an embodiment of the invention, the signal input unit comprises N input buffer subunits, a data routing subunit and a data processing subunit, wherein the N input buffer subunits are used for receiving and buffering a first preset multi-channel digital signal to be transmitted sent by a JESD204B sending end, correlating the digital signal to be transmitted with a clock signal in the starting signal, the data routing subunit is used for carrying out signal transmission on data of each input buffer subunit according to a preset channel connection relation in preset configuration information, and outputting a plurality of first intermediate signals to the outside, wherein N is more than or equal to 2, and N corresponds to the number of channels.
In one embodiment of the invention, the data synchronization unit comprises N code group synchronization subunits, N decoding subunits and N initial channel synchronization subunits, wherein the N code group synchronization subunits are used for performing code group synchronization on first intermediate signals of each channel based on multi-frame clock signals and adjusting the state of the code group synchronization based on decoding results so as to align the first intermediate signals of the multi-channels, the N decoding subunits are used for respectively decoding signals output by the N code group synchronization subunits to obtain decoding results, and the N initial channel synchronization subunits are used for respectively performing initial channel synchronization on the signals output by the N decoding subunits and aligning the boundaries of multi-frame clocks to obtain N second intermediate signals.
In an embodiment of the invention, the data output unit comprises N signal recovery subunits, a de-frame mapping subunit and a mapping unit, wherein the N signal recovery subunits are used for respectively descrambling and replacing characters of second intermediate signals of each channel, and the de-frame mapping subunit is used for correspondingly mapping signals output by the N signal recovery subunits based on the working mode to obtain the digital signals of the second preset multiple channels.
In one embodiment of the invention, the starting module comprises an information configuration unit for receiving the preset configuration information and generating configuration information of each module of the digital circuit based on the preset configuration information, and a clock synchronization unit for generating the internal clock signal and the multi-frame clock signal based on the external clock signal, a plurality of frequency division signals and a plurality of sampling signals, wherein the phases of the sampling signals are different.
In an embodiment of the invention, the information configuration unit comprises a receiving subunit, a storage subunit and a parsing subunit, wherein the receiving subunit is used for receiving the preset configuration information, the storage subunit is used for storing the preset configuration information, and the parsing subunit is used for parsing the preset configuration information in the storage subunit to obtain the configuration information of each module.
In one embodiment of the invention, the clock synchronization unit comprises a synchronization adjustment subunit, a clock reset subunit, a boundary adjustment subunit and a boundary adjustment subunit, wherein the synchronization adjustment subunit is used for determining the phase relation between an analog sampling signal in an analog circuit and a plurality of frequency division signals according to the plurality of sampling signals and generating a delay signal and a clock reset signal, transmitting the delay signal to the analog circuit for multi-chip clock synchronization adjustment, the clock reset subunit is used for receiving the external clock signal, setting an internal clock signal of the digital circuit according to the external clock signal and the clock reset signal and generating a corresponding multi-frame clock signal based on the working mode, and the boundary adjustment subunit is used for communicating with a JESD 204B transmitting end and synchronizing the edges of the multi-frame clock signal so as to pull up or pull down the boundary of the multi-frame clock signal.
In an embodiment of the present invention, the digital circuit further includes a monitoring module, where the monitoring module is configured to monitor the data stream processing module for anomalies.
In an embodiment of the invention, the monitoring module comprises a monitoring unit and a data flow verification unit, wherein the monitoring unit is used for monitoring the digital circuit for abnormality and counting abnormal conditions, and the data flow verification unit is used for verifying the data of the digital signal to be transmitted of the signal input unit based on the verification code, and analyzing and verifying the configuration information of the initial channel synchronization subunit.
The application provides a digital circuit of a multichannel JESD 204B receiving end, which comprises a starting module and a data stream processing module, wherein the starting module is used for generating a starting signal, configuring information of the digital circuit based on preset configuration information input from the outside, starting the digital circuit, receiving a first preset multichannel digital signal to be transmitted sent by the JESD 204B sending end through the data stream processing module, transmitting the digital signal to be transmitted based on a preset configuration information channel connection relation, synchronizing the transmitted digital signal, and mapping and outputting the digital signal according to the working mode of the digital circuit to obtain a second preset multichannel digital signal. The digital circuit of the receiving end of the multichannel JESD 204B provided by the application realizes the data link layer and transmission layer digital signal processing function specified in the JESD 204B protocol, reduces wiring of a circuit board by adding digital logic, and achieves the aim of improving the transmission rate of digital signals.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:
FIG. 1 is a diagram of the locations of a multichannel JESD 204B sender and a portion of a receiver in a mode converter, as shown in an exemplary embodiment of the present invention;
FIG. 2 is a diagram of the location of the receive side of a portion of a multichannel JESD 204B receiver in a digital-to-analog converter, according to an exemplary embodiment of the present invention;
FIG. 3 is a block diagram of digital circuitry of a multichannel JESD 204B receiver, as shown in an exemplary embodiment of the present invention;
FIG. 4 is a block diagram of a digital circuit of a receiving side of a multichannel JESD 204B receiver according to an exemplary embodiment of the present invention;
FIG. 5 is an internal block diagram of an input cache subunit shown in an exemplary embodiment of the invention;
FIG. 6 is a state machine transition diagram during a code group synchronization process, as shown in an exemplary embodiment of the present invention;
FIG. 7 is a state machine transition diagram during initial channel synchronization, as shown in an exemplary embodiment of the present invention;
FIG. 8 is an internal block diagram of a de-framing mapping subunit shown in accordance with an exemplary embodiment of the present invention;
FIG. 9 is a diagram illustrating the mapping of frame data to DACSAMPLES when the digital circuit is operating at mode0 in accordance with an exemplary embodiment of the present invention;
FIG. 10 is a diagram illustrating the mapping of frame data to DACSAMPLES when the digital circuit is operating in mode1, according to an example embodiment of the present invention;
FIG. 11 is a diagram showing the connection of a clock synchronization unit to different modules in an analog circuit according to an exemplary embodiment of the present invention;
Fig. 12 is a diagram illustrating internal clock relationships after multi-chip alignment according to an exemplary embodiment of the present invention.
Detailed Description
Further advantages and effects of the present invention will become readily apparent to those skilled in the art from the disclosure herein, by referring to the accompanying drawings and the preferred embodiments. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
Glue logic is a generic term for simple logic circuits that connect complex logic circuits. It generally refers to the use of fewer logic gates or other basic logic elements in an integrated circuit design to connect and integrate complex functional units such as microprocessors, memory functional blocks, or communication functional blocks, etc. to perform a specific circuit function.
Digital-to-analog converters (DACs) are used to convert digital signals to analog signals, with the inputs being digital signals and the outputs being analog signals. The digital signal input interface of the early Low-speed digital-to-analog converter uses a CMOS interface (Complementary MetalOxide Semiconductor), and the digital signal input interface of the later digital-to-analog converter starts to use an LVDS differential interface (Low Voltage DIFFERENTIAL SIGNALING, i.e., a Low Voltage differential signal) along with the increase of the sampling speed. However, the CMOS interface has a certain problem in data transmission, the number of wires on the circuit board is greatly increased along with the increase of the bit width of the digital-to-analog converter, the length of each wire is consistent to achieve wire delay matching, a large number of wires on the circuit board are easy to be interfered to influence the effective transmission of data, and the CMOS interface cannot complete the high-speed transmission of multi-bit digital signals along with the further increase of the sampling speed of the digital-to-analog converter.
In the digital-to-analog converter system, if the JESD204B protocol is adopted to receive high-speed digital signals, the digital circuit of the receiving end of the multi-channel JESD204B is positioned in the system as shown in fig. 1-2. As shown in fig. 1, 204B Tx framer is a data transmitting end, and transmits 40bit wide data of N lane. The serializer is a parallel-serial conversion circuit, and has the function of converting 40bit data of N lane into 1bit high-speed serial data stream of N lane, wherein the highest rate of each lane is 12.5Gbps, which is a physical layer circuit of a transmitting end. The de-serializer is a serial-parallel conversion circuit that functions to convert a 1-bit high-speed serial data stream of N lane into 40-bit data of N lane. glue logic is used for buffering data transmission between the deserializer and deframer, and ensuring stable data reception. The deservatizer, together with the glue-logic, completes the physical layer signal processing of the receiver portion of the JESD204B protocol.
As shown in FIG. 2, the digital logic circuit includes an N-LANE DEFRAMER module, an FIR+ assemble module, and a top_clk_gen module. N-LANE DEFRAMER is the digital circuit of the receiving end of the multichannel JESD 204B designed by the invention, the signal processing of the data link layer and the transmission layer of the receiving end part in the JESD 204B protocol is completed, and the final output result is DAC SAMPLES data obtained after frame decomposition. The FIR + assemble module is used for decimating filtering and 16 in 4 data stream combining. the top_clk_gen module is used for clock distribution on the digital top layer.
As shown in fig. 2, the fir+ assemble module outputs 4 paths of 16bit data synchronized with clk0 to clk3, decodes the data into 4 paths of 31bit data through the temperaturedecoder module, performs 4-in-1 operation through the mux module, combines the data into 1 path of 31bit data stream (speed is increased by 4 times), and finally outputs the data to a digital-to-analog converter (DAC) after passing through the latch module. DAC working clock clkdac is divided into clk 0-clk 3 through clkdiv module in four ways, and clk 0-clk 3 are used as reference clocks of FIR+ assemble modules and are different in phase by 90 degrees in sequence.
It should be noted that, where N is the number of channels corresponding to the digital circuit, the value of N may be 4 channels, 8 channels, and 16 channels.
As shown in fig. 3, the present application provides a digital circuit of a receiving end of a multi-channel JESD 204B, which includes:
The starting module is used for generating a starting signal and carrying out information configuration on the digital circuit based on preset configuration information so as to start the digital circuit;
the data stream processing module is used for receiving a first preset multi-channel digital signal to be transmitted sent by a JESD 204B sending end, carrying out signal transmission on the digital signal to be transmitted based on a preset channel connection relation in preset configuration information, carrying out signal synchronization processing on the digital signal after transmission, and carrying out mapping output according to a working mode in the preset configuration information to obtain a second preset multi-channel digital signal;
the signal transmission rate of the output end of the data stream processing module is matched with the signal transmission rate of the input end of the data stream processing module.
Specifically, the starting module is used for carrying out information matching according to preset configuration information input by the digital circuit, so that the configuration of the preset information is completed in the digital circuit, meanwhile, a starting signal of the digital circuit is generated according to an external clock signal distributed by the top_clk_gen module, an N-channel 40bit digital signal to be transmitted, which is sent by a glue-logic, is received through the data stream processing module, and a data link layer and a transmission layer data processing of a JESD 204B receiving end are carried out on the N-channel 40bit digital signal to be transmitted, so that an M-channel 16bit digital signal is obtained.
It should be noted that, the data stream processing module receives 8 40bit digital signals to be transmitted sent by the glue-logic, when the highest bit stream rate of each channel is 12.5Gbps, the highest working clock of the digital circuit is not more than 312.5MHz (12.5 GHz/40=312.5 MHz). The total highest bit stream rate of the 8-channel digital circuit is 12.5gbps×8×8 (8/10) =80 Gbps. Selecting a 16-channel 16-bit interface based on a preset configuration information digital circuit output end; 16bit x 312.5 mhz=80 Gbps. It follows that the input signal transmission rate of the data processing module and the output signal transmission rate of the data stream processing module are matched with each other.
The data stream processing module comprises a signal input unit, a data synchronization unit and a data output unit, wherein the signal input unit is used for receiving digital signals to be transmitted, respectively storing each digital signal to be transmitted, and carrying out signal transmission on the stored digital signals so as to output a plurality of first intermediate signals, the data synchronization unit is used for respectively carrying out signal synchronization processing and data decoding on the plurality of first intermediate signals to obtain a plurality of second intermediate signals, and the data output unit is used for carrying out mapping transmission on the plurality of second intermediate signals based on a working mode in preset configuration information to obtain a second preset multichannel digital signal.
In more detail, the signal input unit comprises N input buffer subunits, a data routing subunit and a data processing subunit, wherein the N input buffer subunits are used for receiving and buffering first preset multi-channel digital signals to be transmitted sent by a JESD 204B sending end, correlating the digital signals to be transmitted with internal clock signals in a starting signal, the data routing subunit is used for carrying out signal transmission on data of each input buffer subunit according to a preset channel connection relation in preset configuration information, and outputting a plurality of first intermediate signals to the outside, wherein N is more than or equal to 2, and N corresponds to the number of channels. Specifically, as shown in fig. 4, when the hardware transmission channel of the digital circuit is 8 channels, the signal input unit includes 8 input buffer subunits, that is, 8 input_fifo, and the 8 input buffer subunits receive serial-to-parallel converted 40bit wide data wdata [39:0] to wdata [39:0] sent by 8 channel deserializers, each channel deserializer sends 4-way clock wclk1 to wclk4, the 4-way clock is wclk1 is wdata [9:0], wclk2 is wdata [19:10], wclk is wdata [29:20], wclk is wdata [39:30], and the 8 channels include 32-way clocks, each-way clock has the same frequency as the internal clock signal of the digital circuit, but has different phases, and the highest frequency of the channel clock is not more than 312.5MHz. As shown in fig. 5, each input buffer subunit includes 4 FIFO structures with 16×10 bits therein, the input 40 bits of data are stored in the 4 FIFO structures, and the 8 input buffer subunits further synchronize wdata [9:0], wdata [19:10], wdata [29:20], wdata [39:30] input in the channel clock to the clock signal in the digital circuit. As shown in fig. 5, wrst1_n to wrst4_n are reset signals of 16×10bit fifo1 to 16×10bit fifo4, respectively, for performing a reset operation on the fifo structure. The signal input unit comprises a data routing subunit, namely xbar, the data routing subunit transmits the fifo 0_rdata-fifo 7_rdata output by the 8 input buffer subunits to the corresponding position of the output interfaces lane0_data-lane7_data of the data routing subunit according to the preset channel connection relation, so as to realize the exchange transmission function of the 8 channel data positions according to the preset channel connection relation, and the data routing subunit outputs first intermediate signals (lane0_data-lane7_data) of a plurality of channels to the outside.
The data synchronization unit comprises N code group synchronization subunits, N decoding subunits and N initial channel synchronization subunits, wherein the N code group synchronization subunits are used for carrying out code group synchronization on first intermediate signals of each channel based on multi-frame clock signals and adjusting the state of the code group synchronization based on decoding results so as to align the first intermediate signals of the multi-channels, the N decoding subunits are used for respectively decoding signals output by the N code group synchronization subunits to obtain decoding results, and the N initial channel synchronization subunits are used for respectively carrying out initial channel synchronization on the signals output by the N decoding subunits and aligning the boundaries of multi-frame clocks to obtain N second intermediate signals.
Specifically, as shown in fig. 4, when the hardware transmission channel of the digital circuit is 8 channels, the data synchronization unit includes 8 code group synchronization sub-units, i.e., 8 cgs_fsm0 to cgs_fsm7. Each code group synchronization subunit (cgs_fsm) works independently, the code group synchronization subunit (cgs_fsm) performs code group synchronization on a plurality of first intermediate signals lane0_data-lane7_data output by the output interface of the routing subunit according to multi-frame clock signals, the code word boundaries of the 40bit first intermediate signals are aligned, and when the first intermediate signals perform code group synchronization, the code group synchronization state is regulated according to the decoding result. The 8 decoding subunits, namely 8 decoding_10b8b_0-decoding_10b8b_7, decode the signal output by the code group synchronization subunit by each decoding subunit (decoding_10b8b), and change the data processed by each clock signal from 40 bits to 32 bits. 8 initial channel synchronous subunits, namely 8 ila _fsm0-ila _fsm7, each of which independently works, and signals output by N decoding subunits corresponding to each initial channel synchronous subunit complete ILAS state synchronization and realize multi-frame boundary alignment of 32bit data.
As shown in FIG. 6, the synchronization process of the code group synchronization subunit is that after the digital circuit is started, the state jumps from CS_IDLE to CS_INIT, after 4 continuous/K/codes are detected, the state jumps to CS_WAIT1, then through CS_WAIT2 and CS_WAIT3, jumps to CS_CHECK. And if the decoding result of the decoding subunit exceeds 4 continuous correct code words, entering a CS_DATA state to continuously receive subsequent DATA, if the error code words in the decoding result of the decoding subunit are accumulated to exceed 3, and the code group is broken synchronously, the state is skipped from CS_CHECK to CS_INIT for reconstructing the chain, and if the DATA receiving state is in CS_DATA state, the state is skipped to CS_CHECK for reconstructing immediately.
As shown in FIG. 7, the synchronization process of the initial channel synchronization subunit is that when the valid DATA synchronized by the code group reaches the unit, the state jumps from IDLE to INIT, after detecting/R/code, the state jumps to ILAS, and if receiving successfully, the ILAS DATA of 4 continuous multiframes is received in the state, and if receiving successfully, the state jumps to DATA state to receive the user DATA. If the ILAS state is broken, the ILAS_CHECK state is skipped, if the ILAS_CHECK state can detect the continuous 4/K/codes, the ILAS_CHECK state is skipped to search for the R/codes again, and if the ILAS_CHECK state does not detect the continuous 4/K/codes, the ILAS state is resumed to receive ILAS data. In the DATA state, the broken chain occurs, the arrival of 4 continuous/K/codes is detected, the DATA_CHECK state is skipped, if the continuous 4 continuous/K/codes can be detected in the DATA_CHECK state, the INIT is skipped to search for/R/codes again, and if the continuous 4 continuous/K/codes are not detected any more, the DATA state is returned to continue receiving the user DATA.
The data output unit comprises N signal recovery subunits and a de-frame mapping subunit, wherein the N signal recovery subunits are used for respectively descrambling second intermediate signals of all channels and then performing character replacement, and the de-frame mapping subunit is used for performing corresponding mapping on signals output by the N signal recovery subunits based on a working mode to obtain second preset multi-channel digital signals. Specifically, as shown in fig. 4, the signal recovery subunit includes descramble and rx_replay, the signal output by the initial channel synchronization subunit is descrambled in parallel through descramble to complete 1+x14+x15 polynomial descrambling, if the data signal is not scrambled during data transmission, the transmitted digital signal is not descrambled, the signal output by the initial channel synchronization subunit is directly transmitted to the rx_replay, and the signal output by the initial channel synchronization subunit or the descrambled data through the rx_replay completes a character replacement function in JESD 204B protocol, for example, 20 is replaced with a during data transmission, and a is replaced with 20 at the receiving end of JESD 204B through the rx_replay. The data output unit includes a de-frame mapping subunit, as shown in fig. 4, where the de-frame mapping subunit is tpl_map, and the internal structure diagram of the de-frame mapping subunit is shown in fig. 8, where the problem of signal transmission delay between 8 channels is handled by 8 FIFO with 24×32bit as elastic FIFO, and the 8 elastic FIFO can be uniformly released at the boundary (LMFC) of the multi-frame clock signal, so as to achieve a deterministic delay function, where the depth of the elastic FIFO exceeds the longest LMFC (period of the multi-frame clock signal).
If there are 2 mapping modes of the deframer mapping subunit, according to the working modes, the mapping modes are as shown in table 1:
TABLE 1
The Mode of operation of the digital circuit is Mode0, and the frame data is mapped to DAC SAMPLES as shown in fig. 9, in this Mode of operation, l=8, m=1, f=1, s=4, and the mapping relationship between the digital signal at the input end and the digital signal at the output end is transmitted according to the preset configuration information of the digital circuit. A small square block in fig. 9 represents 1 byte data. 1 cycle of the internal clock signal, as shown in FIG. 9, when 4bytes of data is sent per lane, 8 lanes total 32bytes of data. The method comprises the steps of combining the byte with the number 01 of the first channel (Lane 0) and the byte with the number 11 of the second channel (Lane 1) into the 1 st sample (M0S 0) of the DAC, combining the byte with the number 21 of the third channel (Lane 2) and the byte with the number 31 of the fourth channel (Lane 3) into the 2 nd sample (M0S 1) of the DAC, combining the byte with the number 41 of the fifth channel (Lane 4) and the byte with the number 51 of the sixth channel (Lane 5) into the 3 rd sample (M0S 2) of the DAC, combining the byte with the number 61 of the seventh channel (Lane 6) and the byte with the number 71 of the eighth channel (Lane 7) into the 4 th sample (M0S 3) of the DAC, mapping the subsequent sample, and so on, wherein the total 32byte data can be combined into 16 samples DAC SAMPLES.
The Mode of operation of the digital circuit is Mode1, in which l=8, m= 2,F =1, and s=2, the frame data is mapped to DAC SAMPLES as shown in fig. 10. 1 cycle of the internal clock signal, as shown in FIG. 10, the byte numbered 01 of the first channel (Lane 0) and the byte numbered 11 of the second channel (Lane 1) are combined into the 1 st sample (M0S 0) of the DAC; the byte number 21 of the third channel (lane 2) and the byte number 31 of the fourth channel (lane 3) are combined to form the 2 nd sample (M0S 1) of the DAC; combining byte number 02 of the first channel (lane 0) and byte number 12 of the second channel (lane 1) into the 3 rd sample (M0S 2) of the DAC; the combination of 22-numbered bytes of the third channel (Lane 2) and 32-numbered bytes of the fourth channel (Lane 3) is the 4 th sample (M0S 3) of the DAC, the combination of 41-numbered bytes of the fifth channel (Lane 4) and 51-numbered bytes of the sixth channel (Lane 5) is the 5 th sample (M0S 0) of the DAC, the combination of 61-numbered bytes of the seventh channel (Lane 6) and 71-numbered bytes of the eighth channel (Lane 7) is the 6 th sample (M0S 1) of the DAC, the combination of 52-numbered bytes of the fifth channel (Lane 4) and 52-numbered bytes of the sixth channel (Lane 5) is the seventh sample (M0S 2) of the DAC, the combination of 62-numbered bytes of the seventh channel (Lane 6) and 72-numbered bytes of the eighth channel (Lane 7) is the 6-numbered sample (M0S 1) of the DAC, and the total data of the combination of the bits of the samples of the DAC can be mapped to the 25 th sample (M0S 3) of the DAC.
It should be noted that, the mapping modes of the de-frame mapping subunit are not only the two modes mentioned above, but also include other mapping modes in the JESD204B protocol, and the data transmission mode is changed according to the mapping modes, so that specific output principles of the other mapping modes are not repeated here.
The starting module comprises an information configuration unit, a clock synchronization unit and a starting module, wherein the information configuration unit is used for receiving preset configuration information and generating configuration information of each module of the digital circuit based on the preset configuration information, the clock synchronization unit is used for generating an internal clock signal and a multi-frame clock signal based on an external clock signal, a plurality of frequency division signals and a plurality of sampling signals, and the phases of the sampling signals are different. Specifically, as shown in fig. 4, the preset configuration information is received through an SPI serial interface in the digital circuit, the timing sequence is converted into an internal register read-write timing sequence through an spi_if, the preset configuration information is stored, the configuration information of each unit of the data stream processing module is sent to each unit, or a status flag signal of the digital circuit can be read through an upper computer, and the signal synchronization unit receives an external clock signal, a plurality of frequency division signals and a plurality of sampling signals sent by an analog circuit to perform time synchronization, so as to obtain an internal clock signal and a multi-frame clock signal.
The information configuration unit comprises a receiving subunit, a storage subunit and a parsing subunit, wherein the receiving subunit is used for receiving preset configuration information, the storage subunit is used for storing the preset configuration information, and the parsing subunit is used for parsing the preset configuration information in the storage subunit to obtain the configuration information of each module. Specifically, as shown in fig. 4, the receiving subunit (SPI serial interface) receives preset configuration information, and converts the time sequence of the received configuration information into the internal register read-write time sequence through the storage subunit (spi_if), stores the preset configuration information, the analyzing subunit includes spi_reg and cfg_glue, receives the read-write access request sent by the storage subunit through the spi_reg, analyzes the value configuring each register, receives the value of the spi_reg register from the cfg_glue, analyzes the value in the register, and obtains the configuration information and parameters of each unit of the data stream processing module, including mainly the 204B protocol parameters such as the working mode, L, M, N, S, F, etc., and sends the analyzed configuration information to each unit of the data stream processing module, or reads whether the digital circuit is in the signal transmission state through the upper computer.
The clock synchronization unit comprises a synchronization adjustment subunit, a clock resetting subunit and a boundary adjustment subunit, wherein the synchronization adjustment subunit is used for determining the phase relation between an analog sampling signal and a plurality of frequency division signals in an analog circuit according to a plurality of sampling signals, generating a delay signal and a clock resetting signal, transmitting the delay signal to the analog circuit for multi-chip clock synchronization adjustment, the clock resetting subunit is used for receiving an external clock signal, setting an internal clock signal of a digital circuit according to the external clock signal and the clock resetting signal and generating a corresponding multi-frame clock signal based on an operating mode, and the boundary adjustment subunit is used for communicating with a JESD 204B transmitting end, synchronizing the edges of the multi-frame clock signal and pulling up or pulling down the boundary of the multi-frame clock signal.
Specifically, as shown in fig. 4, the multi-chip synchronization requires that multiple chips transmit or receive data at the boundary of the same multi-frame clock signal LMFC, and further requires that the clock signals of the multiple chips be aligned, and further requires that multiple frequency division signals clk 0-clk 3 of the digital logic of the multiple chips be aligned. The sysref module cooperates with the clkdiv and sysref _sample modules to achieve the alignment function of the multiple frequency division signals clk 0-clk 3 among multiple chips, and finally achieves the effect of multi-chip synchronization, wherein the multi-chip synchronization condition is shown in fig. 12.
As shown in fig. 11, clkdiv is a clock frequency dividing unit in an analog circuit, and has a main function of dividing the DAC working clock clkdac into a plurality of frequency-divided signals clk0 to clk3, and receiving pulses of a delay signal sync_pulse fed back by the synchronization regulating subunit, and delaying clk0 to clk3 by a corresponding clkdac cycles according to the number of pulses in the sync_pulse. sysref _sample is a clock sampling unit in an analog circuit, and has a main function of sampling an analog sampling signal sysref input by an external interface by clk 0-clk 3 to generate a plurality of sampling signals sysref 0-sysref signals.
The synchronous regulation subunit, sysref, mainly has the function of acquiring the phase relation of a plurality of sampling signals (sysref 0-sysref 3) according to a plurality of received sampling signals (sysref 0-sysref) so as to determine the phase relation of an analog sampling signal sysref and a plurality of frequency division signals clk 0-clk 3, thereby generating a delay signal sync_pulse and a clock reset signal sysref _sync, and sending the correct number of delay signal sync_pulse pulses to a clock frequency division unit in an analog circuit for adjusting the phases of the plurality of frequency division signals clk 0-clk 3. Through adjustment, clk 0-clk 3 among the chips are synchronized, and then an external clock signal output in the top_clk_gen module is adjusted.
The clock reset subunit, as shown in fig. 4, namely pclk_gen, receives the external clock signal Plck and the clock reset signal sysref _sync to generate an internal clock signal Plck (312.5 Mkz) of the digital circuit, and generates a multi-frame clock signal LMFC according to an operation mode of the digital circuit, and the boundary adjusting subunit, namely sync_gen, performs interactive communication with the JESD 204B transmitting end through a sync_n signal, and merges the sync_n signals sent by 8 cgs_fsm together to pull up or pull down at the boundary of the multi-frame clock signal LMFC.
In detail, the digital circuit also comprises a monitoring module, and the monitoring module is used for monitoring the abnormality of the data stream processing module.
The monitoring module comprises a monitoring unit and a data flow verification unit, wherein the monitoring unit is used for monitoring the digital circuit for abnormality and counting abnormal conditions, and the data flow verification unit is used for carrying out data verification on the digital signal to be transmitted of the signal input unit based on the verification code, and analyzing and verifying the configuration information of the initial channel synchronization subunit. Specifically, as shown in fig. 4, the monitoring unit, namely err_mon, is used for monitoring errors of all channels of the digital circuit, counting not in table error (NIT) of a plurality of channels, baddisparity error (BDE), unexpected K (UEK) CHARACTER ERROR, and initiating interruption or direct chain breaking after the number exceeds a threshold, the data stream verification unit comprises PRBS _check and linkcfg _decode, and the PRBS7, PRBS15 and PRBS31 of all channels are completed through the PRBS _check module, and the data input by the signal input unit is verified according to the verification code, and pseudo random codes are added in data transmission to verify whether the data transmission is correct. And analyzing the configuration information of the initial channel synchronization stage through linkcfg _decode, and if the analyzed configuration information is not matched with the preset configuration information, failing to transmit.
As shown in fig. 4, the digital circuit further includes a reset unit (rst_gen) for receiving a reset signal rst_n to perform a reset operation on the digital circuit.
It should be noted that, if the digital circuit provided by the present application is a digital circuit of a JESD 204B receiving end with 8 channels, the digital signals to be transmitted may be 1, 2,3, 4, 6, 8 channels, which are determined according to the JESD 204B protocol, and the number of the channels for specific operation is determined according to the transmitted digital signals and the protocol together.
The working flow of the digital circuit of the multichannel JESD204B receiving end provided by the application is that the whole JESD204B system is electrified, the JESD204B sending end is well configured, the information of the JESD204B receiving end is mainly configured with a working mode and protocol related parameters through an information configuration unit, when a plurality of chips work simultaneously, the synchronization of a clock signal in the JESD204B and an external chip is realized through a clock synchronization unit, the digital circuit is started, the digital circuit and the JESD204B sending end interact through sync_n, the code group synchronization and ILAS synchronization of the transmitted digital signal are sequentially carried out, and the high-speed transmission of the digital signal is completed in a data transmission stage.
The application provides a digital circuit of a multichannel JESD 204B receiving end, which comprises a starting module and a data stream processing module, wherein the starting module is used for selecting the number of data transmission channels through preset configuration information in the starting module, generating a starting signal to start the digital circuit, receiving a digital signal to be transmitted sent by a JESD 204B sending end through the data stream processing module, carrying out signal transmission on the digital signal to be transmitted based on a preset channel connection relation in the preset configuration information, carrying out signal synchronization processing on the digital signal after transmission, and carrying out mapping output according to a working mode in the preset configuration information to obtain the digital signal, reducing the wiring of a circuit board in a mode of increasing digital logic to achieve the aim of improving the transmission rate of the digital signal, and carrying out abnormal monitoring on the data stream processing module through a monitoring module so as to timely feed back abnormal feedback when the data transmission is abnormal. According to the mode selection of the digital circuit, the application can transmit data signals with different channel numbers, has high signal transmission rate and meets the data conversion requirement of a high-speed digital-to-analog converter.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.
Claims (10)
1. A digital circuit for a multichannel JESD 204B receiver, comprising:
The starting module is used for generating a starting signal and carrying out information configuration on the digital circuit based on preset configuration information so as to start the digital circuit;
The data stream processing module is used for receiving a first preset multi-channel digital signal to be transmitted sent by a JESD 204B sending end, carrying out signal transmission on the digital signal to be transmitted based on a preset channel connection relation in the preset configuration information, carrying out signal synchronization processing on the transmitted digital signal, and carrying out mapping output according to a working mode in the preset configuration information to obtain a second preset multi-channel digital signal;
The signal transmission rate of the output end of the data stream processing module is matched with the signal transmission rate of the input end of the data stream processing module.
2. A digital circuit at the receiving end of a multichannel JESD 204B according to claim 1, wherein said data stream processing module comprises:
the signal input unit is used for receiving the digital signals to be transmitted, respectively storing each digital signal to be transmitted, and transmitting the stored digital signals to output a plurality of first intermediate signals;
The data synchronization unit is used for respectively carrying out signal synchronization processing and data decoding on the plurality of first intermediate signals to obtain a plurality of second intermediate signals;
and the data output unit is used for mapping and transmitting a plurality of second intermediate signals based on the working mode in the preset configuration information to obtain the second preset multichannel digital signals.
3. A digital circuit at the receiving end of a multichannel JESD 204B according to claim 2, wherein said signal input unit comprises:
N input buffer subunits, which are used for receiving and buffering the digital signal to be transmitted of the first preset multi-channel sent by the JESD 204B sending end, and correlating the digital signal to be transmitted with the internal clock signal in the starting signal;
The data routing subunit is used for carrying out signal transmission on the data of each input cache subunit according to a preset channel connection relation in the preset configuration information, and outputting a plurality of first intermediate signals;
wherein N is more than or equal to 2, and N corresponds to the number of channels.
4. A digital circuit at the receiving end of a multichannel JESD 204B according to claim 3, wherein said data synchronization unit comprises:
N code group synchronization sub-units, which are used for performing code group synchronization on the first intermediate signals of each channel based on multi-frame clock signals, and adjusting the state of the code group synchronization based on the decoding result so as to align the first intermediate signals of the multi-channels;
The N decoding subunits are used for respectively decoding the signals output by the N code group synchronous subunits to obtain the decoding result;
And the N initial channel synchronization subunits are used for respectively carrying out initial channel synchronization on the signals output by the N decoding subunits and aligning the boundaries of multi-frame clocks to obtain N second intermediate signals.
5. A digital circuit at the receiving end of a multichannel JESD 204B according to claim 2, wherein said data output unit comprises:
N signal recovery subunits, which are used for descrambling and character replacement of the second intermediate signals of each channel respectively;
And the de-frame mapping subunit is used for carrying out corresponding mapping on the signals output by the N signal recovery subunits based on the working mode to obtain the digital signals of the second preset multiple channels.
6. A digital circuit at the receiving end of a multichannel JESD 204B as claimed in claim 4, wherein said start-up module comprises:
An information configuration unit, configured to receive the preset configuration information, and generate configuration information of each module of the digital circuit based on the preset configuration information;
A clock synchronization unit configured to generate the internal clock signal and the multi-frame clock signal based on the external clock signal, a plurality of divided signals, and a plurality of sampling signals;
wherein phases of the plurality of sampling signals are different.
7. A digital circuit at the receiving end of a multichannel JESD 204B according to claim 6, wherein said information configuration unit comprises:
a receiving subunit, configured to receive the preset configuration information;
a storage subunit, configured to store the preset configuration information;
And the analysis subunit is used for analyzing the preset configuration information in the storage subunit to obtain the configuration information of each module.
8. A digital circuit at the receiving end of a multichannel JESD 204B according to claim 6, wherein said clock synchronization unit comprises:
the synchronous regulation subunit is used for determining the phase relation between the analog sampling signals in the analog circuit and the frequency division signals according to the sampling signals, generating a delay signal and a clock reset signal, and transmitting the delay signal to the analog circuit so as to carry out multi-chip clock synchronous regulation;
A clock resetting subunit, configured to receive the external clock signal, set an internal clock signal of the digital circuit according to the external clock signal and the clock resetting signal, and generate a corresponding multi-frame clock signal based on the working mode;
And the boundary adjusting subunit is used for communicating with the JESD 204B transmitting end, and synchronizing the edges of the multi-frame clock signals so as to pull up or pull down the boundaries of the multi-frame clock signals.
9. A digital circuit at the receiving end of a multichannel JESD 204B as claimed in claim 4, further comprising a monitoring module for monitoring anomalies of said data stream processing module.
10. A digital circuit at the receiving end of a multichannel JESD 204B according to claim 9, wherein said monitoring module comprises:
the monitoring unit is used for carrying out abnormality monitoring on the digital circuit and counting abnormal conditions;
And the data stream verification unit is used for carrying out data verification on the digital signal to be transmitted of the signal input unit based on the verification code, and analyzing and verifying the configuration information of the initial channel synchronization subunit.
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