CN119450902A - Circuit board structure containing metal materials with different thermal expansion coefficients and manufacturing method thereof - Google Patents

Circuit board structure containing metal materials with different thermal expansion coefficients and manufacturing method thereof Download PDF

Info

Publication number
CN119450902A
CN119450902A CN202310959141.5A CN202310959141A CN119450902A CN 119450902 A CN119450902 A CN 119450902A CN 202310959141 A CN202310959141 A CN 202310959141A CN 119450902 A CN119450902 A CN 119450902A
Authority
CN
China
Prior art keywords
metal material
thermal expansion
circuit board
board structure
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310959141.5A
Other languages
Chinese (zh)
Inventor
洪立群
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tong Hsing Electronic Industries Ltd
Original Assignee
Tong Hsing Electronic Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tong Hsing Electronic Industries Ltd filed Critical Tong Hsing Electronic Industries Ltd
Priority to CN202310959141.5A priority Critical patent/CN119450902A/en
Publication of CN119450902A publication Critical patent/CN119450902A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

本申请公开一种包含不同热膨胀系数金属材料的电路板结构及其制造方法。电路板结构包含核心基板层、形成于核心基板层上的第一线路层以及形成于第一线路层上的绝缘介电层。绝缘介电层内侧形成有讯号导通孔。电路板结构进一步包含形成于讯号导通孔内的第一金属材料及第二金属材料。其中，第一金属材料形成于所述第一线路层上，且第二金属材料形成于第一金属材料上。第一金属材料具有一第一热膨胀系数，第二金属材料具有一第二热膨胀系数，且所述第二热膨胀系数大于所述第一热膨胀系数。因此，能防止当电路板的孔(Via)发生断裂时，还可以维持讯号连接。

The present application discloses a circuit board structure including metal materials with different thermal expansion coefficients and a manufacturing method thereof. The circuit board structure includes a core substrate layer, a first circuit layer formed on the core substrate layer, and an insulating dielectric layer formed on the first circuit layer. A signal via is formed on the inner side of the insulating dielectric layer. The circuit board structure further includes a first metal material and a second metal material formed in the signal via. The first metal material is formed on the first circuit layer, and the second metal material is formed on the first metal material. The first metal material has a first thermal expansion coefficient, the second metal material has a second thermal expansion coefficient, and the second thermal expansion coefficient is greater than the first thermal expansion coefficient. Therefore, when the via of the circuit board is prevented from breaking, the signal connection can also be maintained.

Description

Circuit board structure containing metal materials with different coefficients of thermal expansion and manufacturing method thereof
Technical Field
The present application relates to circuit board structures, and more particularly, to a circuit board structure including metal materials with different coefficients of thermal expansion and a method for manufacturing the same.
Background
As shown in fig. 1, in the prior art, two adjacent layers of wires L in the circuit board E may be connected to each other by, for example, via holes Via and metal material M (e.g., copper) filled therein. In the process of Via Via, the metal material M is filled in the Via hole mainly by a Via filling electroplating process. The surface to be plated in the circuit board E is generally cleaned before plating, so as to ensure that the plating quality meets the requirements. As shown in fig. 2, if the surface to be electroplated of the circuit board E is not cleaned sufficiently, the finally formed circuit board E may be heated during the subsequent operation process, so that the interface fracture C occurs at the interface between the metal material M in the Via hole Via and the circuit L or the copper layer, and the electrical signal cannot be transmitted between the two adjacent layers of circuit L. Accordingly, the product of the circuit board E may be determined to be functional failure due to signal disconnection.
The inventors of the present application have made intensive studies and have made an application in combination with the theory that the above-mentioned drawbacks are felt to be improved, and finally, have proposed a method for improving the above-mentioned drawbacks effectively and reasonably.
Disclosure of Invention
The application provides a circuit board structure containing metal materials with different thermal expansion coefficients, which is used for effectively improving the defects possibly generated by the prior torsion plate.
The application discloses a circuit board structure containing metal materials with different thermal expansion coefficients, which comprises a core substrate layer, a first circuit layer formed on the core substrate layer, an insulating dielectric layer formed on the first circuit layer, a first metal material formed in the signal through hole and formed on the first circuit layer, and a second metal material formed in the signal through hole and formed on the first metal material, wherein the first metal material has a first thermal expansion coefficient, the second metal material has a second thermal expansion coefficient, and the second thermal expansion coefficient is larger than the first thermal expansion coefficient.
Optionally, when the circuit board structure is subjected to a high temperature operation, the volume expansion rate of the second metal material is greater than the volume expansion rate of the first metal material, so that the second metal material generates an extrusion stress in a direction towards the first metal material, and the first metal material can continuously contact with the first circuit layer through extrusion of the second metal material, and maintain electrical connection.
Optionally, in the signal via, the first metal material has a first thickness, the second metal material has a second thickness, and the second thickness of the second metal material is greater than the first thickness of the first metal material.
Optionally, the sum of the thicknesses of the first thickness and the second thickness is defined as a total thickness, the first thickness of the first metal material is 15% to 45% with respect to the total thickness, and the second thickness of the second metal material is 55% to 85% with respect to the total thickness.
Optionally, the first thermal expansion coefficient of the first metal material and the second thermal expansion coefficient of the second metal material are respectively between 10×10 -6/k@20 ℃, and a difference between the second thermal expansion coefficient and the first thermal expansion coefficient is not less than 1×10 -6/k@20 ℃.
Optionally, the circuit board structure further includes a second circuit layer formed on a surface of the insulating dielectric layer away from the first circuit layer, wherein the first circuit layer is connected with the first metal material, and the second circuit layer is connected with the second metal material.
Optionally, the first metal material has a base portion and a protruding portion formed on the base portion, and the width of the base portion is greater than the width of the protruding portion, so that the first metal material has a protruding structure.
Alternatively, the base portion is formed on the first circuit layer, and the protruding portion is embedded in the second metal material such that the first metal material is embedded in the second metal material.
Optionally, when the circuit board structure is cooled, the volume shrinkage rate of the first metal material is greater than the volume shrinkage rate of the second metal material, so that the base portion generates a bending stress in the direction of the protruding portion.
The application also discloses a manufacturing method of the circuit board structure, which comprises the steps of providing a core substrate layer, forming a first circuit layer on one side surface of the core substrate layer, forming an insulating dielectric layer on one side surface of the first circuit layer far away from the core substrate layer, forming a signal via hole on the inner side of the insulating dielectric layer and connected with the upper surface and the lower surface of the insulating dielectric layer, forming a first metal material in the signal via hole and formed on the first circuit layer, wherein the first metal material has a first thermal expansion coefficient, and forming a second metal material in the signal via hole and formed on the first metal material, wherein the second metal material has a second thermal expansion coefficient and is larger than the first thermal expansion coefficient.
In summary, the circuit board structure including metal materials with different thermal expansion coefficients and the method for manufacturing the same according to the present application can prevent the hole (Via) from breaking and maintain the signal connection through the stacking of the first metal material and the second metal material in the signal Via and the design of the thermal expansion coefficients.
For a further understanding of the nature and the technical aspects of the present application, reference should be made to the following detailed description of the application and the accompanying drawings, which are included to illustrate and not to limit the scope of the application.
Drawings
Fig. 1 is a schematic cross-sectional view of a circuit board structure in the prior art.
Fig. 2 is a schematic diagram of an interface fracture at the interface between a metal material and a copper layer in a via hole of a circuit board structure in the prior art.
Fig. 3 is a schematic cross-sectional view of a circuit board structure according to a first embodiment of the present application.
FIG. 4 is a schematic diagram illustrating a downward compressive stress generated by the second metal material of FIG. 1.
Fig. 5 is a schematic diagram of another variation of the circuit board structure of fig. 1.
Fig. 6 is a schematic cross-sectional view of a circuit board structure according to a second embodiment of the application.
Fig. 7 is a partial enlarged view of area VII in fig. 6.
FIG. 8 is a schematic view of the first metal material of FIG. 6 generating a bending stress inward.
Fig. 9 is a flowchart of a method for manufacturing a circuit board structure according to a third embodiment of the present application.
Detailed Description
The following embodiments of the present application are described in terms of specific examples, and those skilled in the art will appreciate the advantages and effects of the present application from the disclosure herein. The application is capable of other and different embodiments and its several details are capable of modifications and various other uses and applications, all of which are obvious from the description, without departing from the spirit of the application. The drawings of the present application are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present application in detail, but the disclosure is not intended to limit the scope of the present application.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or signal from another signal. In addition, the term "or" as used herein shall include any one or combination of more of the associated listed items as the case may be.
First embodiment
Referring to fig. 3 and 4, a circuit board structure 100 is provided according to a first embodiment of the present application, and in particular, a circuit board structure 100 including metal materials with different thermal expansion coefficients is provided, which can solve the problem in the prior art that electrical signals cannot be transmitted due to the breaking of the interface between the Via (Via) and the copper line layer.
To achieve the above objective, the circuit board structure 100 includes a core substrate layer 1, a first circuit layer 2 and an insulating dielectric layer 3. Wherein the first wiring layer 2 is formed on one side surface of the core substrate layer 1, and the insulating dielectric layer 3 is formed on one side surface of the first wiring layer 2 remote from the core substrate layer 1.
In this embodiment, the material of the core substrate layer 1 may be, for example, glass fiber cloth (e.g., FR-4), the first circuit layer 2 may be, for example, a copper circuit layer, and the material of the insulating dielectric layer 3 may be, for example, a semi-cured lamination sheet (e.g., prepreg, PP glue), but the application is not limited thereto.
Further, a signal via 4 is formed on the inner side of the insulating dielectric layer 3, and the signal via 4 is connected to the upper surface and the lower surface of the insulating dielectric layer 3 and corresponds in position to a portion of the first circuit layer 2. In the present embodiment, the signal via 4 is a laser drilled hole, and has a hole shape with a wide top and a narrow bottom, but the present application is not limited thereto.
Furthermore, the circuit board structure 100 is filled with a first metal material 41 and a second metal material 42 in sequence from the direction close to the first circuit layer 2 to the direction far from the first circuit layer 2 (or from the bottom to the top thereof) inside the signal via 4.
Alternatively, the first metal material 41 is formed in the hole of the signal via 4 and on the first circuit layer 2 to be directly connected to and in contact with the first circuit layer 2. In addition, the second metal material 42 is formed in the hole of the signal via 4, and is formed on a side surface of the first metal material 41 away from the first wiring layer 2, and is directly connected and contacted with the first metal material 41.
The first metal material 41 and the second metal material 42 may be formed by at least one of a metal plating process, an electroless plating process, a metal physical deposition process, and a metal chemical deposition process, respectively.
In the present embodiment, the first metal material 41 and the second metal material 42 are both in contact with the sidewall in the signal via 4 (as shown in fig. 3), but the present application is not limited thereto.
In another embodiment of the present application, as shown in fig. 5, the first metal material 41 may be formed on the first circuit layer 2 and cover all the sidewalls of the signal via 4 in an extending manner. And the second metal material 42 fills the remaining portion of the signal via 4 and is not in contact with the sidewall within the signal via 4.
With continued reference to fig. 3 and 4, further, the first metal material 41 has a first thermal expansion coefficient α1, and the second metal material 42 has a second thermal expansion coefficient α2. Wherein the second thermal expansion coefficient α2 of the second metal material 42 is larger than the first thermal expansion coefficient α1 of the first metal material 41.
Accordingly, as shown in fig. 4, when the circuit board structure 100 is subjected to a high temperature operation, the volume expansion rate of the second metal material 42 is greater than that of the first metal material 41, so that the second metal material 42 generates a compressive stress F1 toward the first metal material 41, and the first metal material 41 can continuously contact with the first circuit layer 2 through the compression of the second metal material 42 to maintain the electrical connection.
The high temperature operation may be, for example, high temperature Reflow (Reflow), but the present application is not limited thereto.
According to the above configuration, even though the interface between the first metal material 41 and the first circuit layer 2 is broken, the first metal material 41 is continuously connected to and contacted with the first circuit layer 2 by being pressed by the pressing stress F1. Accordingly, in the prior art, the problem that the electrical signal cannot be transmitted due to the fracture at the interface of the Via (Via) and the copper circuit layer can be effectively solved.
It should be noted that, the thermal expansion coefficient (Coefficient of Thermal Expansion, CTE) refers to the regularity coefficient that the geometric characteristics of the material change along with the rising and falling of the temperature under the action of thermal expansion and contraction effect. The coefficients of thermal expansion of the first and second metallic materials may employ a Coefficient of Linear Thermal Expansion (CLTE), but are not limited thereto.
It should be noted that, in some embodiments of the present application, the first metal material 41 and the second metal material 42 filled in the signal via 4 may be at least one selected from the group consisting of copper metal, silver metal, gold metal, zinc metal and aluminum metal, respectively, but the present application is not limited thereto.
In terms of the linear thermal expansion coefficient α, for example, the copper metal has a linear thermal expansion coefficient α of 16.5×10 -6/k@20 ℃. The linear thermal expansion coefficient alpha of the silver metal is 19.5 x 10 -6/K@20 ℃.
The linear thermal expansion coefficient alpha of the gold metal is 14.2 x 10 -6/K@20 ℃. And the linear thermal expansion coefficient alpha of the zinc metal is 36.0 x 10 -6/K@20 ℃. Further, the linear thermal expansion coefficient α of the aluminum metal is 23.0X10: 10 -6/K@20 ℃.
In some embodiments of the present application, the second metal material 42 may be, for example, copper metal (α2=16.5×10 -6/k@20 ℃), and the first metal material 41 may be, for example, gold metal (α1=20 ℃)
14.2 X 10 -6/k@20℃). Or the second metallic material 42 may be, for example, silver metal (α2=19.5×10 -6/k@20 ℃), and the first metallic material 41 may be, for example, copper metal (α2=16.5×10 -6/k@20 ℃).
It should be noted that, the second thermal expansion coefficients α2 of the second metal materials 42 in the above embodiment are all larger than the first thermal expansion coefficient α1 of the first metal material 41.
From another aspect, the first thermal expansion coefficient α1 of the first metal material 41 and the second thermal expansion coefficient α2 of the second metal material 42 are respectively in a range of 10 to 40×10 -6/k@20 ℃.
Further, a difference between the second thermal expansion coefficient α2 of the second metal material 42 and the first thermal expansion coefficient α1 of the first metal material 41 is not less than 1×10 -6/k@20 ℃, and preferably not less than 2×10 -6/k@20 ℃.
However, it should be noted that the above embodiments are merely exemplary, and the present application is not limited to the above embodiments.
With continued reference to fig. 3 and 4, in the signal via 4, the first metal material 41 has a first thickness T1, and the second metal material 42 has a second thickness T2. Wherein, the second thickness T2 of the second metal material 42 is greater than the first thickness T1 of the first metal material 41.
In some embodiments of the application, the sum of the thicknesses of the first thickness T1 and the second thickness T2 is defined as the total thickness. The first thickness T1 of the first metal material 41 is 15% to 45%, and preferably 20% to 40% in proportion to the total thickness. Further, the second thickness T2 of the second metal material 42 is 55% to 85%, and preferably 60% to 80% with respect to the total thickness.
Based on the above thickness ratio, the second metal material 42 can generate more sufficient compressive stress F1 on the first metal material 41 during high temperature operation, so that the first metal material 41 is continuously in contact with the first circuit layer 2 for electrical connection.
Further, in the present embodiment, the circuit board structure 100 further includes a second circuit layer 5, and the second circuit layer 5 is formed on a surface of the insulating dielectric layer 3, which is far from the first circuit layer 2. From another perspective, the first wiring layer 2 and the second wiring layer 5 are respectively formed on two opposite side surfaces of the insulating dielectric layer 3. Wherein the first wiring layer 2 is connected to the first metal material 41, and the second wiring layer 5 is connected to the second metal material 42.
In an embodiment of the application, the first circuit layer 2 and the first metal material 41 may be formed separately in different electroplating processes or metal deposition processes, and the second circuit layer 5 may be formed in the same electroplating process or metal deposition process as the second metal material 42, but the application is not limited thereto.
Second embodiment
Referring to fig. 6 to 8, a circuit board structure 100' is further provided according to a second embodiment of the present application. The circuit board structure 100' includes a core substrate layer 1, a first circuit layer 2, an insulating dielectric layer 3, and a second circuit layer 5. Wherein the first circuit layer 2 is formed on a side surface of the core substrate layer 1, the insulating dielectric layer 3 is formed on a side surface of the first circuit layer 2 away from the core substrate layer 1, and the second circuit layer 5 is formed on a side surface of the insulating dielectric layer 3 away from the first circuit layer 2.
A signal via 4 is formed inside the insulating dielectric layer 3, and the signal via 4 is connected to the upper surface and the lower surface of the insulating dielectric layer 3. The signal via 4 is sequentially filled with a first metal material 41 and a second metal material 42, the first metal material 41 is formed on the first circuit layer 2, and the second metal material 42 is formed on the first metal material 41. The first metal material 41 has a first thermal expansion coefficient α1, the second metal material 42 has a second thermal expansion coefficient α2, and the second thermal expansion coefficient α2 is greater than the first thermal expansion coefficient α1. The first metal material 41 is connected to the first circuit layer 2, and the second metal material 42 is connected to the second circuit layer 5, so that the first circuit layer 2 is electrically connected to the second circuit layer 5.
The circuit board structure 100' according to the second embodiment of the present application is substantially the same as the circuit board structure 100 of the first embodiment, and is mainly different in that the first metal material 41 in the second embodiment of the present application further has a base portion 411 and a protruding portion 412 formed on the base portion 411. Wherein, the width of the base 411 is larger than the width of the protrusion 412, so that the second metal material 42 has a convex structure.
Further, the base portion 411 is formed on the first wiring layer 2 to be directly connected to and in contact with the first wiring layer 2. The protrusion 412 is embedded in the second metal material 42, so that the first metal material 41 is embedded in the second metal material 42. Accordingly, the contact area between the first and second metal materials 41 and 42 can be increased to effectively increase the bonding between heterogeneous materials.
Similar to the first embodiment, when the circuit board structure 100' is subjected to a high temperature operation, the volume expansion rate of the second metal material 42 is larger than that of the first metal material 41, so that the second metal material 42 generates a compressive stress F1 toward the first metal material 41, and the first metal material 41 can be continuously contacted with the first circuit layer 2 by the compression of the second metal material 42 to maintain the electrical connection.
Further, when the circuit board structure 100' is cooled by the high temperature operation, the volume shrinkage rate of the first metal material 41 is larger than the volume shrinkage rate of the second metal material 42, so that the base portion 411 generates a bending stress F2 (as shown in fig. 8) towards the protruding portion 412, thereby generating a tighter bond between the first metal material 41 and the second metal material 42 and contacting the first circuit layer 2 downward to maintain the electrical connection.
According to the above configuration, the first metal material 41 is continuously connected to and contacted with the first circuit layer 2, although there is a case where an interface fracture occurs at the interface of the first metal material 41 and the first circuit layer 2. Accordingly, in the prior art, the problem that the electrical signal cannot be transmitted due to the fracture at the interface of the Via (Via) and the copper circuit layer can be effectively solved.
Third embodiment
The structural features and material features of the circuit board structures 100, 100' according to the embodiments of the present application are described above, and the manufacturing method of the circuit board structures according to the embodiments of the present application will be described below. As shown in fig. 9, the method for manufacturing the circuit board structure includes steps S110 to S160.
It should be noted that the order and the actual operation mode of the steps carried by the present embodiment may be adjusted according to the requirements, and are not limited to the steps carried by the present embodiment.
The step S110 includes providing a core substrate layer 1. The step S120 includes forming a first circuit layer 2 on a side surface of the core substrate layer 1.
The step S130 includes forming an insulating dielectric layer 3 on a surface of the first circuit layer 2 away from the core substrate layer 1.
The step S140 includes forming a signal via 4 inside the insulating dielectric layer 3, where the signal via 4 is connected to the upper surface and the lower surface of the insulating dielectric layer 3 and corresponds in position to a portion of the first circuit layer 2.
The step S150 includes forming a first metal material 41 in the signal via 4 and on the first circuit layer 2 to be directly connected to and in contact with the first circuit layer 2. The first metal material 41 may have a flat layered shape as shown in fig. 3, or the first metal material 41 may have a convex shape as shown in fig. 6. Wherein the first metal material 41 has a first thermal expansion coefficient α1.
The step S160 includes forming a second metal material 42 in the signal via 4 and on the first metal material 41 to be directly connected and contacted with the first metal material 41. The second metal material 42 has a second thermal expansion coefficient α2, and the second thermal expansion coefficient α2 of the second metal material 42 is greater than the first thermal expansion coefficient α1 of the first metal material 41.
In some embodiments of the present application, the first metal material 41 and the second metal material 42 may be formed in the signal via 4 by at least one of a metal plating process, an electroless plating process, a metal physical deposition process, and a metal chemical deposition process, respectively.
Advantageous effects of the invention
The circuit board structure comprising metal materials with different coefficients of thermal expansion and the manufacturing method thereof can prevent the hole (Via) from breaking and maintain signal connection through the stacking of the first metal material and the second metal material in the signal Via hole and the design of the coefficients of thermal expansion.
The above disclosure is only a preferred embodiment of the present application and is not intended to limit the scope of the present application, so that all equivalent technical changes made by the specification and drawings of the present application are included in the scope of the present application.

Claims (10)

1.一种包含有不同热膨胀系数金属材料的电路板结构，其特征在于，所述电路板结构包括：1. A circuit board structure comprising metal materials with different thermal expansion coefficients, characterized in that the circuit board structure comprises: 一核心基板层；a core substrate layer; 一第一线路层，形成于所述核心基板层上；A first circuit layer formed on the core substrate layer; 一绝缘介电层，形成于所述第一线路层上；其中，所述绝缘介电层的内侧形成有一讯号导通孔；An insulating dielectric layer is formed on the first circuit layer; wherein a signal via hole is formed inside the insulating dielectric layer; 一第一金属材料，形成于所述讯号导通孔内、且形成于所述第一线路层上；以及a first metal material formed in the signal via hole and on the first circuit layer; and 一第二金属材料，形成于所述讯号导通孔内、且形成于所述第一金属材料上；a second metal material formed in the signal via hole and formed on the first metal material; 其中，所述第一金属材料具有一第一热膨胀系数，所述第二金属材料具有一第二热膨胀系数，且所述第二热膨胀系数大于所述第一热膨胀系数。The first metal material has a first thermal expansion coefficient, the second metal material has a second thermal expansion coefficient, and the second thermal expansion coefficient is greater than the first thermal expansion coefficient. 2.根据权利要求1所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，当所述电路板结构经历一高温作业时，所述第二金属材料的体积膨胀率大于所述第一金属材料的体积膨胀率，以使得所述第二金属材料朝着所述第一金属材料的方向产生一挤压应力，且所述第一金属材料能通过所述第二金属材料的挤压、而持续地与所述第一线路层接触，并维持电性连接。2. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 1 is characterized in that, when the circuit board structure undergoes a high-temperature operation, the volume expansion rate of the second metal material is greater than the volume expansion rate of the first metal material, so that the second metal material generates an extrusion stress in the direction of the first metal material, and the first metal material can continuously contact the first circuit layer and maintain electrical connection through the extrusion of the second metal material. 3.根据权利要求1所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，于所述讯号导通孔中，所述第一金属材料具有一第一厚度，所述第二金属材料具有一第二厚度，并且所述第二金属材料的所述第二厚度大于所述第一金属材料的所述第一厚度。3. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 1, characterized in that, in the signal via hole, the first metal material has a first thickness, the second metal material has a second thickness, and the second thickness of the second metal material is greater than the first thickness of the first metal material. 4.根据权利要求3所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，所述第一厚度与所述第二厚度的厚度加总定义为总厚度，所述第一金属材料的所述第一厚度相对于所述总厚度的占比为15％至45％，且所述第二金属材料的所述第二厚度相对于所述总厚度的占比为55％至85％。4. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 3 is characterized in that the sum of the thickness of the first thickness and the second thickness is defined as the total thickness, the first thickness of the first metal material accounts for 15% to 45% of the total thickness, and the second thickness of the second metal material accounts for 55% to 85% of the total thickness. 5.根据权利要求1所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，所述第一金属材料的所述第一热膨胀系数以及所述第二金属材料的所述第二热膨胀系数分别介于10至40*10-6/K@20℃，且所述第二热膨胀系数与所述第一热膨胀系数间的一差值不小于1*10-6/K@20℃。5. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 1, wherein the first thermal expansion coefficient of the first metal material and the second thermal expansion coefficient of the second metal material are respectively between 10 and 40*10 -6 /K@20°C, and a difference between the second thermal expansion coefficient and the first thermal expansion coefficient is not less than 1*10 -6 /K@20°C. 6.根据权利要求1所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，所述的包含有不同热膨胀系数金属材料的电路板结构进一步包含一第二线路层，其形成于所述绝缘介电层远离于所述第一线路层的一侧表面上；其中，所述第一线路层与所述第一金属材料相连接，并且所述第二线路层与所述第二金属材料相连接。6. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 1 is characterized in that the circuit board structure comprising metal materials with different thermal expansion coefficients further comprises a second circuit layer formed on a surface of the insulating dielectric layer on one side away from the first circuit layer; wherein the first circuit layer is connected to the first metal material, and the second circuit layer is connected to the second metal material. 7.根据权利要求1所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，所述第一金属材料具有一基底部及形成于所述基底部上的一凸出部，且所述基底部的宽度大于所述凸出部的宽度，以使所述第一金属材料呈现凸字型结构。7. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 1 is characterized in that the first metal material has a base portion and a protrusion formed on the base portion, and the width of the base portion is greater than the width of the protrusion, so that the first metal material presents a convex structure. 8.根据权利要求7所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，所述基底部形成于所述第一线路层上，且所述凸出部被包埋于所述第二金属材料中，以使得所述第一金属材料嵌合于所述第二金属材料。8. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 7, wherein the base portion is formed on the first circuit layer, and the protrusion is embedded in the second metal material so that the first metal material is embedded in the second metal material. 9.根据权利要求8所述的包含有不同热膨胀系数金属材料的电路板结构，其特征在于，当所述电路板结构降温时，所述第一金属材料的体积收缩率大于所述第二金属材料的体积收缩率，使所述基底部朝所述凸出部的方向产生一弯曲应力。9. The circuit board structure comprising metal materials with different thermal expansion coefficients according to claim 8 is characterized in that when the circuit board structure is cooled down, the volume shrinkage rate of the first metal material is greater than the volume shrinkage rate of the second metal material, so that a bending stress is generated in the base portion toward the protrusion. 10.一种电路板结构的制造方法，其特征在于，所述电路板结构的制造方法包括：10. A method for manufacturing a circuit board structure, characterized in that the method for manufacturing a circuit board structure comprises: 提供一核心基板层；Providing a core substrate layer; 形成一第一线路层于所述核心基板层的一侧表面上；Forming a first circuit layer on a surface of one side of the core substrate layer; 形成一绝缘介电层于所述第一线路层远离于所述核心基板层的一侧表面上；forming an insulating dielectric layer on a surface of the first circuit layer away from the core substrate layer; 形成一讯号导通孔于所述绝缘介电层的内侧，并且所述讯号导通孔连接于所述绝缘介电层的上表面及下表面；Forming a signal via hole inside the insulating dielectric layer, and the signal via hole is connected to the upper surface and the lower surface of the insulating dielectric layer; 形成一第一金属材料于所述讯号导通孔内、并且形成于所述第一线路层上；forming a first metal material in the signal via hole and on the first circuit layer; 其中，所述第一金属材料具有一第一热膨胀系数；以及Wherein, the first metal material has a first thermal expansion coefficient; and 形成一第二金属材料于所述讯号导通孔内、并且形成于所述第一金属材料上；其中，所述第二金属材料具有一第二热膨胀系数，且所述第二热膨胀系数大于所述第一热膨胀系数。A second metal material is formed in the signal via hole and on the first metal material; wherein the second metal material has a second thermal expansion coefficient, and the second thermal expansion coefficient is greater than the first thermal expansion coefficient.
CN202310959141.5A 2023-08-01 2023-08-01 Circuit board structure containing metal materials with different thermal expansion coefficients and manufacturing method thereof Pending CN119450902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310959141.5A CN119450902A (en) 2023-08-01 2023-08-01 Circuit board structure containing metal materials with different thermal expansion coefficients and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310959141.5A CN119450902A (en) 2023-08-01 2023-08-01 Circuit board structure containing metal materials with different thermal expansion coefficients and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN119450902A true CN119450902A (en) 2025-02-14

Family

ID=94520374

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310959141.5A Pending CN119450902A (en) 2023-08-01 2023-08-01 Circuit board structure containing metal materials with different thermal expansion coefficients and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN119450902A (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001189536A (en) * 1999-12-28 2001-07-10 Hitachi Ltd Wiring board
CN1467831A (en) * 2002-05-27 2004-01-14 株式会社日立制作所 Multilayer circuit board, manufacturing process of multilayer circuit board, board for multilayer circuit, and electronic device
CN1901177A (en) * 2000-09-25 2007-01-24 揖斐电株式会社 Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
KR20090050660A (en) * 2007-11-16 2009-05-20 삼성전기주식회사 Multilayer Ceramic Substrate and Manufacturing Method
CN102349359A (en) * 2009-03-09 2012-02-08 株式会社村田制作所 Resin wiring board
CN111586972A (en) * 2015-07-31 2020-08-25 惠普发展公司，有限责任合伙企业 Printed circuit board to mold compound joint
CN113574974A (en) * 2020-01-31 2021-10-29 迅达科技公司 Printed circuit board assembly with engineered thermal path and method of manufacture
CN113853058A (en) * 2021-10-25 2021-12-28 深圳市宝明科技股份有限公司 A circuit board and method of making the same
CN114126206A (en) * 2021-11-27 2022-03-01 华为技术有限公司 Printed circuit board, manufacturing method thereof, board-level framework and electronic equipment
CN115621242A (en) * 2022-12-15 2023-01-17 北京唯捷创芯精测科技有限责任公司 Substrate with low warpage stress, preparation method, packaging structure and electronic product

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001189536A (en) * 1999-12-28 2001-07-10 Hitachi Ltd Wiring board
CN1901177A (en) * 2000-09-25 2007-01-24 揖斐电株式会社 Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board
CN1467831A (en) * 2002-05-27 2004-01-14 株式会社日立制作所 Multilayer circuit board, manufacturing process of multilayer circuit board, board for multilayer circuit, and electronic device
KR20090050660A (en) * 2007-11-16 2009-05-20 삼성전기주식회사 Multilayer Ceramic Substrate and Manufacturing Method
CN102349359A (en) * 2009-03-09 2012-02-08 株式会社村田制作所 Resin wiring board
CN111586972A (en) * 2015-07-31 2020-08-25 惠普发展公司，有限责任合伙企业 Printed circuit board to mold compound joint
CN113574974A (en) * 2020-01-31 2021-10-29 迅达科技公司 Printed circuit board assembly with engineered thermal path and method of manufacture
CN113853058A (en) * 2021-10-25 2021-12-28 深圳市宝明科技股份有限公司 A circuit board and method of making the same
CN114126206A (en) * 2021-11-27 2022-03-01 华为技术有限公司 Printed circuit board, manufacturing method thereof, board-level framework and electronic equipment
CN115621242A (en) * 2022-12-15 2023-01-17 北京唯捷创芯精测科技有限责任公司 Substrate with low warpage stress, preparation method, packaging structure and electronic product

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
薛耀辉;蒋军彪;张辉;文昌秀;苏宗锋;崔晓霞;郭海涛;: "低膨胀β-锂霞石基复合材料的研究现状与进展", 材料导报, no. 05, 3 February 2020 (2020-02-03) *

Similar Documents

Publication Publication Date Title
JP5725962B2 (en) Wiring board manufacturing method and mounting structure manufacturing method thereof
US20100065318A1 (en) Circuit board and semiconductor element mounted structure using the same
WO1999037704A1 (en) Heat-resistant insulating film, raw substrate for printed wiring board using the same and method for producing the substrate
KR102117242B1 (en) Wiring substrate
JPS63259907A (en) Electric base body material
JP7011946B2 (en) Wiring board
JP2011049289A (en) Wiring board and manufacturing method thereof
CN119450902A (en) Circuit board structure containing metal materials with different thermal expansion coefficients and manufacturing method thereof
JP2010123829A (en) Printed wiring board and manufacturing method thereof
JP3921756B2 (en) Printed circuit board and manufacturing method thereof
TWI888876B (en) Circuit board structure including metallic materials with different thermal expansion coefficients and method for producing the same
JP2005050885A (en) Wiring board and manufacturing method thereof
US10134652B2 (en) Substrate for integrated circuit package
TWI622140B (en) Substrate for integrated circuit package
CN119384873A (en) Wiring substrate and mounting structure using the wiring substrate
KR102752220B1 (en) Wiring board
JP5207811B2 (en) Mounting structure and wiring board
KR20130001923A (en) Semi-additive flexible copper thin film laminated film and manufacturing method thereof
JP2012074687A (en) Manufacturing method of wiring board and manufacturing method of mounting structure thereof
US20120047731A1 (en) Method for Manufacturing Circuit Board and Method for Manufacturing Structure Using the Same
CN222531895U (en) A circuit board structure
KR101897015B1 (en) Manufacturing method of chip package member and manufacturing method of chip package
JP3817430B2 (en) Laminate for printed wiring boards
JP2000133942A (en) Multilayer printed wiring board
TWI647989B (en) Roll-to-roll processed flexible circuit board and quick method for forming the same

Legal Events

Date Code Title Description
PB01 Publication
SE01 Entry into force of request for substantive examination