CN119649727A - Display panel, display driving method and display device - Google Patents
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Abstract
本申请属于显示驱动技术领域，具体涉及一种显示面板、显示驱动方法和显示设备，该显示面板包括N行扫描线、M列数据线，以及N行×2M列像素电路；每个像素电路包括像素单元和控制单元，第n行控制单元的第一控制端与第n行扫描线相连，第2m‑1列控制单元的第二控制端、第2m‑1列控制单元的输入端、第2m列控制单元的第二控制端和第2m列控制单元的输入端均与第m列数据线相连；在第n行扫描线开启时，第m列数据线上的数据信号控制第n行第2m‑1列控制单元和第n行第2m列控制单元任意一个导通或分时交替导通；本申请在同等分辨率的显示条件下使数据线的数量减少一半，不仅降低了面板的功耗和成本，还提高了刷新率和开口率。
The present application belongs to the field of display driving technology, and specifically relates to a display panel, a display driving method and a display device, wherein the display panel comprises N rows of scan lines, M columns of data lines, and N rows×2M columns of pixel circuits; each pixel circuit comprises a pixel unit and a control unit, a first control end of the n-th row control unit is connected to the n-th row of scan lines, a second control end of the 2m‑1-th column control unit, an input end of the 2m‑1-th column control unit, a second control end of the 2m‑2m column control unit and an input end of the 2m column control unit are all connected to the m-th column of data lines; when the n-th row of scan lines is turned on, a data signal on the m-th column of data lines controls any one of the n-th row of 2m‑1-th column control unit and the n-th row of 2m column control unit to be turned on or to be turned on alternately in time-sharing; the present application reduces the number of data lines by half under display conditions of the same resolution, which not only reduces the power consumption and cost of the panel, but also improves the refresh rate and aperture ratio.
Description
Technical Field
The disclosure belongs to the technical field of display driving, and particularly relates to a display panel, a display driving method and display equipment.
Background
In the prior art, a matrix-arranged pixel unit is arranged in a display panel, each pixel unit needs a data line for providing data signals and a scanning line for controlling the pixel unit to be turned on or off, along with the continuous updating and iteration of the display technology, a high-resolution panel gradually becomes a main stream product in the market, and the high-resolution means that more data lines and scanning lines are needed, so that RC Loading (resistance-capacitance load, abbreviated as resistance-capacitance load) of the display panel is continuously increased, and the problem of high power consumption of the display panel is caused.
It can be seen that how to reduce the power consumption of the display panel is a current problem to be solved.
Disclosure of Invention
The application provides a display panel, a display driving method and a display device, which solve the problem of high power consumption of the display panel, the application reduces the number of the data lines by half under the display condition of the same resolution, thereby not only reducing the power consumption and the cost of the panel, but also improving the refresh rate and the aperture opening ratio.
The first aspect provides a display panel which comprises N rows of scanning lines, M columns of data lines and N rows of x 2M columns of pixel circuits, wherein each pixel circuit comprises a pixel unit and a control unit, the control units are used for charging the pixel units through data signals on the data lines when the pixel circuits are in a conducting state, each control unit comprises a first control end, a second control end, an input end and an output end, the first control end of each N row of control units is connected with the N rows of scanning lines, the second control end of each 2M-1 column of control units, the input end of each 2M-1 column of control units, the second control end of each 2M-1 column of control units and the input end of each 2M-th column of control units are connected with the M-th column of data lines, when the N rows of scanning lines are on, the data signals on the M-th data lines control the N rows of control units and the N rows of control units, the N rows of control units and the N rows of control units are conducted alternately or the N rows of control units are conducted alternately, and the N rows of control units are conducted alternately in the order of 1, and N is equal to 1.
Optionally, the control unit comprises a first switching tube, a second switching tube and a second switching tube, wherein the control end of the first switching tube is connected with the data line, the first end of the first switching tube is connected with the scanning line, the control end of the second switching tube is connected with the second end of the first switching tube, the first end of the second switching tube is connected with the data line, the second end of the second switching tube is connected with the pixel unit, and the opening voltages of the first switching tube of the nth row and the 2m-1 th column control unit and the first switching tube of the nth row and the 2 m-th column control unit are opposite.
Optionally, the odd-numbered line scanning lines of the current frame are in an on state, and corresponding first data signals and second data signals are alternately output by each column of data lines in an on time period of the odd-numbered line scanning lines of the current frame, or the even-numbered line scanning lines of the current frame are in an on state, and corresponding first data signals and second data signals are alternately output by each column of data lines in an on time period of the even-numbered line scanning lines of the current frame, wherein the polarities of the first data signals and the second data signals are opposite.
Alternatively, each column of data lines alternately outputs corresponding first data signals and second data signals in an n-th row scanning line on period of a current frame, wherein polarities of the first data signals and the second data signals are opposite;
Optionally, each column of data lines outputs a corresponding first data signal in an n-th row scan line on period of the current frame.
Optionally, the mth column data line outputs a first data signal in the nth row scan line on period of the current frame, and the mth column data line outputs a second data signal in the (n+1) th row scan line on period, wherein the polarities of the first data signal and the second data signal are opposite.
Optionally, the 3i+1 column pixel unit is a first color sub-pixel, the 3i+2 column pixel unit is a second color sub-pixel, and the 3i+3 column pixel unit is a third color sub-pixel, wherein i= [0,1, 2..OtherwiseRepresentation ofThe result of (2) is rounded down;
Optionally, the 3j+1-th row of pixel units is a first color sub-pixel, the 3j+2-th row of pixel units is a second color sub-pixel, and the 3j+3-th row of pixel units is a third color sub-pixel, wherein j= [0,1, 2.. OtherwiseRepresentation ofThe result of (2) is rounded down.
Optionally, the pixel unit includes a liquid crystal capacitor, and a pixel electrode of the liquid crystal capacitor is connected with an output end of the control unit;
Optionally, the pixel unit comprises a storage capacitor, a driving transistor and a light emitting diode, wherein a first end of the storage capacitor is connected with an output end of the control unit, a second end of the storage capacitor is connected with a power end, a control end of the driving transistor is connected with the first end of the storage capacitor, the first end of the driving transistor is connected with the second end of the storage capacitor, an anode of the light emitting diode is connected with the second end of the driving transistor, and a cathode of the light emitting diode is grounded.
The second aspect of the application provides a display driving method, which comprises the steps of obtaining a first target conduction polarity corresponding to a first control end of each control unit and a second target conduction polarity corresponding to a second control end of each control unit in the display panel, and generating a scanning signal corresponding to each row of scanning lines and a data signal corresponding to each column of data lines according to all the first target conduction polarities, all the second target conduction polarities and a display picture of a current frame, so that when an nth row of scanning lines are started, the data signals on an mth column of data lines control any one of the nth row, the mth column and the mth column of control units to be conducted or alternately conducted in a time sharing mode.
In a third aspect, the application provides a display device comprising a gate driving circuit for outputting a scanning signal, a source driving circuit for outputting a data signal, and a display panel, wherein scanning lines of the display panel are connected with the gate driving circuit, and data lines of the display panel are connected with the source driving circuit.
The technical scheme provided by the application has at least the following beneficial effects:
1. According to the application, two adjacent rows of pixel circuits share one scanning line, two adjacent columns of pixel circuits share the same data line, and the pixel circuits connected to the same scanning line and the same data line are controlled by the data line and the scanning line not to be opened simultaneously, so that the number of the scanning lines and the number of the data lines are reduced by at least half under the display condition of the same resolution, and the number of the scanning lines and the number of the data lines in the panel are reduced along with the reduction of RC Loading on the scanning lines and the data lines in the panel, thereby greatly reducing the power consumption of the display panel.
2. According to the application, by reducing half of the scanning lines and half of the data lines, the manufacturing cost of the display panel is reduced, and the refresh rate and the opening rate of the panel are improved, so that the market competitiveness of the product is improved.
3. Because the RC loading value of the display panel is in direct proportion to the noise value, the application can reduce panel noise and improve display accuracy while reducing the panel RC Loading.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.
Fig. 2 is a schematic circuit diagram of a first pixel circuit according to an embodiment of the application.
Fig. 3 is a schematic circuit diagram of a second pixel circuit according to an embodiment of the application.
Fig. 4 is a schematic flow chart of a display driving method according to an embodiment of the application.
Fig. 5 is a schematic diagram of a first display screen and waveforms according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a second display screen and waveforms according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a third display screen and waveforms according to an embodiment of the present application.
Fig. 8 is a schematic diagram of a fourth display screen and waveforms according to an embodiment of the present application.
Fig. 9 is a schematic diagram of a pixel architecture of a display panel according to an embodiment of the application.
Reference numerals illustrate:
100. display panel, 110, scanning line, 120, data line, 130, pixel circuit, 131, control unit, 132, pixel unit;
t0, a driving transistor, T1, a first switching tube, T2, a second switching tube, T3, a third switching tube, cc, a storage capacitor, cs, a pixel capacitor, ct, a storage capacitor, an OLED and a light emitting diode.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many different forms and should not be construed as limited to the examples set forth herein, but rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
The application will be described in further detail with reference to the drawings and the specific examples. It should be noted that the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application, and as shown in fig. 1, the display panel 100 includes N rows of scan lines 110, M columns of data lines 120, and pixel circuits 130 arranged in an array, where the number of columns of the pixel circuits 130 is 2M columns and the number of rows is N, that is, the number of columns of the pixel circuits 130 in the display panel 100 is 2 times that of the data lines 120. Wherein the scan lines 110 and the data lines 120 in fig. 1 cross but are not connected, G1, G2, G3, G4, and GN in fig. 1 represent a first row scan line, a second row scan line, a third row scan line, a fourth row scan line, and an nth row scan line, respectively, and S1 and SM represent a first column data line and an mth column data line, respectively.
In an embodiment, each pixel circuit 130 includes a pixel unit 132 and a control unit 131, the control unit 131 is configured to input a data signal on the data line 120 into the pixel unit 132 when in a conductive state, so as to charge the pixel unit 132 through the data signal on the data line 120, conversely, when the control unit 131 is in a non-conductive state (i.e., in a disconnected state), the data signal on the data line 120 cannot be input into the pixel unit 132, so as not to charge the pixel unit 132, and the display panel 100 may be a Liquid Crystal Display (LCD) or an OLED (Organic Light-Emitting Diode) display, and when the display panel 100 is a Liquid crystal display, the pixel unit 132 includes Liquid crystal molecules, and when the display panel 100 is an OLED display, the pixel unit 132 includes Light Emitting diodes.
As shown in FIG. 1, the control unit 131 includes a first control end K1, a second control end K2, an input end Vi and an output end Vo, the first control end K1 of the nth row control unit 131 is connected with the nth row scanning line 110, the second control end K2 of the 2m-1 th column control unit 131, the input end Vi of the 2m-1 th column control unit 131, the second control end K2 of the 2 m-th column control unit 131 and the input end Vi of the 2 m-th column control unit 131 are connected with the mth column data line, and the output end Vo of each control unit 131 is connected with the input end of the corresponding pixel unit 132.
It should be noted that N and M in the present embodiment are variables, N and M are constants, the range of the variable N is 1 to N, the range of the variable M is 1 to M, N and M are positive integers greater than 1, in addition, the control units 131 of two adjacent columns in the present embodiment are connected to the same corresponding data line 120, the two adjacent columns refer to the 2M-1 th column and the 2M-th column, and the same corresponding data line 120 refers to the M-th column data line 120.
For example, when n=1, the first control ends K1 of the 1 st row control units 131 are all connected to the 1 st row scan line 110, when n=2, the first control ends K1 of the 2 nd row control units 131 are all connected to the 2 nd row scan line 110, and so on, when n=n, the first control ends K1 of the N-th row control units 131 are all connected to the N-th row scan line 110.
When m=1, the second control ends K2 of all control units 131 in column 1 and K2 of all control units in column 2 are connected to column 1 data line 120, and the input ends Vi of all control units 131 in column 1 and Vi of all control units 131 in column 2 are connected to column 1 data line 120, when m=2, the second control ends K2 of all control units 131 in column 3 and K2 of all control units in column 4 are connected to column 2 data line 120, and the input ends Vi of all control units 131 in column 3 and Vi of all control units 131 in column 4 are also connected to column 2 data line 120, and when m=m, the second control ends K2 of all control units 131 in column 2M-1 and K2 of all control units in column 2 are connected to column M data line 120, and the input ends Vi of all control units 131 in column 2M-1 and Vi of all control units 131 in column 2 are also connected to column 2 data line 120.
In the pixel circuit of the same row, the on-off states of the 2m-1 th column control unit 131 and the 2 m-th column control unit 131 at the same time are opposite, so that when the nth row scanning line is turned on, the data signal on the mth column data line 120 controls any one of the 2m-1 th column control unit 131 and the 2 m-th column control unit 131 of the nth row to be conducted or conducted alternately in a time sharing manner.
It should be noted that, in the present embodiment, the on-off state of the control unit 131 is controlled by the scan line 110 and the data line 120 through the first control end K1 and the second control end K2, and two adjacent rows of control units in the same row of pixel circuits are controlled by the same row of data lines; therefore, in this embodiment, the data signal on the mth column data line 120 may control the 2m-1 th column control unit 131 to be in a conducting state in the on period of the nth row scan line 110, the data signal on the mth column data line 120 may control the 2m column control unit 131 to be in a conducting state in the on period of the nth row scan line 110, and the data signal on the mth column data line 120 may control the 2m-1 th column control unit 131 and the 2m column control unit 131 to be alternately conducted in a time-sharing manner in the on period of the nth row scan line 110, where the time-sharing alternate conduction includes that the 2m-1 th column control unit 131 is conducted for a first time period and the 2m column control unit 131 is conducted for a second time period, or that the 2m column control unit 131 is conducted for the first time period and the 2m-1 th column control unit 131 is conducted for a second time period, and the sum of the first time period and the second time period is less than or equal to the on period of the nth row scan line 110.
In summary, the display panel provided by the embodiment has at least the following advantages:
1. the application uses two adjacent rows of pixel circuits to share the same data line, and uses the common control of the data line and the scanning line to prevent the two adjacent pixel circuits from being opened at the same time, and reduces the number of the data lines by half under the display condition of the same resolution, so that RC Loading on the data line in the panel is reduced, thereby greatly reducing the power consumption of the display panel.
2. According to the application, the manufacturing cost of the display panel is reduced by reducing half of the data lines, and the refresh rate and the opening rate of the panel are improved, so that the market competitiveness of the product is improved.
3. Because the RC loading value of the display panel is in direct proportion to the noise value, the application can reduce panel noise and improve display accuracy while reducing the panel RC Loading.
Fig. 2 is a circuit schematic diagram of a first pixel circuit provided in an embodiment of the present application, where, as shown in fig. 2, the control unit 131 includes a first switching tube T1 and a second switching tube T2, a control end of the first switching tube T1 is connected to the data line 120, a first end of the first switching tube T1 is connected to the scan line 110, a control end of the second switching tube T2 is connected to a second end of the first switching tube T1, a first end of the second switching tube T2 is connected to the data line 120, and a second end of the second switching tube T2 is connected to the pixel unit 132, where, an opening voltage of the first switching tube T1 of the nth row 2m-1 column control unit is opposite to an opening voltage of the first switching tube T1 of the nth row 2 m-th column control unit.
It should be noted that, the turn-on voltage of the first switch tube T1 of the nth row 2m-1 column control unit and the turn-on voltage of the first switch tube T1 of the nth row 2m column control unit are opposite, that is, the types of the first switch tube T1 between the two control units 131 connected to the same data line in the same row are different, that is, the first switch tube T1 of one control unit 131 is a P-type MOS tube, the first switch tube T1 of the other control unit 131 is an N-type MOS tube, for example, the first switch tube of the 1 st row 1 column control unit is an NMOS tube, the first switch tube of the 1 st row 2 column control unit is a PMOS tube, and the first switch tube of the 2 nd row 1 column control unit is a PMOS tube, so that one of the two control units 131 can be controlled to be in a conductive state by the data signal at the same time, thereby preventing the problem that the two pixel units are charged simultaneously.
The specific working principle of the control unit 131 in this embodiment is that, taking the first switching tube T1 as a P-type MOS tube and the second switching tube T2 as an N-type MOS tube as an example, when the data signal output by the mth column data line 120 is at a low level and the data signal output by the nth row data line 110 is at a high level, the first switching tube T1 is turned on, the second switching tube T2 is turned on by the high level on the nth row data line 110, so that the data signal output by the mth column data line 120 charges the pixel unit 132, conversely, when the data signal output by the mth column data line 120 is at a high level, the first switching tube T1 is turned off, the second switching tube T2 cannot be turned on no matter whether the data signal output by the nth row data line 110 is at a high level or a low level, so that the pixel unit 132 cannot be charged, in addition, when the mth column data line 120 outputs a low level, the first switching tube T1 and the second switching tube T2 are turned on, and when the first switching tube T1 and the second switching tube T2 are turned off, i.e., the first switching tube T131 and the second switching tube 131 are turned off, and the second switching tube 131 are in a state, and the first switching tube T2 is turned off.
According to the embodiment, the first switching tubes of different types are arranged between the two control units connected with the same data line in the same row of pixel circuits, so that one of the two adjacent control units can be controlled to be in a conducting state by the data signals and the scanning signals at the same moment, and the problem of wrong pixel charging is avoided.
It should be noted that the turn-on (turn-on) voltage of the switching tube formed by a-si (amorphous silicon) may be about 0.2V, and for the lowest gray scale display, the data voltage supplied by the data line 120 is generally not about 0V but about 0.3V, so that the first switching tube T1 may be turned on for the lowest gray scale display, and the scan line 110 may be turned on for about 20V, so that the first switching tube T1 enters the saturation region, and the voltage of the scan line 110 is applied to the gate of the second switching tube T2 through the first switching tube T1 to control the turn-on of the second switching tube T2.
In addition, the upper gray level voltage of the lowest gray level display is generally 0.5V, and other higher gray level voltages are sufficient to turn on the first switching tube T1, and the first switching tube T1 can be operated in the saturation region in cooperation with the voltage given by the scan line 110. Thus, the voltage on the data line 120 may remain 0V when the data voltage is not applied.
In one embodiment of the present application, as shown in fig. 2, the pixel unit 132 includes a storage capacitor Cc, a driving transistor T0, and a light emitting diode OLED, wherein a first terminal of the storage capacitor Cc is connected to the output terminal Vo of the control unit 131, a second terminal of the storage capacitor Cc is connected to the power terminal VDD, a control terminal of the driving transistor T0 is connected to the first terminal of the storage capacitor Cc, a first terminal of the driving transistor T0 is connected to the second terminal of the storage capacitor Cc, an anode of the light emitting diode OLED is connected to the second terminal of the driving transistor T0, and a cathode of the light emitting diode OLED is grounded VSS.
In this embodiment, when the control unit 131 is in the on state, the data signal on the data line 120 charges the storage capacitor Cc, and under the effect of the driving voltage output from the power supply end, the driving transistor T0 outputs the corresponding driving current to drive the light emitting diode OLED to emit light.
Fig. 3 is a circuit schematic diagram of a second pixel circuit according to an embodiment of the present application, as shown in fig. 4, a pixel unit 132 includes a liquid crystal capacitor Cs, a pixel electrode of the liquid crystal capacitor Cs is connected to an output end Vo of the control unit 131, where the liquid crystal capacitor Cs generally includes a pixel electrode, a common electrode, and liquid crystal molecules between the pixel electrode and the common electrode, and data signals with different magnitudes are applied to the pixel electrode to rotate the liquid crystal molecules to different angles, so as to realize brightness adjustment of the pixel unit 132.
In this embodiment, the pixel unit 132 further includes a storage capacitor Ct, where a pixel electrode of the storage capacitor Ct is connected to the output terminal Vo of the control unit 131, for realizing the maintenance of the charging voltage.
Fig. 4 is a schematic flow chart of a display driving method according to an embodiment of the present application, and as shown in fig. 5, the display driving method is applied to the display panel of the above embodiment, and specifically includes the following steps:
Step S100, acquiring a first target conduction polarity corresponding to a first control end of each control unit and a second target conduction polarity corresponding to a second control end of each control unit in the display panel.
In this embodiment, the first target conduction polarity indicates a voltage polarity for conducting the second switching tube, the second target conduction polarity indicates a voltage polarity for conducting the first switching tube, if the second switching tube is a PMOS tube, the corresponding first target conduction polarity is a negative polarity, and if the first switching tube is an NMOS tube, the corresponding second target conduction polarity is a positive polarity. The first target conduction polarity corresponding to the first control end and the second target conduction polarity corresponding to the second control end can be obtained through the transistor types of the first switching tube and the second switching tube in each control unit.
Step 200, generating a corresponding scanning signal on each row of scanning lines and a corresponding data signal on each column of data lines according to all the first target conduction polarities, all the second target conduction polarities and the display pictures of the current frame, so that when the nth row of scanning lines are started, the data signals on the mth column of data lines control any one of the nth row 2m-1 column control units and the nth row 2m column control units to be conducted or conducted alternately in a time-sharing mode.
In this embodiment, the display screen of the current frame may include various situations, for example, all pixel units are fully bright, two adjacent rows of pixel units are bright half, two adjacent columns of pixel units are bright half, and four adjacent pixels are bright half alternately, where in this embodiment, n=2, m=3 is taken as an example to illustrate a plurality of display screens:
(1) In the first case, when the display screen of the current frame is fully-bright, each column of data lines alternately outputs a corresponding first data signal and a corresponding second data signal in the opening time period of the nth row scanning line of the current frame, wherein the polarities of the first data signal and the second data signal are opposite, the waveforms output by G1 and S1 are shown as 5a in FIG. 5, the fully-bright display screen is shown as 5b in FIG. 5, the waveforms of G2 and G1 are the same, the waveforms of S2 and S3 are similar to those of S1, and the detailed description is omitted herein.
(2) In the second case, when the display picture of the current frame is half bright of the two adjacent rows of pixel units:
The method comprises the steps of enabling odd-numbered scanning lines of a current frame to be in an on state, alternately outputting corresponding first data signals and second data signals by each column of data lines in an on period of the odd-numbered scanning lines of the current frame, or enabling even-numbered scanning lines of the current frame to be in an on state, alternately outputting corresponding first data signals and second data signals by each column of data lines in an on period of the even-numbered scanning lines of the current frame, wherein the odd-numbered scanning lines are equivalent to charging odd-numbered pixel units in the current frame, only charging even-numbered pixel units in the next frame, the scanning lines can be in the on state and can be in the scanning lines to output first scanning signals, the first scanning signals can be in the high level and also in the low level, the polarity of the first scanning signals is determined according to the on polarity of a second switching tube, G1, S1 and G2 output waveforms are shown as 6a in fig. 6a, and two adjacent rows of pixel units are in the bright half of a display picture as shown in 6b in the fig. 6.
(3) In the third case, when the display picture of the current frame is half of the bright display pictures of the two adjacent columns of pixel units, outputting corresponding first data signals by each column of data lines in the on time period of the nth row scanning lines of the current frame, wherein the first data signals can be high level or low level, the polarity of the first data signals is determined according to the on polarity of the first switching tube, waveforms output by G1 and S1 are shown as 7a in fig. 7, half of the bright display pictures of the two adjacent columns of pixel units are shown as 7b in fig. 7, in addition, in the display picture of the next frame, the other half of the bright and symmetrical adjacent columns of pixel units are half of the bright display picture of the next frame, in the case, all the data lines can be charged simultaneously while half power consumption is reduced, scanning time is saved, and the cross display of the upper and lower frames can prevent picture crosstalk.
(4) And fourthly, outputting a first data signal by an mth column data line in an n-th row scanning line opening time period of the current frame and outputting a second data signal by an mth column data line in an n+1-th row scanning line opening time period when the display picture of the current frame is half of the cross brightness of four adjacent pixels, wherein the polarities of the first data signal and the second data signal are opposite. The waveforms output by G1, S1 and G2 are shown as 8a in fig. 8, the display of the adjacent four pixel units of the current frame is shown as 8b in fig. 8, in addition, in the display of the next frame, the adjacent four pixel units are cross-bright symmetrical and the other half, in this case, the power consumption can be reduced by half, all the data lines can be charged simultaneously to save the scanning time, and the cross display of the upper and lower frames can prevent the cross talk of the frames.
In one embodiment of the application, the 3i+1 th column pixel element is a first color sub-pixel, the 3i+2 th column pixel element is a second color sub-pixel, and the 3i+3 th column pixel element is a third color sub-pixel, wherein i= [0,1, 2..i ], when 2M is a multiple of 3OtherwiseRepresentation ofThe result of (2) is rounded down.
It should be noted that when i=0, the 1 st column pixel unit is a first color sub-pixel, the 2 nd column pixel unit is a second color sub-pixel, the 3 rd column pixel unit is a third color sub-pixel, and so on, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged at intervals of columns, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively, as shown in fig. 5-8, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel may also be a blue sub-pixel, a green sub-pixel, and a red sub-pixel, respectively,The lower rounded representation of (2) divided by the integer part of 3, e.g. when m=7
In one embodiment of the application, the 3j+1 th row of pixel cells is a first color subpixel, the 3j+2 th row of pixel cells is a second color subpixel, and the 3j+3 th row of pixel cells is a third color subpixel, wherein j= [0,1, 2..OtherwiseRepresentation ofIt should be noted that when j=0, the 1 st row of pixel units are all first color sub-pixels, the 2 nd row of pixel units are all second color sub-pixels, the 3 rd row of pixel units are all third color sub-pixels, and so on, the first color sub-pixels, the second color sub-pixels and the third color sub-pixels are arranged at row intervals, the first color sub-pixels, the second color sub-pixels and the third color sub-pixels can be red sub-pixels, green sub-pixels and blue sub-pixels respectively, and in addition,The lower rounding of the result of (c) means taking the integer part of N divided by 3, e.g. when n=7
For example, in this embodiment, taking n=6 and m=2 as an example, each row of pixel units sequentially represents a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the pixel architecture of the display panel is shown in fig. 9.
The application uses two adjacent rows of pixel circuits to share the same data line, so that the number of the data lines can be reduced by half, RC Loading in the display panel is greatly reduced, the problem of higher power consumption of the display panel is solved, in addition, the driving mode of one frame of bright half pixel unit and the other half pixel unit of the next frame of bright is combined, the power consumption of the display panel can be further reduced, and the refresh rate of the display panel can be further improved. The panel driving method provided by the embodiment can be applied to liquid crystal displays and OLED displays, and improves the market competitiveness of products.
In one embodiment, the application provides a display device, which comprises a grid driving circuit, a grid driving circuit and a display panel shown in the embodiment, wherein the grid driving circuit is used for outputting a scanning signal, the source driving circuit is used for outputting a data signal, a scanning line of the display panel is connected with the grid driving circuit, and a data line of the display panel is connected with the source driving circuit.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", or a third "may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, reference to the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made in the above embodiments by those skilled in the art within the scope of the application, which is therefore intended to be covered by the appended claims and their equivalents.
Claims (10)
1. A display panel, the display panel comprising:
each pixel circuit comprises a pixel unit and a control unit, wherein the control unit is used for charging the pixel unit through a data signal on the data line when the pixel unit is in a conducting state;
The control unit comprises a first control end, a second control end, an input end and an output end, wherein the first control end of an nth row control unit is connected with an nth row scanning line, the second control end of a 2m-1 st column control unit, the input end of a 2m-1 st column control unit, the second control end of a 2m th column control unit and the input end of a 2m th column control unit are all connected with an mth column data line, and the output end of each control unit is connected with the input end of a corresponding pixel unit;
When the nth row scanning line is started, the data signal on the mth column data line controls any one of the nth row 2M-1 column control unit and the nth row 2M column control unit to be conducted or conducted alternately in a time-sharing mode; wherein n= [1, ], N ], m= [1, ], M, N and M are positive integers greater than 1.
2. The display panel according to claim 1, wherein the control unit includes:
the control end of the first switching tube is connected with the data line, and the first end of the first switching tube is connected with the scanning line;
the control end of the second switching tube is connected with the second end of the first switching tube, the first end of the second switching tube is connected with the data line, and the second end of the second switching tube is connected with the pixel unit;
The first switching tube of the nth row and the 2m-1 th column control unit is opposite to the first switching tube of the nth row and the 2m-1 th column control unit in turn-on voltage.
3. The display panel of claim 1, wherein the odd-numbered row scan lines of the current frame are in an on state and each column of data lines alternately outputs corresponding first data signals and second data signals during an on period of the odd-numbered row scan lines of the current frame, or wherein the even-numbered row scan lines of the current frame are in an on state and each column of data lines alternately outputs corresponding first data signals and second data signals during the on period of the even-numbered row scan lines of the current frame, wherein polarities of the first data signals and the second data signals are opposite.
4. The display panel according to claim 1, wherein corresponding first data signals and second data signals are alternately output per column of data lines in an n-th row scan line on period of a current frame, the first data signals and the second data signals having opposite polarities.
5. The display panel of claim 1, wherein each column of data lines outputs a corresponding first data signal during an n-th row scan line on period of a current frame.
6. The display panel of claim 1, wherein an mth column data line outputs a first data signal during an nth row scan line on period of a current frame and an mth column data line outputs a second data signal during an n+1th row scan line on period, wherein polarities of the first data signal and the second data signal are opposite.
7. The display panel of claim 2, wherein the 3i+1 column pixel cells are first color subpixels, the 3i+2 column pixel cells are second color subpixels, and the 3i+3 column pixel cells are third color subpixels, wherein i= [0,1,2,..OtherwiseRepresentation ofThe result of (2) is rounded down;
Or, 3j+1 row of pixel units is a first color sub-pixel, 3j+2 row of pixel units is a second color sub-pixel, and 3j+3 row of pixel units is a third color sub-pixel, wherein j= [0,1,2, ], when 2N is a multiple of 3 OtherwiseRepresentation ofThe result of (2) is rounded down.
8. The display panel according to any one of claims 1 to 7, wherein,
The pixel unit comprises a liquid crystal capacitor, and a pixel electrode of the liquid crystal capacitor is connected with the output end of the control unit;
Or the pixel unit comprises a storage capacitor, a driving transistor and a light emitting diode, wherein the first end of the storage capacitor is connected with the output end of the control unit, the second end of the storage capacitor is connected with the power end, the control end of the driving transistor is connected with the first end of the storage capacitor, the first end of the driving transistor is connected with the second end of the storage capacitor, the anode of the light emitting diode is connected with the second end of the driving transistor, and the cathode of the light emitting diode is grounded.
9. A display driving method applied to the display panel according to any one of claims 1 to 8, comprising:
acquiring a first target conduction polarity corresponding to a first control end of each control unit in the display panel and a second target conduction polarity corresponding to a second control end of each control unit;
And generating a corresponding scanning signal on each row of scanning lines and a corresponding data signal on each column of data lines according to all the first target conduction polarities, all the second target conduction polarities and the display pictures of the current frame, so that when the nth row of scanning lines are started, the data signals on the mth column of data lines control any one of the nth row 2m-1 column control units and the nth row 2m column control units to be conducted or conducted alternately in a time sharing mode.
10. A display device, the display device comprising:
a gate driving circuit for outputting a scan signal;
a source driving circuit for outputting a data signal;
The display panel of any one of claims 1-8, wherein the scan lines of the display panel are connected to the gate driving circuit and the data lines of the display panel are connected to the source driving circuit.
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| CN105448243A (en) * | 2014-09-22 | 2016-03-30 | Nlt科技股份有限公司 | Pixel circuit, driving method thereof and display device |
| CN114299892A (en) * | 2021-12-24 | 2022-04-08 | 长沙惠科光电有限公司 | Pixel structure, pixel driving method, display panel and display device |
| EP4125082A1 (en) * | 2021-07-30 | 2023-02-01 | LG Display Co., Ltd. | Pixel circuit and display panel including the same |
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| CN105448243A (en) * | 2014-09-22 | 2016-03-30 | Nlt科技股份有限公司 | Pixel circuit, driving method thereof and display device |
| EP4125082A1 (en) * | 2021-07-30 | 2023-02-01 | LG Display Co., Ltd. | Pixel circuit and display panel including the same |
| CN114299892A (en) * | 2021-12-24 | 2022-04-08 | 长沙惠科光电有限公司 | Pixel structure, pixel driving method, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119851592A (en) * | 2024-12-31 | 2025-04-18 | 惠科股份有限公司 | Display panel, display driving method and display device |
| CN119851592B (en) * | 2024-12-31 | 2025-09-19 | 惠科股份有限公司 | Display panel, display driving method and display device |
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