CN120321069B - A channel estimation device based on power delay spectrum estimation - Google Patents

A channel estimation device based on power delay spectrum estimation

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Publication number
CN120321069B
CN120321069B CN202510241720.5A CN202510241720A CN120321069B CN 120321069 B CN120321069 B CN 120321069B CN 202510241720 A CN202510241720 A CN 202510241720A CN 120321069 B CN120321069 B CN 120321069B
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power
data
channel estimation
frequency domain
channel
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CN120321069A (en
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王闻今
谢艾可
江彬
庄佳伟
周晨
马千里
孙旸
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Southeast University
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Southeast University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/024—Channel estimation channel estimation algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H04W72/044—Wireless resource allocation based on the type of the allocated resource
    • H04W72/0446—Resources in time domain, e.g. slots or frames
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H04W72/044—Wireless resource allocation based on the type of the allocated resource
    • H04W72/0473—Wireless resource allocation based on the type of the allocated resource the resource being transmission power
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/12—Wireless traffic scheduling
    • H04W72/1263—Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

The invention discloses a channel estimation device based on power delay spectrum estimation, which is characterized in that firstly, resource particles of pilot frequency are extracted from frequency domain resource grids aiming at different physical channels, LS channel estimation is carried out with generated local pilot frequency, then, according to different physical channels, two strategies of segmentation calculation and inversion edge data are adopted, data are changed into power point numbers of 2, channel estimation values at the pilot frequency are converted into a delay domain through a base 2IFFT fast algorithm, a power delay spectrum window is calculated in the delay domain, noise reduction treatment is carried out on the channel estimation values at the pilot frequency of the delay domain, finally, interpolation is carried out through a base 2FFT fast algorithm, and channel estimation values of the whole frequency domain are obtained, and data are integrated and output according to different physical channels. The invention can give consideration to performance and implementation complexity, process time delay and hardware resources, improve the universality, compatibility, portability and expandability of the system and effectively solve the problem of channel estimation realized based on FPGA or ASIC.

Description

Channel estimation device based on power time delay spectrum estimation
Technical Field
The invention belongs to the wireless field, and particularly relates to a channel estimation device based on power delay spectrum estimation.
Background
Wireless communication environments are quite complex and diverse and are often affected by terrain, buildings, weather, and the like. These factors present challenges such as multipath effects, channel fading, time-variability, frequency selectivity, etc., making the signal susceptible to interference and attenuation in transmission. In such an environment, channel estimation plays a vital role. The method is characterized in that the influence of the signal in the transmission process is accurately known by estimating the state of a transmission channel. The channel estimation helps the system effectively compensate signal distortion, track dynamic changes of the channel in real time, and adjust communication parameters according to current channel conditions. The capacity can ensure that the system can still keep lower error rate and strong anti-interference capacity under a complex environment, and ensures stable communication quality.
Currently, there are relatively few implementations of minimum mean square error (Minimum Mean Square Error, MMSE) channel estimation algorithms. The conventional MMSE channel estimation algorithm needs to be implemented based on the result of Least Square (LS) channel estimation, and needs prior information such as a cross-correlation matrix of a known frequency domain pilot frequency band and a frequency domain full-band channel, and an autocorrelation matrix of the frequency domain pilot frequency band.
Because the MMSE channel estimation algorithm involves matrix inversion and matrix multiplication, which is not beneficial to the hardware implementation of a field programmable gate array (Field Programmable GATE ARRAY, FPGA) or an Application SPECIFIC INTEGRATED Circuit (ASIC), the MMSE channel estimation needs to be approximately simplified and deformed to meet the requirements of performance and implementation complexity, computation delay, FPGA or ASIC hardware resource consumption, and the like. Furthermore, in order to use the radix-2 fast fourier transform (Fast Fourier Transform, FFT), the number of data to be processed needs to be a power of 2. At present, the mainstream algorithm is to zero-fill data of non-2 powers to two powers, however, spectrum leakage caused by the strategy is more serious, and the performance of the MMSE algorithm is obviously reduced.
Disclosure of Invention
The invention aims to solve the problems that the calculation of the current MMSE channel estimation algorithm is complex and is not beneficial to the hardware realization, after zero padding is carried out on non-2 power data, the frequency spectrum leakage is serious when a base 2FFT fast algorithm is used, the algorithm performance is seriously reduced, and the like.
The invention discloses a channel estimation device based on power delay spectrum estimation, which is used for processing a signal of a receiving end of a wireless channel and specifically comprises the following steps:
the resource element extraction module is used for extracting resource elements for placing pilot frequency in a frequency domain resource grid according to a 3GPP protocol aiming at different physical channels, wherein the different physical channels comprise a physical shared channel (Physical Downlink SHARED CHANNEL, PDSCH), a physical broadcast channel (Physical Broadcast Channel, PBCH) and a physical control channel (Physical Control Channel, PDCCH);
the LS channel estimation module is used for generating a local pilot frequency sequence and carrying out LS channel estimation with the received pilot frequency;
the IFFT operation module is used for transforming the data into power point numbers of 2 by adopting two strategies of segmentation calculation and inversion edge data according to different physical channels, and converting an LS channel estimated value at a pilot frequency into a time delay domain through base 2 inverse fast Fourier transform (INVERSE FAST Fourier Transform, IFFT);
the power delay spectrum estimation and noise reduction module is used for calculating a power delay spectrum window in a delay domain and carrying out noise reduction treatment on a channel estimation value at a pilot frequency of the delay domain;
the FFT operation module is used for interpolating through a base 2FFT fast algorithm and obtaining a channel estimation value of a full frequency domain;
and the integration output module is used for integrating and outputting the data according to different physical channels.
Furthermore, the device is deployed and realized on an FPGA or ASIC hardware platform, the unified and fixed-point data bit width is realized, the top layer module, the internal sub-module and the calling IP all use the interface protocol of the unified AXI4-Stream, the internal IP of the module adopts a pipeline structure, and the data processing adopts a parallel processing mode.
Further, the local pilot sequence is generated according to a protocol, specifically, a gold pseudo-random sequence is modulated by Quadrature phase shift coding (Quadrature PHASE SHIFT KEYING, QPSK). In the physical shared channel, the generation of the gold sequence is related to factors such as the sequence number of the time slot in the radio frame, the scrambling ID, the number of orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM) symbols contained in one time slot, and the OFDM symbol index where the DMRS is placed in one time slot. In the physical broadcast channel, the gold sequence is generated in relation to factors such as SS/PBCH block index, cell ID, field indication, etc. In the physical control channel, the generation of the gold sequence is related to factors such as the sequence number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in one time slot, the OFDM symbol index where the DMRS is placed in one time slot, and the like.
Furthermore, in the physical shared channel, configuration of different partial Bandwidths (BWP) is supported, so that the number of input frequency domain data is calculated according to configuration information, such as the size of the input RB, and then the maximum number of power points smaller than 2 of the number of input frequency domain data is obtained by table lookup, and the input data is segmented according to the table lookup result. The method is characterized in that data are divided into two sections, wherein the data of the power point number of the first 2 are the first half section, the data of the power point number of the second 2 are the second half section, the first half section is fetched from the top of the complete frequency domain data, the second half section is fetched from the tail of the complete frequency domain data, and the data at the two ends are partially overlapped in the middle. If the size of the input frequency domain data is just the power of 2, the two pieces of data are the size of the input frequency domain data, namely the original data are not segmented, so that the universality of the whole module can be improved. And then performing IFFT fast operation on the two sections of data respectively.
Further, in the physical broadcast channel, the pilot signals on the complete OFDM symbols of columns 2 and 4 in the physical broadcast block are used for estimation. Since the OFDM symbols of the 2 nd and 4 th columns of the synchronous broadcast block fixedly occupy 240 subcarriers in the frequency domain, and the pilots are four times spread, 60 pilot data are fixed on one column. And reversing the last 4 data, supplementing the total data to 64 points, and performing 64-point IFFT fast operation.
Furthermore, in the physical control channel, due to the resource mapping characteristic, pilot symbols are distributed on 1-3 OFDM symbols, and a four-time sparse distribution placing mode is presented on a frequency domain. Therefore, it is necessary to calculate the number of input frequency domain data according to configuration information, such as the size of the input RB, then look up a table to obtain the maximum number of power points smaller than 2 of the input data, and segment the input data according to the result of the table look up. The method is characterized in that data are divided into two sections, wherein the data of the power point number of the first 2 are the first half section, the data of the power point number of the second 2 are the second half section, the first half section is fetched from the top of the complete frequency domain data, the second half section is fetched from the tail of the complete frequency domain data, and the data at the two ends are partially overlapped in the middle. If the size of the input frequency domain data is just the power of 2, the two pieces of data are the size of the input frequency domain data, namely the original data are not segmented, so that the universality of the whole module can be improved. And then performing IFFT fast operation on the two sections of data respectively.
Further, the power delay profile estimation includes the following steps:
(a) Intercepting the LS channel estimation value of the time delay domain, carrying out first noise reduction, and configuring the noise reduction window length from the outside of the module;
(b) Calculating the power of an LS channel estimated value at a pilot frequency position on a time delay domain;
(c) Calculating the average value of the LS channel estimation value power value on the same subcarrier in the same time slot or in a plurality of time slots;
(d) Calculating a time delay domain power spectrum soft window by combining noise power, wherein the noise power is input from the outside of a module and is compared with a time delay domain power average value obtained on the same subcarrier, so that a numerator and a denominator of a power time delay spectrum window are obtained, if the time delay domain power is smaller than the noise power and the noise power is 0, the denominator of the power time delay spectrum window is 1, if the time delay domain power is smaller than the noise power and the noise power is not 0, the denominator of the power time delay spectrum window is the noise power, otherwise, the denominator of the power time delay spectrum window is the time delay domain power, and if the time delay domain power is not smaller than the noise power, the numerator of the power time delay spectrum window is the time delay domain power minus the noise power, otherwise, the denominator is 0;
(e) And adding a soft window to the LS channel estimation value at the pilot frequency in the time delay domain to perform secondary noise reduction.
Furthermore, in the physical shared channel, because the pilot frequency is placed in a double sparse way, the LS channel estimation value after the noise reduction of the time delay domain is subjected to zero padding firstly, so that the data volume after the zero padding reaches twice the pilot frequency data volume after segmentation, then the FFT fast operation of the corresponding point number is carried out, the frequency domain interpolation is completed, and finally the overlapping parts of the frequency domain channel estimation values obtained by the two segments of interpolation are combined, and the complete frequency domain full channel estimation value is output.
Furthermore, in the physical broadcast channel, because the pilot frequency is placed in a four-time sparse way, the LS channel estimation value after the noise reduction of the time delay domain is subjected to zero filling firstly, so that the data volume after the zero filling reaches 4 times of the pilot frequency data volume after the segmentation, then the FFT fast operation of the corresponding point number is carried out, the frequency domain interpolation is completed, the data is finally truncated to 240 points, and the channel estimation value on the 3 rd OFDM symbol of the SSB block can be obtained by averaging or interpolating the channel estimation value on the 2 nd OFDM symbol and the 4 th OFDM symbol.
Furthermore, in the physical control channel, because the pilot frequency is placed in a four-fold sparse way, the LS channel estimation value after the time delay domain noise reduction is subjected to zero padding firstly, so that the data volume after the zero padding reaches 4 times of the pilot frequency data volume after segmentation, then the FFT fast operation of the corresponding point number is carried out, the frequency domain interpolation is completed, and finally the overlapped parts of the frequency domain channel estimation values obtained by the two segments of interpolation are combined, and the complete frequency domain full channel estimation value is output.
Compared with the prior art, the invention has the following advantages:
1. The architecture can support the channel estimation processing of a receiving end of a plurality of physical channels including a physical shared channel, a physical broadcast channel, a physical control channel and the like, has good channel estimation performance under the channel conditions of a Gaussian Noise channel (ADDITIVE WHITE AWGN), a multipath channel and the like, and improves the universality of the module;
2. The method has the advantages that the data quantity is controlled to be the power point number of 2 by using the segmentation and inversion edge data, the hardware implementation is more convenient by using the FFT fast algorithm, the frequency spectrum leakage caused by zero padding is optimized, and the problem of serious performance degradation caused by the frequency spectrum leakage is solved;
3. The data processing adopts a pipelining parallel processing mode, so that the data processing time delay is effectively reduced;
4. For the physical control channel, channel estimation caused by interleaving when the resource grid is discontinuous in the frequency domain can be supported, and the compatibility of the system is improved;
5. the reasonable design of the calculation structure unifies the bit width of the fixed-point data, thereby saving the hardware realization resources;
6. The module portability is improved by using the interface protocol of unified AXI 4-Stream;
7. the hardware implementation logic of the data processing module is optimized, and the expandability of the module is improved, namely, when the power value of the delay domain signal is averaged, multiple groups of additional pilots in one time slot or multiple groups of pilots and additional pilots in multiple time slots can be averaged, so that the overall performance is improved.
Drawings
Fig. 1 is a schematic diagram of a channel estimation device based on power delay spectrum estimation according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a PDSCH channel frequency domain resource grid structure.
Fig. 3 is a schematic diagram of an implementation structure of an LS channel estimation module according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a data segment implementation structure according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a power delay spectrum window implementation structure according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of an implementation structure of a power accumulation average module according to an embodiment of the invention.
Fig. 7 is a flowchart of power delay spectrum window calculation according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a zero padding module implementation structure according to an embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further described below with reference to the attached drawings and specific embodiments.
The embodiment of the invention discloses a channel estimation device structure based on power delay spectrum estimation, which can be deployed and realized on an FPGA or ASIC hardware platform.
As shown in fig. 1, the channel estimation device based on power delay spectrum estimation includes a resource element extraction module, an LS channel estimation module, an IFFT operation module, a power delay spectrum estimation and noise reduction module, an FFT operation module and an integration output module. The system comprises a base station side or a user terminal, a resource element extraction module, an IFFT operation module, a power delay spectrum estimation and noise reduction module, an FFT operation module and an integration output module, wherein the base station side or the user terminal is used for extracting resource elements for placing pilots in a frequency domain resource grid according to different physical channels, the different physical channels comprise a PDSCH channel, a PBCH channel and a PDCCH channel, the LS channel estimation module is used for generating local pilot sequences through the protocols and carrying out LS channel estimation with received pilots, the IFFT operation module is used for changing data into power point numbers of 2 according to the different physical channels, the LS channel estimation value at the pilots is converted into a time delay domain through a base 2IFFT fast algorithm, the power delay spectrum estimation and noise reduction module is used for calculating a power delay spectrum window in the time delay domain and carrying out noise reduction processing on the channel estimation value at the pilots of the time delay domain, the FFT operation module is used for carrying out interpolation through the base 2FFT fast algorithm and obtaining the channel estimation value of the whole frequency domain, and the integration output module is used for integrating and outputting the data according to the different physical channels.
The working flow of the channel estimation device based on the power time delay spectrum estimation is that at a receiving end, frequency domain data, noise variance and system configuration information, such as RB size to be processed, frame timing information including subcarrier index, OFDM symbol index, time slot number index and frame number index, are input by an upper module, and after the frequency domain data is processed by the flow, frequency domain channel coefficient estimation values are output by taking time slots as units.
In this embodiment, in the PDSCH, the time-frequency resource position of the Demodulation reference signal (DMRS) is related to factors such as the duration of the physical channel in one slot, the DMRS mapping method, and the additional pilot configuration. In the PBCH, the time-frequency resource position of the DMRS is placed on the 2,3,4 th symbol of the synchronous broadcast block (Synchronization Signal/PBCH, SSB). In each Resource Block (RB), a DMRS specific mapping location is related to a cell ID configuration. In the PDCCH, the position of the DMRS on the resource grid is the 1 st, 5 th and 9 th resource elements in each resource block.
Fig. 2 is a schematic diagram of a PDSCH channel frequency domain resource grid structure. Taking PDSCH channel as an example, in the resource element extraction module, pilot symbols are extracted according to the frequency domain position of the physical shared channel indicated in the physical control channel and the pilot mapping mode, and then subsequent channel estimation is performed. In the physical shared channel, there are various pilot mapping modes, as shown in fig. 2, the pilot is mapped on the 3 rd and 10 th OFDM symbols in the time domain, and the frequency domain adopts a mapping mode of 2 times sparse division.
For the PBCH channel, it is necessary to first find the resource grid where the SSB is located, and then extract the complete pilot symbols in columns 2 and 4 in the PBCH to perform subsequent channel estimation.
For the PDCCH channel, blind detection is required, and then pilot symbols in a continuous frequency domain on a control resource set (Control Resource Set, CORESET) are extracted to perform subsequent channel estimation.
Fig. 3 is a schematic diagram of an implementation structure of the LS channel estimation module. The LS channel estimation module mainly realizes the function of carrying out LS channel estimation on the extracted received pilot frequency and a locally generated pilot frequency sequence. Because of the specificity of the local pilot sequence, its modulus is 1, and there is only a phase difference between different pilot symbols. The local pilot sequence is generated according to a protocol, specifically, the gold pseudo-random sequence is subjected to quadrature phase shift coded QPSK modulation. In the PDSCH channel, the generation of the gold sequence is related to factors such as the sequence number of the time slot in the radio frame, the scrambling ID, the number of the OFDM symbols contained in one time slot, and the OFDM symbol index where the DMRS is placed in one time slot. In the PBCH channel, the gold sequence is generated in relation to factors such as SS/PBCH block index, cell ID, field indication, etc. In the PDCCH, the gold sequence is generated according to the sequence number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in one time slot, the OFDM symbol index placed in one time slot by the DMRS, and other factors.
Specifically, the specific generation mode of the local pilot frequency in the PDSCH channel is that gold pseudo-random sequences are QPSK modulated, namely:
Wherein r represents a generated demodulation reference signal, m represents a symbol sequence number after modulation, c represents a pseudo random sequence, and the specific generation mode is as follows:
c(n)=[x1(n+Nc)+x2(n+Nc)]mod2
Where N c = 1600, the sequences x 1 (N) and x 2 (N) are defined as:
x1(n+31)＝[x1(n+3)+x1(n)]mod2
x2(n+31)＝[x2(n+3)+x2(n+2)+x2(n+1)+x2(n)]mod2
the initial values of x 1 (n) and x 2 (n) are respectively:
Wherein, the Wherein, the For the number of OFDM symbols in one slot,For the slot number in a frame, l is the OFDM symbol index in which the DMRS is placed in a slot, n SCID is the scrambling ID, n SCID ε {0,1} is given by the DMRS initialization field,Representing an identifier associated with the reference signal,Given by the relevant parameters in the DMRS-DownlinkConfig IE, if no DMRS-DownlinkConfig IE is providedWherein the method comprises the steps ofIs the physical cell ID of the serving cell.
In the PBCH channel, the reference sequence and the pseudo random sequence are generated in the same manner as the PDSCH, and the initialization value is generated in the following manner:
where n hf is the field indication of the PBCH, i SSB is the index of the SS/PBCH block, Is the physical cell ID of the serving cell.
In the PDCCH, the reference sequence and the pseudo random sequence are generated in the same manner as the PDSCH, and the initialization value is generated in the following manner:
Wherein, the For the number of OFDM symbols in one slot,For a slot number within a frame, i is an OFDM symbol index within a slot, N ID is a scrambling ID, N ID e {0,1} is given by the DMRS initialization field, N ID e {0, 1..65535 } is given by a related parameter in pdcch-DMRS-ScramblingID, if pdcch-DMRS-ScramblingID is not providedWherein the method comprises the steps ofIs the physical cell ID of the serving cell.
Because of the specificity of the local pilot sequence, the hardware implementation of the LS channel estimation algorithm can convert division into phase rotation of the local pilot by means of the CORDIC algorithm, so that the hardware resource consumption of the FPGA or the ASIC can be reduced, and the processing time delay is reduced. The module outputs LS channel estimates at the pilot symbols.
The IFFT operation module is used for carrying out fast IFFT operation after mainly segmenting the LS channel estimation value of the frequency domain into powers of 2 and converting the LS channel estimation value into the LS channel estimation value of the time delay domain. In the physical shared channel, different partial bandwidth configurations are supported, so that the number of input frequency domain data is calculated according to configuration information, such as the size of an input RB, then the maximum number of power points which is less than 2 of the number of input frequency domain data is obtained through table lookup, and the input data is segmented according to the table lookup result. The method is characterized in that data are divided into two sections, wherein the data of the power point number of the first 2 are the first half section, the data of the power point number of the second 2 are the second half section, the first half section is fetched from the top of the complete frequency domain data, the second half section is fetched from the tail of the complete frequency domain data, and the data at the two ends are partially overlapped in the middle. If the size of the input frequency domain data is just the power of 2, the two pieces of data are the size of the input frequency domain data, namely the original data are not segmented, so that the universality of the whole module can be improved. And then performing IFFT fast operation on the two sections of data respectively.
In the physical broadcast channel, the pilot signals on the complete OFDM symbols of columns 2 and 4 in the physical broadcast block are used for estimation. Since the OFDM symbols of the 2 nd and 4 th columns of the synchronous broadcast block fixedly occupy 240 subcarriers in the frequency domain, and pilots are four times spread, 60 pilot data are fixed on one column. And reversing the last 4 data, supplementing the total data to 64 points, and performing 64-point IFFT fast operation.
In the physical control channel, due to the resource mapping characteristic, pilot symbols are distributed on 1-3 OFDM symbols, and a four-time sparse placement mode is presented on a frequency domain. Therefore, it is necessary to calculate the number of input frequency domain data according to configuration information, such as the size of the input RB, then look up a table to obtain the maximum number of power points smaller than 2 of the input data, and segment the input data according to the result of the table look up. The method is characterized in that data are divided into two sections, wherein the data of the power point number of the first 2 are the first half section, the data of the power point number of the second 2 are the second half section, the first half section is fetched from the top of the complete frequency domain data, the second half section is fetched from the tail of the complete frequency domain data, and the data at the two ends are partially overlapped in the middle. If the size of the input frequency domain data is just the power of 2, the two pieces of data are the size of the input frequency domain data, namely the original data are not segmented, so that the universality of the whole module can be improved. And then performing IFFT fast operation on the two sections of data respectively.
Illustratively, FIG. 4 is a schematic diagram of a data segment implementation. As shown in fig. 4 (a), for LS channel estimation values of non-2 power points in PDCCH and PDSCH, data is divided into two pieces of power data of 2 before and after, and the two pieces of data overlap partially. If the data quantity of the LS channel estimation value is just the power of 2, the two segments of data are both original data, so that the universality of the module is improved. The length of the intercepted power point number of the front section 2 and the rear section 2 can be obtained through table lookup according to the input system configuration information, such as configuration information of RB size and the like.
As shown in fig. 4 (b), for PBCH, the LS channel estimation value is fixed to 60 data, so that the end data is inverted to 4 bits, i.e., the 56 th to 59 th data are directly inverted and spliced to the 60 th data, and then 64 bit data are directly formed, which is the smallest two power data larger than 60, and thus the algorithm performance is better than the segmentation into 232 point data.
As shown in fig. 4 (c), the hardware implementation of the IFFT operation is to use the FFT IP core in the FPGA or ASIC hardware platform to complete the power point serial IFFT operation corresponding to 2. The input time delay domain channel estimation value is divided into the data of the power point number of the front section and the rear section 2 through the counting of the frame timing information, and then, for the PDSCH and the PDCCH channels, a FIFO IP is used for buffering, for the PBCH channels, a stack function module is used for reversing the data, and finally, the two sections of data are serially input into an FFT IP core. And configuring the information such as the operation point number of the FFT IP, the flag bit of the last data, the valid flag bit of the data and the like according to externally input system configuration information such as the size of a resource block and the like so as to enable the FFT IP to perform dynamic FFT operation point number configuration.
Since the receiving end data may be affected by noise, the first noise reduction operation is needed to be performed on the delay domain data, namely, the noise reduction window length is configured outside the module, and a window can be configured before and after the whole data so as to cope with frequency domain leakage. And cutting off output data of the FFT IP according to the window length, reserving data in front and rear windows, and carrying out zero setting processing on data outside the windows. The window length can be configured from outside, so that the universality and the flexibility of the system are improved.
The power delay spectrum estimation and noise reduction module is mainly used for completing the calculation of the power delay spectrum window in the delay domain and reducing the noise of the channel estimation value at the pilot frequency on the delay domain. The power delay spectrum estimation comprises the following steps of (a) cutting off a delay domain LS channel estimation value, carrying out first noise reduction, (b) calculating the power of the LS channel estimation value at a pilot frequency position on the delay domain, (c) calculating the average value of LS channel estimation value power values on the same subcarrier in the same time slot or multiple time slots, (d) calculating a delay domain power spectrum soft window by combining noise power, and (e) adding the soft window to the LS channel estimation value at the pilot frequency position on the delay domain, and carrying out second noise reduction.
Fig. 5 is a schematic diagram of a power delay spectrum window implementation structure, and the module mainly comprises a power accumulation average module, a power delay spectrum window module, a secondary windowing module and a zero padding module. The module obtains the power of the input complex-valued signal data and obtains the average power on the same subcarrier of a plurality of OFDM symbols in the same time slot or on the same subcarrier of a plurality of OFDM symbols in a plurality of time slots. The module supports window length calculation of single time slot and multiple time slots, and expandability and universality of the module are improved.
The implementation structure of the power accumulation average module is shown in fig. 6, and mainly consists of two DSPIP. The time delay domain data after the first noise reduction is in a complex form, the real part and the imaginary part of the data are separated, and the real part square is calculated by using a function of DSPIP A, B and C. Wherein, the A and B ports are both input with real part of data, and the C port is selected to input with output data of the subsequent stage DSPIP or 0. The module simultaneously realizes the accumulation function, so that when the input data is the data on the first column of the accumulated OFDM symbols, the selector selects 0 for input, and if the input data is the data on other columns of OFDM symbols in the same time slot or the data on OFDM symbols in the subsequent time slot, the second DSPIP is selected for output. The second DSPIP selects the function of a x B + C for the calculation of the square of the imaginary part and sums the square of the real part. Wherein, the A and B ports are both input with the imaginary part of the data, and the C port is selected to input the output result of the first DSPIP. The output result of the second stage DSPIP needs to be selectively processed, that is, if the accumulated values on the same subcarrier on a plurality of OFDM symbols in the same time slot are calculated, or the accumulated values on the same subcarrier on a plurality of OFDM symbols in a plurality of time slots are calculated, the power values are averaged and output, and if the accumulated calculation is not completed, the calculation result is stored in the FIFO, and the data in the next group of OFDM symbols is waited for input.
The power time delay spectrum window generating module is mainly composed of DIV IP, and the generating mode of the power time delay spectrum window numerator and denominator is shown as a power time delay spectrum window calculation flow chart in figure 7. The noise power is input from the outside and then compared with the average value of the delay domain power obtained on the same subcarrier, so as to obtain the numerator and denominator of the power delay spectrum window. The method comprises the following steps that if the delay domain power is smaller than the noise power and the noise power is 0, the denominator of the power delay spectrum window is 1, if the delay domain power is smaller than the noise power and the noise power is not 0, the denominator of the power delay spectrum window is the noise power, otherwise, the denominator of the power delay spectrum window is the delay domain power, if the delay domain power is not smaller than the noise power, the numerator of the power delay spectrum window is the delay domain power minus the noise power, otherwise, the numerator is 0. And finally, division operation is carried out by using a DIV IP core in the FPGA or ASIC hardware platform, and a power delay spectrum window is output. The reasonable design of the calculation structure is realized, and the magnitude of the numerator and the denominator are close in the designed soft window, so that the data can be scaled according to a unified format, the problem that the bit width of the fixed-point data is required to be increased due to overlarge or undersize divider results is avoided, and the hardware realization resources are saved.
In the secondary windowing module, the time delay domain LS channel estimation data after the first noise reduction is multiplied with the generated soft window result, the multiplication can be realized through MULT IP in FPGA or ASIC, and the module completes the secondary noise reduction in the time delay domain.
As shown in the implementation structure diagram of the zero padding module in fig. 8, in the zero padding module, zero padding output is required to be performed on data after the secondary windowing. The specific method is that for PDSCH channel, the length of power data of each segment 2 is assumed to be N, because the pilot frequency is double sparse in frequency domain, N0 are needed to be added in the middle of effective data of front and back windows to make the total length of data be 2N, for PBCH and PDCCH channel, the length of power data of each segment 2 is assumed to be N, because the pilot frequency is four times sparse in frequency domain, 3N 0 are needed to be added in the middle of effective data of front and back windows to make the total length of data be 4N. The module outputs LS channel estimation data after zero padding of the time delay domain after the secondary noise reduction.
And inputting the time delay domain data after the secondary noise reduction into an FFT operation module, and correspondingly configuring the information such as the operation point number of the FFT IP, the flag bit of the last data, the effective flag bit of the data and the like. The FFT operation point number can be obtained by looking up a table according to the input system configuration information, such as the configuration information of the size of the resource block.
The main function of the integration output module is to integrate and output the segmented frequency domain data finally. And for PDSCH and PDCCH channels, averaging overlapped parts of the segmented full-frequency-domain channel estimation and outputting. For the PBCH channel, the first 240 points of the frequency domain channel estimation value are intercepted and output as the channel estimation value of the PBCH frequency domain channel, and for the channel estimation value of the PBCH on the 3 rd incomplete OFDM symbol in the SSB, the channel estimation value of the PBCH on the 2 rd and 4 th OFDM symbols can be obtained through average or interpolation.
In the channel estimation device based on power delay spectrum estimation, the top layer module, the inner sub-module and the calling IP all use the interface protocol of the unified AXI4-Stream, so that the portability of the module is improved. And the IP inside the module adopts a pipeline structure, and the data processing adopts a parallel processing mode, so that the data processing time delay is effectively reduced.

Claims (8)

1.一种基于功率时延谱估计的信道估计装置，其特征在于，包括：1. A channel estimation device based on power delay spectrum estimation, characterized in that it comprises: 资源粒子提取模块，用于针对不同物理信道，提取出频域资源栅格中放置导频的资源粒子；所述不同物理信道包括物理共享信道，物理广播信道和物理控制信道；The resource particle extraction module is used to extract the resource particles in the frequency domain resource grid that contain pilots for different physical channels; the different physical channels include physical shared channels, physical broadcast channels and physical control channels; LS信道估计模块，用于生成本地导频序列，并与资源粒子提取模块提取出的导频进行LS信道估计；The LS channel estimation module is used to generate local pilot sequences and perform LS channel estimation with the pilots extracted by the resource particle extraction module. IFFT运算模块，用于根据不同物理信道，采用分段计算和反转边缘数据两种策略，将输入频域数据变形成2的幂次点数，通过基2 IFFT快速算法将导频处的LS信道估计值转换到时延域；The IFFT operation module is used to transform the input frequency domain data into a power of 2 number of points by employing two strategies: segmented calculation and inverted edge data, based on different physical channels. The radix-2 IFFT fast algorithm is then used to convert the LS channel estimate at the pilot to the time delay domain. 功率时延谱估计及降噪模块，用于在时延域计算功率时延谱窗，并对时延域的导频处的信道估计值进行降噪处理；The power delay spectrum estimation and noise reduction module is used to calculate the power delay spectrum window in the delay domain and to perform noise reduction processing on the channel estimate at the pilot in the delay domain. FFT运算模块，用于输入降噪处理后的时延域信道估计值，通过基2 FFT快速算法插值并得到全频域的信道估计值；The FFT operation module is used to input the time-delay domain channel estimate after noise reduction, and then interpolate it using the radix-2 FFT fast algorithm to obtain the full-frequency domain channel estimate. 整合输出模块，用于根据不同物理信道将分段的频域数据进行整合输出；The integrated output module is used to integrate and output segmented frequency domain data according to different physical channels; 物理广播信道中，采用反转边缘数据策略，将最后几个数据进行反转，将总体数据补至最小的2的幂次点数，再进行IFFT快速运算；In the physical broadcast channel, the reverse edge data strategy is adopted, which reverses the last few data points, fills the total data to the minimum power of 2 points, and then performs IFFT fast operation. 物理控制信道中，采用分段计算策略，根据配置信息，计算得到输入频域数据量，然后查表求得最大的小于输入频域数据量的2的幂次点数，并根据查表结果对输入数据进行分段：前2的幂次点数的数据为前半段，后2的幂次点数的数据为后半段，前半段从完整频域数据顶头开始取，后半段从完整频域数据末尾开始取，两端数据在中间有部分重叠，若输入频域数据量大小恰好为2的幂次，则两段数据均为输入频域数据本身数据量大小；接着对两段数据分别进行IFFT快速运算。In the physical control channel, a segmented calculation strategy is adopted. Based on the configuration information, the input frequency domain data volume is calculated. Then, a table is consulted to find the largest power of 2 point that is less than the input frequency domain data volume. The input data is then segmented according to the table lookup result: the data with the first power of 2 points is the first half, and the data with the second power of 2 points is the second half. The first half is taken from the top of the complete frequency domain data, and the second half is taken from the end of the complete frequency domain data. The two ends of the data overlap in the middle. If the input frequency domain data volume is exactly a power of 2, then both segments of data are the same size as the input frequency domain data itself. Then, IFFT fast calculation is performed on the two segments of data respectively. 2.根据权利要求1所述的一种基于功率时延谱估计的信道估计装置，其特征在于，所述装置在FPGA或ASIC硬件平台上部署实现，统一定点化数据位宽，顶层模块及内部子模块、调用IP均使用统一AXI4-Stream的接口协议，模块内部IP都采用流水结构，且数据处理采用并行处理方式。2. The channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that the device is deployed on an FPGA or ASIC hardware platform, with a unified fixed-point data bit width, the top-level module and internal sub-modules and calling IP all use the unified AXI4-Stream interface protocol, the internal IP of the modules all adopt a pipelined structure, and the data processing adopts a parallel processing method. 3.根据权利要求1所述的一种基于功率时延谱估计的信道估计装置，其特征在于，所述本地导频根据协议生成，通过gold序列进行QPSK调制；物理共享信道中，gold序列的生成与时隙在无线帧中的序号，加扰ID，一个时隙内所含OFDM符号个数以及DMRS在一个时隙内放置的OFDM符号索引有关；物理广播信道中，gold序列的生成与SS/PBCH块索引，小区ID和半帧指示有关；物理控制信道中，gold序列的生成与时隙在无线帧中的序号，加扰ID，一个时隙内所含OFDM符号个数以及DMRS在一个时隙内放置的OFDM符号索引有关。3. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that: the local pilot is generated according to a protocol and QPSK modulation is performed using a gold sequence; in the physical shared channel, the generation of the gold sequence is related to the sequence number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in a time slot, and the OFDM symbol index placed by the DMRS in a time slot; in the physical broadcast channel, the generation of the gold sequence is related to the SS/PBCH block index, the cell ID, and the half-frame indicator; in the physical control channel, the generation of the gold sequence is related to the sequence number of the time slot in the radio frame, the scrambling ID, the number of OFDM symbols contained in a time slot, and the OFDM symbol index placed by the DMRS in a time slot. 4.根据权利要求1所述的一种基于功率时延谱估计的信道估计装置，其特征在于，物理共享信道中，采用分段计算策略，支持不同部分带宽配置，根据配置信息，计算得到输入频域数据量，然后查表求得最大的小于输入频域数据量的2的幂次点数，并根据查表结果对输入数据进行分段：前2的幂次点数的数据为前半段，后2的幂次点数的数据为后半段，前半段从完整频域数据顶头开始取，后半段从完整频域数据末尾开始取，两端数据在中间有部分重叠，若输入频域数据量大小恰好为2的幂次，则两段数据均为输入频域数据本身数据量大小；接着对两段数据分别进行IFFT快速运算。4. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, in the physically shared channel, a segmented calculation strategy is adopted to support different bandwidth configurations. According to the configuration information, the input frequency domain data volume is calculated, and then the largest power of 2 points less than the input frequency domain data volume are obtained by looking up a table. The input data is then segmented according to the table lookup result: the data with the first power of 2 points is the first half, and the data with the last power of 2 points is the second half. The first half is taken from the top of the complete frequency domain data, and the second half is taken from the end of the complete frequency domain data. The data at both ends overlap in the middle. If the input frequency domain data volume is exactly a power of 2, then both segments of data are the same size as the input frequency domain data itself. Then, IFFT fast calculation is performed on the two segments of data respectively. 5.根据权利要求1所述的一种基于功率时延谱估计的信道估计装置，其特征在于，所述功率时延谱估计包括如下步骤：5. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that the power delay spectrum estimation includes the following steps: （a）对时延域LS信道估计值进行截断，进行第一次降噪，其中降噪窗长由模块外部配置；(a) The time delay domain LS channel estimate is truncated and the first noise reduction is performed, wherein the noise reduction window length is configured externally to the module; （b）计算时延域上导频处LS信道估计值的功率；(b) Calculate the power of the estimated LS channel at the pilot in the time delay domain; （c）计算同一个时隙内或者多个时隙内，同一个子载波上的LS信道估计值功率值的平均值；(c) Calculate the average value of the estimated power values of the LS channel on the same subcarrier within the same time slot or multiple time slots; （d）结合噪声功率计算时延域功率谱软窗，其中噪声功率由模块外部输入，再由其与同一个子载波上求得的时延域功率平均值相比较，从而获得功率时延谱窗的分子和分母，若时延域功率小于噪声功率且噪声功率为0，则功率时延谱窗的分母为1，若时延域功率小于噪声功率且噪声功率不为0，则功率时延谱窗的分母为噪声功率，否则功率时延谱窗的分母为时延域功率；若时延域功率不小于噪声功率则功率时延谱窗的分子为时延域功率减去噪声功率，否则为0；(d) Calculate the power spectrum soft window in the time delay domain by combining the noise power. The noise power is input from outside the module and then compared with the average power in the time delay domain obtained on the same subcarrier to obtain the numerator and denominator of the power time delay spectrum window. If the power in the time delay domain is less than the noise power and the noise power is 0, the denominator of the power time delay spectrum window is 1. If the power in the time delay domain is less than the noise power and the noise power is not 0, the denominator of the power time delay spectrum window is the noise power. Otherwise, the denominator of the power time delay spectrum window is the power in the time delay domain. If the power in the time delay domain is not less than the noise power, the numerator of the power time delay spectrum window is the power in the time delay domain minus the noise power. Otherwise, it is 0. （e）对时延域上导频处的LS信道估计值加上软窗进行二次降噪。(e) Add a soft window to the LS channel estimate at the pilot in the time delay domain for secondary noise reduction. 6.根据权利要求1所述的一种基于功率时延谱估计的信道估计装置，其特征在于，物理共享信道中，导频二倍疏分放置，首先对时延域降噪后的LS信道估计值进行补零，使补零后的数据量达到分段后导频数据量的两倍，然后再进行对应点数的FFT快速运算，完成频域插值，最后将两段插值得到的频域信道估计值重叠部分合并，并输出完整的频域全信道估计值。6. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, in the physical shared channel, the pilots are placed in a double-sparse manner. First, the LS channel estimation value after delay domain noise reduction is padded with zeros so that the amount of data after zero padding is twice the amount of pilot data after segmentation. Then, the corresponding number of FFT fast calculations are performed to complete the frequency domain interpolation. Finally, the overlapping part of the frequency domain channel estimation values obtained by the two interpolations is merged, and the complete frequency domain full channel estimation value is output. 7.根据权利要求1所述的一种基于功率时延谱估计的信道估计装置，其特征在于，物理广播信道中，导频是四倍疏分放置，首先对时延域降噪后的LS信道估计值进行补零，使补零后的数据量达到分段后导频数据量的四倍，然后再进行对应点数的FFT快速运算，完成频域插值，最后将数据截断至原点数，对于SSB块的第三列OFDM符号上的信道估计值可由第二、四列OFDM符号上的信道估计值通过平均或者插值得到。7. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, in the physical broadcast channel, the pilots are placed in a four-fold sparse distribution. First, the LS channel estimation value after delay domain noise reduction is padded with zeros so that the amount of data after zero padding reaches four times the amount of pilot data after segmentation. Then, the corresponding number of points is subjected to fast FFT calculation to complete frequency domain interpolation. Finally, the data is truncated to the original number of points. The channel estimation value on the third column OFDM symbol of the SSB block can be obtained by averaging or interpolating the channel estimation values on the second and fourth columns OFDM symbols. 8.根据权利要求1所述的一种基于功率时延谱估计的信道估计装置，其特征在于，物理控制信道中，导频是四倍疏分放置，首先对时延域降噪后的LS信道估计值进行补零，使补零后的数据量达到分段后导频数据量的四倍，然后再进行对应点数的FFT快速运算，完成频域插值，最后将两段插值得到的频域信道估计值重叠部分合并，并输出完整的频域全信道估计值。8. A channel estimation device based on power delay spectrum estimation according to claim 1, characterized in that, in the physical control channel, the pilots are placed in a four-fold sparse distribution. First, the LS channel estimation value after delay domain noise reduction is padded with zeros so that the amount of data after zero padding reaches four times the amount of pilot data after segmentation. Then, the corresponding number of FFT fast calculations are performed to complete the frequency domain interpolation. Finally, the overlapping part of the frequency domain channel estimation values obtained by the two interpolations is merged, and the complete frequency domain full channel estimation value is output.
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