CN120322012A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the sameInfo
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- CN120322012A CN120322012A CN202410042945.3A CN202410042945A CN120322012A CN 120322012 A CN120322012 A CN 120322012A CN 202410042945 A CN202410042945 A CN 202410042945A CN 120322012 A CN120322012 A CN 120322012A
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Abstract
一种半导体装置及其形成方法，其中，半导体装置具有第一导电类型的基底、形成于基底上且具有第一导电类型的外延层、第一元件以及与第一元件电连接的第二元件。第一元件包含第一栅极沟槽结构和第一遮蔽部，基底作为第一元件的漏极。第二元件包含第二栅极沟槽结构、平面栅极结构和第二遮蔽部。第一和第二栅极沟槽结构自外延层的顶表面延伸至外延层中。平面栅极结构位于外延层的顶表面上。第一遮蔽部位于第一栅极沟槽结构下方并与第一栅极沟槽结构的底部接触。第二遮蔽部位于第二栅极沟槽结构下方并与第二栅极沟槽结构的底部接触。第一遮蔽部和第二遮蔽部具有第二导电类型。
A semiconductor device and a method for forming the same, wherein the semiconductor device has a substrate of a first conductivity type, an epitaxial layer formed on the substrate and having the first conductivity type, a first element, and a second element electrically connected to the first element. The first element includes a first gate trench structure and a first shielding portion, and the substrate serves as a drain of the first element. The second element includes a second gate trench structure, a planar gate structure, and a second shielding portion. The first and second gate trench structures extend from the top surface of the epitaxial layer into the epitaxial layer. The planar gate structure is located on the top surface of the epitaxial layer. The first shielding portion is located below the first gate trench structure and in contact with the bottom of the first gate trench structure. The second shielding portion is located below the second gate trench structure and in contact with the bottom of the second gate trench structure. The first shielding portion and the second shielding portion have a second conductivity type.
Description
Technical Field
The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device and a method for forming the same in which devices having different driving current directions are integrated on the same substrate.
Background
The semiconductor industry is continually improving the integration density of different electronic components, allowing more components to be integrated in a given area by continually reducing the minimum device size. For example, a Vertical Diffusion Metal Oxide Semiconductor (VDMOS) is widely used in power switching devices by using a vertical structure design to reduce cell pitch (CELL PITCH) to increase functional density, and by using the back surface of a wafer as the drain electrode and forming the source and gate electrodes of a plurality of transistors on the front surface of the wafer, so that the driving current flows from the planar direction to the vertical direction, and the semiconductor device reaches high reverse withstand voltage and low on-resistance.
As the requirements for electrical performance of semiconductor devices continue to increase, the types and functions of integrated devices have increased to meet the application requirements. For example, a driving device (e.g., having a driving current flowing in a planar direction) and a VDMOS device (e.g., having a driving current flowing in a vertical direction) with different current driving methods can be integrated by packaging. Additional wire bonding (or additional routing) is required to form electrical connections in the package structure to achieve device integration. However, such additional routing or routing creates parasitic inductance between the drive elements and the VDMOS elements in the package structure. If the parasitic inductance is too high, the entire circuit or system may not operate at high frequencies. Thus, while currently existing semiconductor devices are generally adequate and adequate for their intended purposes, they are not entirely satisfactory in all respects.
Disclosure of Invention
Some embodiments of the present invention provide a semiconductor device that can integrate MOS devices with different driving current directions on the same substrate. The semiconductor device comprises a substrate of a first conductivity type, an epitaxial layer formed on the substrate and having the first conductivity type, a first element and a second element, wherein the second element is arranged at a distance from the first element and is electrically connected with the first element. The first element comprises a first gate trench structure and a first shielding portion. The first gate trench structure extends from a top surface of the epitaxial layer into the epitaxial layer, wherein the substrate serves as a drain of the first device. The first shielding part is positioned below the first gate trench structure and is in contact with the bottom of the first gate trench structure, and the first shielding part has the second conductivity type. The second element comprises a second gate trench structure, a planar gate structure and a second shielding portion. The second gate trench structure extends from a top surface of the epitaxial layer into the epitaxial layer, and the planar gate structure is located on the top surface of the epitaxial layer. The second shielding part is positioned below the second gate trench structure and is in contact with the bottom of the second gate trench structure, and the second shielding part has a second conductivity type.
Some embodiments of the present invention provide a method of forming a semiconductor device, including providing a substrate having a first conductivity type, forming an epitaxial layer on the substrate, the epitaxial layer having the first conductivity type, and forming first and second elements at first and second regions of the epitaxial layer, respectively, the second element being disposed apart from and electrically connected to the first element. The first element comprises a first gate trench structure extending from a top surface of the epitaxial layer into the epitaxial layer, wherein the substrate serves as a drain electrode of the first element, and a first shielding portion located below the first gate trench structure and in contact with a bottom of the first gate trench structure, and the first shielding portion has a second conductivity type. The second element comprises a second gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, a planar gate structure located on the top surface of the epitaxial layer, and a second shielding portion located below and in contact with the bottom of the second gate trench structure, and the second shielding portion has a second conductivity type.
Drawings
Fig. 1-10 are schematic cross-sectional views of a semiconductor device at various intermediate stages of fabrication according to some embodiments of the invention.
Reference numerals:
10 semiconductor device
10-1 First element
10-2 Second element
10-3 Third element
100 Substrate
100A,102a,1021a top surface
1121B bottom surface
101 Masking layer
1011 First shielding part
1012, A second shielding part
102 Epitaxial layer
1021 First epitaxial portion
1022 Second epitaxial portion
1041,1043 Current spreading layer
105 Matrix region
106,1061,1062 Well region
108,1081,1082,1083 First heavily doped portion
109,1091,1092,1093 Second heavily doped portion
1081S,1082s,1093s side wall
110 Guard ring
112G-1 first gate trench structure
112G-2 second gate trench structure
112G-3 third gate trench structure
1121 Bottom conductive portion
1122 Top conductive portion
1123 Insulating layer
113 Cover layer
114,1142,1143 Planar gate structure
116,1161,1162,1163 Contact
A1 first region
A2 second region
A3 third region
A G peripheral region
D1 first direction
D2, second direction
D3 third direction
Detailed Description
The following invention provides many embodiments, or examples, for implementing different elements of the provided semiconductor devices. Specific examples of the respective elements and their configurations are described below to simplify the explanation of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit embodiments of the present invention. For example, references to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.
Furthermore, spatially relative terms, such as "under," "above," "over," "above," and other like terms, may be used in the following description to simplify the statement of the relationship as shown between one element or component and another element or component. This spatially relative term includes, in addition to the orientation depicted in the drawings, also the different orientations of the semiconductor device in use or operation. The semiconductor device may be oriented in other directions and the spatially relative descriptions used herein may be construed accordingly.
Some variations of the embodiments are described below. In the various drawings and illustrative embodiments, like reference numerals are used to designate like elements. It will be appreciated that additional steps may be provided before, during, and after the method, and that some of the recited steps may be replaced or deleted for other embodiments of the method.
Embodiments of the present invention provide a semiconductor device and a method for forming the same, which can integrate metal-oxide-semiconductor (MOS) devices with different driving current directions on the same substrate to manufacture a semiconductor device. In some embodiments, a complementary metal oxide semiconductor (complementary MOS; CMOS) device with a driving current flowing in a planar direction and a Vertical Diffusion Metal Oxide Semiconductor (VDMOS) device with a driving current flowing in a vertical direction are integrated on a substrate, and the CMOS device and the VDMOS device have trench gates (TRENCH GATE) are described as examples of the semiconductor device.
Fig. 1-10 are schematic cross-sectional views of a semiconductor device at various intermediate stages of fabrication according to some embodiments of the invention.
Referring to fig. 1, a substrate 100 having a first conductivity type is provided according to some embodiments. The substrate 100 may be a bulk semiconductor substrate, such as a semiconductor wafer. The substrate 100 may be made of silicon or other semiconductor material, such as a silicon wafer. Or the substrate 100 may comprise other elemental semiconductor materials, such as germanium. Furthermore, in some embodiments, the substrate 100 may include a compound semiconductor, such as silicon carbide (SiC), gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 100 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In some embodiments, the substrate 100 may also include a silicon-on-insulator (silicon on insulator; SOI) or other suitable substrate. The SOI substrate may be formed using an oxygen implantation isolation (SIMOX) process, a wafer bonding process, other applicable approaches, or a combination of the foregoing. In some embodiments, the substrate 100 may be composed of different semiconductor materials, such as silicon, silicon germanium, silicon carbide, and the like.
In one example of an application to a semiconductor device including a VDMOS element, such as a vertical trench gate metal oxide semiconductor field effect transistor (VERTICAL TRENCH GATE MOSFET), the substrate 100 is, for example, a wafer doped with dopants of a first conductivity type. The substrate 100 having the first conductivity type may serve as a drain region of a VDMOS device. In this embodiment, the first conductivity type is n-type, but the present invention is not limited thereto. In some other embodiments, the first conductivity type may also be p-type.
Next, an epitaxial growth process is performed on the substrate 100 to form an epitaxial layer 102 (fig. 2), and a shielding layer including a plurality of separated shielding portions is formed in the epitaxial layer 102. Epitaxial layer 102 has the same conductivity type as substrate 100, while masking layer 101 contains a dopant of the opposite conductivity type to epitaxial layer 102. In some embodiments, such as, but not limited to, applications in which a silicon-based (silicon-based) substrate is used for a fabrication process, the epitaxial layer 102 may be formed by continuous epitaxial growth, and dopants may be implanted into the epitaxial layer 102 by an implantation process to form the masking layer 101. In some embodiments, such as, but not limited to, applications in which a fabrication process is performed using a silicon carbide substrate, epitaxial growth may be performed in stages to form epitaxial layer 102, with masking layer 101 formed between the stage growth. In this example, the epitaxial layer 102 is formed in a two-stage epitaxial growth.
As shown in fig. 1, according to some embodiments, an epitaxial growth process is performed on the top surface 100a of the substrate 100 to form a first epitaxial portion 1021 of the epitaxial layer 102. The substrate 100 and the first epitaxial portion 1021 have the same conductive type, for example, the first conductive type. In this example, the substrate 100 and the first epitaxial portion 1021 are n-type. Furthermore, the doping concentration of the first epitaxial portion 1021 of the epitaxial layer 102 is less than the doping concentration of the substrate 100.
In this example, a first element (e.g., a VDMOS element) is formed at a first region A1 of epitaxial layer 102, a second element (e.g., an NMOS element) is formed at a second region A2, and a third element (e.g., a PMOS element) is formed at a third region A3. The NMOS element and the PMOS element are electrically connected to form a CMOS element. Accordingly, a semiconductor device having a VDMOS device and a CMOS device is integrally formed on the same substrate.
After the first epitaxial portion 1021 is formed, a dopant is implanted into the first epitaxial portion 1021 by an implantation process to form a first shielding portion 1011 at the first region A1 and a second shielding portion 1012 at the second region A2 and the third region A3. In this example, as shown in fig. 1, the first shielding portion 1011 and the second shielding portion 1012 extend in a first direction D1 (for example, Y direction) and are spaced apart from each other in a second direction D2 (for example, X direction).
In some embodiments, the separated first and second shields 1011, 1012 have a different conductivity type than the first epitaxial portion 1021, e.g., a second conductivity type. In this example, the first shielding portion 1011 and the second shielding portion 1012 are p-type, which may also be referred to as p-type shielding portions. The dopant of the first shielding portion 1011 and the second shielding portion 1012 may be aluminum (Al), or other suitable dopant. In some embodiments, the doping concentration of the first shielding portion 1011 and the second shielding portion 1012 is, for example (but not limited to), in the range of about 1e16 atoms/cm 3 to about 1e18 atoms/cm 3.
Thereafter, referring to fig. 2, according to some embodiments, epitaxial growth is continued toward the third direction D3 (e.g., Z direction) on the top surface 1021a of the first epitaxial portion 1021 to form a second epitaxial portion 1022. The second epitaxial portion 1022 covers the shielding layer 101 including the first shielding portion 1011 and the second shielding portion 1012. The second epitaxial portion 1022 also has the first conductivity type, e.g., n-type. In this example, the first epitaxial portion 1021 and the second epitaxial portion 1022 together comprise an epitaxial layer 102. The thickness of the epitaxial layer 102 (in the third direction D3) may be adjusted depending on the operating voltage required for the semiconductor device to be actually used.
In some embodiments, epitaxial layer 102 may be formed by metal organic chemical vapor deposition (metal organic chemical vapor deposition; MOCVD), molecular beam epitaxy (molecular beam epitaxy; MBE), hydride vapor phase epitaxy (hydride vapour phase epitaxy; HVPE), liquid phase epitaxy (liquid phase epitaxy; LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable processes, or combinations of the foregoing to perform the epitaxial growth process described above.
Thereafter, a plurality of doped regions required for the respective elements are formed in the epitaxial layer 102.
Referring to fig. 3, in some embodiments of forming a VDMOS device at the first region A1 of the epitaxial layer 102, a current diffusion layer (CSL) 1041 is formed by implanting dopants of the same conductivity type as the epitaxial layer 102 at the first region A1 of the epitaxial layer 102. Further, the current diffusion layer 1041 extends downward from the top surface 102a of the epitaxial layer 102 and contacts the first shielding portion 1011. In this example, the first region A1 of the epitaxial layer 102 includes two first shielding portions 1011 disposed apart in the second direction D2, and the current diffusion layer 1041 further extends between the two first shielding portions 1011. As shown in fig. 3, the bottom surface of the current diffusion layer 1041 is substantially coplanar with the bottom surface of the first shielding portion 1011, for example.
In this example, the current spreading layer 1041 has a first conductivity type, for example n-type. Furthermore, the doping concentration of the current diffusion layer 1041 is greater than that of the epitaxial layer 102, so that electrons can flow from the source electrode to the drain electrode (substrate 100) through the space between the two first shielding portions 1011 during operation of the subsequently manufactured VDMOS device, thereby reducing the resistance of the VDMOS device.
Furthermore, in some embodiments in which the PMOS device is formed at the third region A3 of the epitaxial layer 102, another current diffusion layer 1043 may also be formed at the third region A3 of the epitaxial layer 102. The current spreading layer 1043 also has a first conductivity type, for example n-type. The current diffusion layer 1043 may serve as a channel region of the PMOS element formed at the third region A3. Furthermore, the doping concentration of the current diffusion layer 1043 may be greater than that of the epitaxial layer 102 to further improve the threshold voltage of the PMOS device manufactured later. In this example, the current spreading layer 1043 extends downward from the top surface 102a of the epitaxial layer 102 and contacts the second shielding portion 1012.
According to some embodiments of the present invention, the current diffusion layers 1041 and 1043 may be formed in the same process, and may be formed by simultaneously implanting dopants having a first conductivity type (e.g., n-type) into the epitaxial layer 102, for example, through an ion implantation process.
According to some embodiments, the current diffusion layer 1041 and the current diffusion layer 1043 described above may be formed by a deposition process, a photolithography patterning process, an etching process, and an implantation process. For example, in one example, an oxide hard mask material layer (oxide HARDMASK MATERIAL LAYER) (not shown) may be deposited over the top surface 102a of the epitaxial layer 102, then a patterned photoresist corresponding to the locations of the current spreading layer 1041 and the current spreading layer 1043 may be formed on the oxide hard mask material layer, and the oxide hard mask material layer may be etched according to the patterned photoresist to form an oxide hard mask, after which the patterned photoresist may be removed, and the epitaxial layer 102 may be doped according to the formed oxide hard mask to form the current spreading layer 1041 and the current spreading layer 1043 in the epitaxial layer 102. Then, the oxide hard mask is removed.
Referring to fig. 4, according to some embodiments, a body region 105 is formed in the current spreading layer 1041 of the first region A1. This body region 105 is doped downward from the top surface 102a of the epitaxial layer 102 and extends in the current diffusion layer 1041, for example along the first direction D1. Furthermore, the body region 105 has a different conductivity type from the current diffusion layer 1041.
In this example, a dopant having a second conductivity type, such as a p-type dopant, is implanted at the current diffusion layer 1041 to form the body region 105. Further, in this example, the position of the base region 105 corresponds approximately to an upper portion between the two first shielding portions 1011, for example. And the bottom surface of the base region 105 is spaced apart from the top surface of the first shielding portion 1011 in the third direction D3. Furthermore, according to some embodiments, the body region 105 may be formed by a deposition process, a photolithographic patterning process, an etching process, and an implantation process as described above.
Referring to fig. 5, a well region 106 is formed in the epitaxial layer 102, according to some embodiments. Wherein the depth of the well region 106 is greater than the depth of the body region 105. For example, a well 1061 is formed in the epitaxial layer 102 in the first region A1, and the well 1061 extends from the top surface 102a of the epitaxial layer 102 down to connect with the first mask 1011. Similarly, a well 1062 is formed in the epitaxial layer 102 in the second region A2, and the well 1062 extends from the top surface 102a of the epitaxial layer 102 down to connect with the second mask 1012.
Furthermore, according to some embodiments, the well region 1061 and the well region 1062 include dopants of opposite conductivity type from the epitaxial layer 102. Dopants of a second conductivity type, such as p-type dopants, may be implanted into the epitaxial layer 102 by an implantation process to form the well region 1061 and the well region 1062. As shown in FIG. 5, in this example, the well region 1061 of the first region A1 is adjacent to the current spreading layer 1041 and the well region 1062 of the second region A2 is adjacent to the current spreading layer 1042. In this example, the well region 1062 of the second conductivity type (e.g., p-type) may serve as a channel region for an NMOS device (i.e., second device) formed at the second region A2.
Thereafter, according to some embodiments of the present invention, a plurality of heavily doped portions required for the elements are formed in the respective regions (e.g., the first region A1, the second region A2, and the third region A3), including a plurality of first heavily doped portions 108 and a plurality of second heavily doped portions 109 of different conductivity types, as source regions, drain regions, and base regions of the respective elements (e.g., VDMOS elements, NMOS elements, and PMOS elements included in CMOS elements) to be manufactured.
Referring to fig. 6, a plurality of first heavily doped portions 108 having a first conductivity type are formed according to some embodiments. The first heavily doped portion 108 (e.g., including the first heavily doped portions 1081, 1082 and 1083) may be formed by simultaneously implanting dopants of the first conductivity type into the body region 105, the current spreading layer 1043 and the well region 1062, for example, by an ion implantation process. In this example, such first heavily doped portions 108 have the same first conductivity type as the epitaxial layer 102, e.g., n-type.
In detail, in some embodiments of forming the VDMOS device at the first region A1, a first heavily doped portion 1081 having a first conductivity type (e.g., n-type) is formed in the body region 105 to serve as a source region of the VDMOS device. The first heavily doped portion 1081 extends along the first direction D1 in addition to extending downward from the top surface 102a of the epitaxial layer 102. Furthermore, the depth of the first heavily doped portion 1081 in the vertical direction (e.g., the third direction D3) is smaller than the depth of the body region 105 in the vertical direction (e.g., the third direction D3).
Furthermore, in some embodiments in which the NMOS device is formed at the second region A2, two first heavily doped portions 1082 having the first conductivity type (e.g., n-type) are formed in the well region 1062 to serve as a source region and a drain region of the NMOS device. The first heavily doped portion 1082 extends downward from the top surface 102a of the epitaxial layer 102 and is spaced apart by a distance in the first direction D1. The depth of the first heavily doped portion 1082 in the vertical direction (e.g., the third direction D3) is also smaller than the depth of the well region 1062 in the vertical direction (e.g., the third direction D3).
Furthermore, in some embodiments of forming the PMOS device at the third region A3, a first heavily doped portion 1083 having a first conductivity type (e.g., n-type) is formed in the current diffusion layer 1043 to serve as a base region (bulk region) of the PMOS device. The base region may be adjacent to a subsequently formed source region (e.g., a second heavily doped portion 1093 in fig. 7).
The first heavily doped portion 108 is formed by a method similar to the method for forming the current diffusion layer 1041, the current diffusion layer 1043 and the well region 1062. In some embodiments, the doping concentration of the first heavily doped portion 108 is greater than the doping concentrations of the current diffusion layer 1041 and the current diffusion layer 1043. In some embodiments, the doping concentration of the first heavily doped portion 108 is, for example (but not limited to), in the range of about 1e18 atoms/cm 3 to about 1e21 atoms/cm 3.
Thereafter, referring to fig. 7, according to some embodiments, a second heavily doped portion 109 required for the element is formed in each region. The second heavily doped portions 109 (e.g., including the second heavily doped portions 1091, 1092, and 1093) may be formed by simultaneously implanting dopants of the second conductivity type into the source region (i.e., the first heavily doped portion 1081), the current diffusion layer 1043, and the well region 1062, for example, by an ion implantation process. In this example, such second heavily doped portions 109 have the same second conductivity type as the shielding layer 101, e.g., p-type.
In detail, in some embodiments in which the VDMOS element is formed at the first region A1, a second heavily doped portion 1091 having a second conductivity type (e.g., p-type) is formed in the source region 1081 to serve as a base region of the VDMOS element. Although not shown, such second heavily doped portions 1091 in the source region (i.e., first heavily doped portion 1081) extend downward into contact with the underlying body region 105. Accordingly, the depth of the second heavily doped portion 1091 in the vertical direction (e.g., the third direction D3) of this example is substantially equal to the depth of the first heavily doped portion 1081 in the vertical direction (e.g., the third direction D3).
Furthermore, in some embodiments in which an NMOS element is formed at the second region A2, a second heavily doped portion 1092 having a second conductivity type (e.g., p-type) is formed in the well region 1062 as a base region of the NMOS element. As shown in fig. 7, the second heavily doped portion 1092, which is the base region of the NMOS element, adjoins the first heavily doped portion 1082, which is the source region of the NMOS element.
Furthermore, in some embodiments in which the PMOS device is formed at the third region A3, two second heavily doped portions 1093 having the second conductivity type (e.g., p-type) are formed in the current diffusion layer 1043 to serve as a source region and a drain region of the PMOS device. As shown in fig. 7, the second heavily doped portion 1093, which is the source region of the PMOS element, adjoins the first heavily doped portion 1083, which is the base region of the PMOS element.
In addition, according to some embodiments, a plurality of guard rings (guard rings) 110 are also formed at the periphery of the regions where such elements are formed (e.g., the first region A1, the second region A2, and the third region A3). For example, in the peripheral region a G of the epitaxial layer 102, a dopant having the second conductivity type is implanted into the epitaxial layer 102 by an ion implantation process to form the guard ring 110, thereby preventing the manufactured device from being affected by noise.
The second heavily doped portion 109 and the guard ring 110 may be formed in the same process to have substantially the same ion implantation depth. The second heavily doped portion 109 and the guard ring 110 are formed, for example, by a method similar to the formation method of the current diffusion layer 1041, the current diffusion layer 1043, and the well region 1062 described above. In some embodiments, the doping concentration of the second heavily doped portion 109 and the guard ring 110 is greater than the doping concentration of the shielding layer 101. In some embodiments, the doping concentration of the second heavily doped portion 109 and the guard ring 110 is, for example (but not limited to), in the range of about 1E18 atoms/cm 3 to about 1E21atoms/cm 3.
According to some embodiments, after the first heavily doped portions 108, the second heavily doped portions 109, and the guard ring 110 are formed, a high temperature annealing process is performed to activate the dopants in the respective regions/layers/portions of the epitaxial layer 102. After the high temperature annealing process, the junction (junctions) of such doped regions/layers/portions in epitaxial layer 102 is finalized. The temperature of the high temperature annealing process may depend on the material actually selected for the substrate 100. In some embodiments using a silicon-based substrate 100, a high temperature annealing process is performed, for example, but not limited to, between a temperature range of about 1000 ℃ to about 1200 ℃. In some embodiments using silicon carbide substrate 100, a high temperature annealing process is performed, for example, but not limited to, between a temperature range of about 1600 ℃ to about 1700 ℃.
Thereafter, referring to fig. 8, gate trench structures for individual elements are formed in the respective regions in accordance with some embodiments of the invention. In this example, a first gate trench structure 112G-1 of a first element (e.g., a VDMOS element) is formed at a first region A1, a second gate trench structure 112G-2 of a second element (e.g., an NMOS element) is formed at a second region A2, and a third gate trench structure 112G-3 of a third element (e.g., a PMOS element) is formed at a third region A3.
In some embodiments, the gate trench structures of all elements of the semiconductor device are fabricated simultaneously. Specifically, the first gate trench structure 112G-1, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 are formed in the same process to simplify the process of the semiconductor device of the embodiment. Such gate trench structures extend, for example, from a top surface of epitaxial layer 102 down into epitaxial layer 102. Furthermore, in some embodiments, such gate trench structures are formed as split-GATE TRENCH structures.
As shown in fig. 8, in some examples of forming a VDMOS device having a trench gate at the first region A1, each first gate trench structure 112G-1 includes a bottom conductive portion 1121, a top conductive portion 1122 above the bottom conductive portion 1121, and an insulating layer 1123 electrically isolating the bottom conductive portion 1121 and the top conductive portion 1122. Wherein the insulating layer 1123 encapsulates the sidewalls of the bottom and top conductive portions 1121, 1122 and is positioned between the bottom and top conductive portions 1121, 1122 to electrically isolate the bottom conductive portion 1121 from the top conductive portion 1122.
Furthermore, two first gate trench structures 112G-1 in this example extend in the first direction D1 and are spaced apart from each other in the second direction D2, wherein the first heavily doped portion 1081, the second heavily doped portion 1091 and the body region 105 are located between the two first gate trench structures 112G-1. In this example, opposing sidewalls 1081s of the first heavily doped portion 1081 and opposing sidewalls of the body region 105 contact the insulating layer 1123 of the first gate trench structure 112G-1.
It is noted that, in some embodiments, the bottom of the first gate trench structure 112G-1 contacts the first shielding portion 1011. More specifically, the bottom conductive portion 1121 of the first gate trench structure 112G-1 directly contacts (or is referred to as physically contacting) the first shielding portion 1011 and is electrically connected to the first shielding portion 1011. Furthermore, in some embodiments, the bottom conductive portion 1121 of the first gate trench structure 112G-1 is electrically connected to the source (i.e., the first heavily doped portion 1081) of a first device (e.g., a VDMOS device).
The first gate trench structure 112G-1 may be formed by, for example and without limitation, a deposition process, a photolithographic patterning process, and an etching process to form a trench in the current diffusion layer 1041 (fig. 7). The trenches extend in a first direction D1, and the bottoms of the trenches expose the first shielding portions 1011. Thereafter, an insulating material is formed on the sidewalls and bottom surface of the trench, and a portion of the insulating material may be removed by etching back to form a lower portion of the insulating layer 1123 and expose the first shielding portion 1011. Thereafter, a bottom conductive portion 1121 may be formed by depositing a conductive material and etching back the conductive material, wherein a bottom surface 1121b of the bottom conductive portion 1121 directly contacts the first shielding portion 1011. Thereafter, an insulating material may be formed again in the remaining space of the trench to form an upper portion of the insulating layer 1123 on the upper sidewall of the trench and on the bottom conductive portion 1121, wherein the upper portion of the insulating layer 1123 covers the bottom conductive portion 1121. Thereafter, a top conductive portion 1122 may be formed over the bottom conductive portion 1121 by depositing another conductive material and etching back this conductive material, and the top conductive portion 1122 is separated from the bottom conductive portion 1121 by an insulating layer 1123. Further, in this example, the top conductive portion 1122 is relatively recessed in the trench, and a cap layer 113 (e.g., comprising an oxide or other suitable insulating material) is deposited over the top conductive portion 1122 to cover the top conductive portion 1122, wherein a top surface of the cap layer 113 is substantially coplanar with the top surface 102a of the epitaxial layer 102.
According to some embodiments, the bottom conductive portion 1121 may comprise polysilicon, titanium nitride, other suitable conductive materials, or a combination of the foregoing. The top conductive portion 1122 may comprise polysilicon or other suitable conductive material. And the bottom conductive portion 1121 and the top conductive portion 1122 may comprise the same or different conductive materials. In some embodiments, the insulating layer 1123 may be silicon oxide, or other suitable semiconductor oxide material, or a combination of the foregoing materials. Furthermore, the insulating layer 1123 may be formed by a deposition process, an oxidation process, a combination of the foregoing, or other suitable process. In an example where the epitaxial layer 102 comprises silicon carbide, silicon oxide may be formed by oxidizing silicon carbide on the side and bottom surfaces of the trench by a high temperature process (e.g., using a high temperature furnace) as part of the insulating layer 1123 on the side and bottom surfaces of the trench, and additionally, an oxide layer may be formed, for example, by deposition, on the bottom conductive portion 1121 to cover the top surface of the bottom conductive portion 1121 such that the subsequently formed top conductive portion 1122 may be electrically isolated from the bottom conductive portion 1121.
Furthermore, as shown in fig. 8, in some examples of forming NMOS devices at the second region A2 and forming PMOS devices at the third region A3, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 have the same configuration as the first gate trench structure 112G-1. Each of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 also includes a bottom conductive portion 1121, a top conductive portion 1122 above the bottom conductive portion 1121, and an insulating layer 1123 electrically isolating the bottom conductive portion 1121 and the top conductive portion 1122. The materials and fabrication methods of the relevant components of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 may be referred to the materials and fabrication methods of the first gate trench structure 112G-1 described above, and will not be repeated here.
Furthermore, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 in this example also extend in the first direction D1 and are spaced apart from each other in the second direction D2. The first heavily doped portion 1082, the second heavily doped portion 1092 and the well region 1062 in the second region A2 are located between the two second gate trench structures 112G-2, and opposite sidewalls of the first heavily doped portion 1082, the second heavily doped portion 1092 and the well region 1062 contact the second gate trench structures 112G-2. For example, in the drawings, opposite sidewalls 1082s of the first heavily doped portion 1082 respectively contact the insulating layers 1123 of the second gate trench structure 112G-2. Similarly, the first heavily doped portion 1083, the second heavily doped portion 1093 and the current diffusion layer 1043 in the third region A3 are located between the two third gate trench structures 112G-3, and opposite sidewalls of the first heavily doped portion 1083, the second heavily doped portion 1093 and the current diffusion layer 1043 contact the third gate trench structures 112G-3. For example, opposite sidewalls 1093s of the second heavily doped portion 1093 in the drawing contact the insulating layer 1123 of the third gate trench structure 112G-3, respectively.
Notably, in some embodiments, bottoms of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 contact the second shielding portion 1012. More specifically, the bottom conductive portion 1121 of each of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 is in direct contact (or physical contact) with the second shielding portion 1012 and is electrically connected with the second shielding portion 1012.
According to some embodiments of the present invention, since the shielding layer 101 in the semiconductor device includes the first shielding portion 1011 and the second shielding portion 1012, which are formed in the same process, the first shielding portion 1011 and the second shielding portion 1012 may have substantially the same horizontal height and also substantially the same depth (along the third direction D3) in the epitaxial layer. Since the first gate trench structure 112G-1, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 are also formed by the same process and all of the gate trench structures extend to the corresponding shielding portions below, the first gate trench structure 112G-1, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 have substantially the same vertical depth in the epitaxial layer 102.
Thereafter, referring to fig. 9, in accordance with some embodiments, a planar gate structure 114 is further formed in the region of the non-vertical semiconductor element. For example, a planar gate structure 1142 of a second device (e.g., an NMOS device) is formed at the second region A2, and a planar gate structure 1143 of a third device (e.g., a PMOS device) is formed at the third region A3.
In some embodiments, the top conductive portion 1122 of the second gate trench structure 112G-2 at the second region A2 is electrically connected to the upper planar gate structure 1142, and the bottom conductive portion 1121 of the second gate trench structure 112G-2 is electrically connected to the lower second shielding portion 1012.
In some embodiments, the top conductive portion 1122 of the third gate trench structure 112G-3 at the third region A3 is electrically connected to the upper planar gate structure 1143, and the bottom conductive portion 1121 of the third gate trench structure 112G-3 is electrically connected to the lower second shielding portion 1012.
In some embodiments, each of planar gate structures 1142 and 1143 includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. To clearly show the relative configuration of the planar gate and the underlying doped regions, the gate dielectric layers in planar gate structures 1142 and 1143 are omitted from fig. 9, and only the gate electrode is shown.
The gate dielectric layer may be silicon oxide or other suitable dielectric material. The gate electrode may comprise polysilicon or other suitable conductive material. A layer of dielectric material (not shown) may be formed on epitaxial layer 102 by a deposition process, such as a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or a thermal oxidation process. Thereafter, a conductive material (not shown) is deposited on the dielectric material layer, and the deposition process may be a physical vapor deposition process, a chemical vapor deposition process, or other suitable process. The dielectric material layer and the conductive material may then be patterned by a photolithography process and an etching process to form the gate dielectric layer and the gate electrode of the planar gate structures 1142 and 1143.
Furthermore, as shown in fig. 9, in some examples of forming the NMOS device at the second region A2, the first heavily doped portions 1082 as the source region and the drain region are spaced apart in the first direction D1 and correspond to opposite sides of the planar gate structure 1142, respectively. More specifically, two second gate trench structures 112G-2 are disposed apart in the second direction D2, and a planar gate structure 1142 and a first heavily doped portion 1082 (as a source region and a drain region) are located between the second gate trench structures 112G-2. Wherein the first heavily doped portion 1082 extends between the second gate trench structures 112G-2, e.g., opposite sidewalls 1082s of the first heavily doped portion 1082 contact the second gate trench structures 112G-2, respectively. In some embodiments, one set of opposing sidewalls of planar gate structure 1142 extends in the first direction D1, while the other set of opposing sidewalls of planar gate structure 1142 corresponds to the first heavily doped portions 1082 as source and drain regions, respectively.
Thus, in accordance with some embodiments of the present invention, a second element (e.g., an NMOS element) formed at the second region A2 has not only the planar gate structure 1142 but also the second gate trench structure 112G-2. Thus, in embodiments, the non-vertical semiconductor devices integrated with the first device (e.g., a VDMOS device) each have multiple gates and multiple channels, such as the tri-gate structure (tri-gate structure) shown in the second device (e.g., an NMOS device) in this example, including two second gate trench structures 112G-2 and one planar gate structure 1142, thus having three channels.
Similarly, a third element (e.g., a PMOS element) formed at the third region A3 has a planar gate structure 1143 and a third gate trench structure 112G-3. Thus, the third device integrated with the first device (e.g., VDMOS device) also has multiple gates and multiple channels. For example, three gate structures (including two third gate trench structures 112G-3 and one planar gate structure 1143) are shown in this example, and three channels may be formed.
Thereafter, referring to fig. 10, after forming planar gate structures 1142 and 1143, an interlayer dielectric layer is formed over epitaxial layer 102 to cover epitaxial layer 102, the plurality of first and second heavily doped portions 108 and 109, well region 1062, guard ring 110, first gate trench structure 112G-1, second gate trench structure 112G-2, third gate trench structure 112G-3, planar gate structure 1142, and planar gate structure 1143, in accordance with some embodiments. Thereafter, a plurality of contacts 116 are formed in the interlayer dielectric layer.
The gate dielectric layers (only the gate electrode is shown) in planar gate structures 1142 and 1143 and the interlayer dielectric layers are omitted from fig. 10 for clarity of illustration of the relative configuration of planar gate structure 114, contact 116 and underlying doped regions.
In some embodiments, the interlayer dielectric layer may be silicon oxide, or other suitable low-k dielectric material, or a combination of the foregoing. In some embodiments, the material of the interlayer dielectric layer is different from the material of the insulating layer 1123 of the gate trench structure. In some other embodiments, the material of the interlayer dielectric layer is the same as the material of the insulating layer 1123 of the gate trench structure. Furthermore, an interlayer dielectric layer may be deposited over the epitaxial layer 102 by a deposition process. In some embodiments, the deposition process described above may be a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, other suitable process, or a combination of the preceding.
Thereafter, according to some embodiments, portions of the interlayer dielectric layer may be removed by a photolithographic patterning process and etching process to form contact holes (not shown), wherein the bottoms of the contact holes expose underlying respective conductive portions, such as source, drain and body regions. The photolithographic patterning process described above includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing.
Thereafter, according to some embodiments, the contact holes in the regions are filled with a suitable conductive material to form contacts 116.
As shown in fig. 10, in some embodiments, a contact 1161 of a first element 10-1 (e.g., a VDMOS element) located in the first region A1 electrically connects the first heavily doped portion 1081 (source region) and the second heavily doped portion 1091 (base region). In some embodiments, since the second heavily doped portion 1091 is connected to the underlying body region 105, the source and base of the first element 10-1 are electrically connected, and the first and second heavily doped portions 1081, 1091 are equipotential when the element is operated. In other words, the contacts 1161 of the first device 10-1 are electrically connected to the source.
Furthermore, in some embodiments, the contacts 1162 of the second device 10-2 (e.g., NMOS device) in the second region A2 are electrically connected to the first heavily doped portion 1082 (e.g., with n+ dopant) as the source region and the drain region, and to the second heavily doped portion 1092 (e.g., with p+ dopant) as the base region, respectively. Wherein the source and base of the second element 10-2 are electrically connected since the second heavily doped portion 1092, which is the base region of the NMOS element, is adjacent to the first heavily doped portion 1082, which is the source region, and the second heavily doped portion 1092, which is the base region, are equipotential when the element operation is performed.
Similarly, in some embodiments, contacts 1163 of the third element 10-3 (e.g., PMOS element) located in the third region A3 are electrically connected to the first heavily doped portion 1083 (e.g., with n+ dopant) as the base region and to the second heavily doped portion 1093 (e.g., with p+ dopant) as the source and drain regions, respectively. Wherein the source and base of the third element 10-3 are electrically connected since the first heavily doped portion 1083 as the base region of the PMOS element adjoins the second heavily doped portion 1093 as the source region, the second heavily doped portion 1093 as the source region and the first heavily doped portion 1083 as the base region are equipotential when the element operation is performed.
Furthermore, the contact 116 may have a single-layer or multi-layer structure. In some embodiments, the contact 116 includes a contact barrier layer and a contact conductive layer. The contact barrier layer is formed on the sidewall and bottom of the contact hole to form a barrier liner layer, and the contact conductive layer fills the remaining space in the contact hole. The drawings illustrated herein, as shown in fig. 2, show only the contacts 116 in a single layer structure to simplify the drawing. Further, in some examples, the top surfaces of contacts 116 (including the top surfaces of the contact barrier layer and the top surfaces of the contact conductive layer, if any) are substantially coplanar with the top surfaces of the interlayer dielectric layer (not shown).
In some examples, a barrier material (not shown) may be formed on the interlayer dielectric layer by a deposition process, and isotropically deposited in the contact holes, and a conductive material (not shown) may be deposited over the barrier material layer, and fills the remaining spaces in the contact holes. The contact 116 is then formed, for example, by etching or other suitable means to remove excess portions of the conductive and barrier materials above the interlayer dielectric layer to form a contact barrier layer and a contact conductive layer in the contact hole.
Materials that may be used as contact barrier for the contacts 116 include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP), ruthenium (Ru), aluminum oxide (Al 2O3), magnesium oxide (MgO), aluminum nitride (AlN), tantalum pentoxide (Ta 2O5), silicon dioxide (SiO 2), hafnium oxide (HfO 2), zirconium dioxide (ZrO 2), magnesium fluoride (MgF 2), calcium fluoride (CaF 2), other suitable barrier materials, or combinations thereof. In some embodiments, the contact barrier layer may be formed by a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, other suitable processes, or combinations of the preceding.
In some embodiments, the conductive material that may be the contact conductive layer of the contact 116 includes tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NICKEL SILICIDE; niSi), cobalt silicide (CoSi), tantalum carbide (tantulum carbide; taC), tantalum silicon nitride (tantulum SILICIDE NITRIDE; taSiN), tantalum carbonitride (tantalum carbide nitride; taCN), titanium aluminide (titanium aluminide; tiAl), titanium aluminum nitride (titanium aluminide nitride; tiAlN), other suitable metals, or combinations of the foregoing. Furthermore, in some embodiments, the contact conductive layer may be formed by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, other suitable processes, or a combination thereof.
In some embodiments, contacts 116 for all elements of semiconductor device 10 are fabricated simultaneously. Specifically, the contact 1161 of the first element 10-1 (e.g., a VDMOS element) in the first region A1, the contact 1162 of the second element 10-2 (e.g., an NMOS element) in the second region A2, and the contact 1163 of the third element 10-3 (e.g., a PMOS element) in the third region A3 are formed in the same process to simplify the process of the semiconductor device 10 of the embodiment.
Subsequent processing of the other components of semiconductor device 10 is performed after formation of contacts 116. According to some embodiments, a metal layer (not shown) is formed over the interlayer dielectric layer and the contacts 116. The metal layer covers the contact 116 and is in physical and electrical contact with the contact 116, so that the metal layer is electrically connected to, for example, the first heavily doped portion 108, the second heavily doped portion 109, the body region 105, and the well region 1062 through the contact 116.
In some embodiments, the metal layer may comprise copper, silver, gold, aluminum, tungsten, other suitable metal materials, or combinations of the foregoing. In some embodiments, the material of the metal layer is the same as the material of the contact 116. In some other embodiments, the material of the metal layer is different from the material of the contact 116. According to some embodiments, a metal layer may be formed on the contact 116 through a deposition process. In some embodiments, the deposition process described above may be a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination of the foregoing. After the metal layer is formed, a process of the semiconductor device 10 is completed.
According to some embodiments, the semiconductor device 10 may include a first element 10-1, such as a VDMOS element, a second element 10-2, such as an NMOS element, and a third element 10-3, such as a PMOS element, wherein the NMOS element is electrically connected to the PMOS element to form a Complementary Metal Oxide Semiconductor (CMOS) element. The CMOS device can be used as a switching device for controlling the VDMOS device to turn on or off the VDMOS device. In one non-limiting example, in a CMOS device, the NMOS device is interconnected with the drain of the PMOS device, while the gate of the VDMOS device is electrically connected to the drain of the CMOS device.
In summary, the semiconductor device according to the embodiments of the present invention can realize the devices including different driving current flowing directions on the same substrate, for example, a semiconductor device including a VDMOS device (having a driving current flowing in a vertical direction) and a CMOS device (having a driving current flowing in a planar direction). In high power device applications, the VDMOS device is a high power device, and the CMOS device may be used as a driver for the VDMOS device. The semiconductor device of the embodiment has many advantages. For example, the integrated (monolithic) semiconductor device according to the present embodiment can effectively reduce parasitic inductance between the VDMOS device and the driving circuit of the CMOS device (control device) compared to the conventional package method in which different functional devices are combined to generate excessive parasitic inductance. The reduction in parasitic inductance may increase the operating frequency of the overall circuit or system. In addition, if in some embodiments of semiconductor devices fabricated using silicon carbide epitaxy, the device operation may be performed at higher temperatures.
Furthermore, in accordance with some embodiments of the present invention, each element in the semiconductor device includes a split gate trench structure. For the VDMOS device of the embodiment, the split gate of the first gate trench structure 112G-1 can reduce parasitic capacitance of the gate-drain and increase switching speed of the VDMOS device. For the CMOS element of the semiconductor device of the embodiment, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 fabricated simultaneously with the first gate trench structure 112G-1 can simplify the process and increase the number of channels of the CMOS element. For example, in the above example, the NMOS element formed at the second region A2 and the PMOS element formed at the third region A3 have three gates and three channels, respectively. Compared with the traditional planar grid CMOS element, the CMOS element of the embodiment can construct more channels under the condition of the same area, the channel density is improved, and more current can be generated when the element is operated, so that the operation speed is improved.
Furthermore, the shielding layer 101 of the semiconductor device according to some embodiments of the present invention can provide good protection effect for the device. For example, the first shielding portion 1011 formed at the first region A1 is located at the bottom of the first gate trench structure 112G-1 of the VDMOS device, so as to prevent the gate insulating layer in the gate trench structure from being damaged by the high-intensity electric field. For example, the second shielding portion 1012 formed at the second region A2 and the third region A3 is located under the CMOS device and covers the relevant well region of the CMOS device and the bottom of the gate trench structure (including the second gate trench structure 112G-2 and the third gate trench structure 112G-3), thereby serving as a good isolation layer of the CMOS device in the epitaxial layer 102.
Furthermore, in the conventional planar CMOS device (without gate trench structure), pins are disposed on the top surface of the epitaxial layer, and accumulated charges of the isolation layer embedded in the epitaxial layer can only be conducted out through the well region between the isolation layer and the surface pins, and no conductor is directly connected to the isolation layer and the surface pins, so that the conducting path of accumulated charges is longer, and the capability of removing charges is weaker. While the bottoms (e.g., bottom conductive portions 1121) of the gate trench structures (e.g., first gate trench structure 112G-1, second gate trench structure 112G-2, and third gate trench structure 112G-3) of the respective elements are in direct contact with and electrically connected to the shielding layer 101, the shielding layer 101 contains dopants having a second conductivity type (e.g., p-type), and the shielding layer 101 may be grounded through a connection (not shown) according to some embodiments of the present invention. Therefore, if charges are accumulated at the bottom conductive portion 1121 when the semiconductor device of the embodiment is operated, the shielding layer 101 in direct contact with the bottom conductive portion 1121 can rapidly conduct out the accumulated charges. Therefore, the semiconductor device of the embodiment has better capability of removing charge interference.
According to some embodiments of the method of manufacturing, as illustrated in the above steps, for the devices in different regions, the first device (e.g., VDMOS device) is formed in the first region A1, the second device (e.g., NMOS device) is formed in the second region A2, and the third device (e.g., PMOS device) is formed in the third region A3, and thus, since many related components of the CMOS device of the embodiment can be manufactured simultaneously with the components of the VDMOS device, only slightly modified process steps, such as adding two additional masks to manufacture the well region 1062 of the NMOS device (fig. 5) and to manufacture the planar gate structure 114 of the NMOS device/PMOS device (fig. 9), can be manufactured.
Claims (25)
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