CN121237143A

CN121237143A - Pseudo-static random access memory and its access methods, I/O interfaces, electronic devices

Info

Publication number: CN121237143A
Application number: CN202511814025.XA
Authority: CN
Inventors: 刘星; 李杨
Original assignee: Xi'an Xincun Semiconductor Co ltd
Current assignee: Xi'an Xincun Semiconductor Co ltd
Priority date: 2025-12-03
Filing date: 2025-12-03
Publication date: 2025-12-30
Anticipated expiration: 2045-12-03
Also published as: CN121237143B

Abstract

This disclosure relates to pseudo-static random access memory and its access method, I/O interface, and electronic device. The I/O interface includes: first and second sets of data terminals for first and second interface protocols, respectively, with the second set having more terminals than the first set; a set of control terminals for the first and second interface protocols; a mode register cache configured to cache mode register values input via a first portion of the first set of data terminals or the first set of control terminals, wherein at least one bit is used as an interface protocol selection signal; and a control logic unit including first and second control logic modules for instruction decoding according to the first and second interface protocols, respectively, and configured to decode instruction values using the corresponding control logic modules according to the interface protocol selection signal. The I/O interface of this disclosure is compatible with two interface protocols, one of which supports a larger data width, achieves higher bandwidth, and allows protocol switching via a protocol selection signal, making it suitable for a wider range of application scenarios.

Description

Pseudo-static random access memory, access method thereof, IO interface and electronic equipment

Technical Field

The present disclosure relates to the field of storage, and in particular, to a pseudo static random access memory (Pseudo Static Random Access Memory, PSRAM) and an access method thereof, an IO (Input/Output) interface, an electronic device including the same, and the like.

Background

With the development of such as multimedia, artificial intelligence, and high-speed communication scenarios, the demands for electronic devices and systems performance continue to increase, and PSRAM, which is a low-power memory, is increasingly in demand for high bandwidth.

Thus, it is desirable to provide PSRAM with higher bandwidth.

Disclosure of Invention

One technical problem to be solved by the present disclosure is to provide a pseudo-static random access memory with a higher bandwidth.

According to a first aspect of the present disclosure, there is provided an IO interface for a pseudo-static random access memory selectively operating in a first interface protocol mode or a second interface protocol mode, the IO interface comprising:

A first set of data terminals for the first interface protocol;

A second set of data terminals for the second interface protocol having a number of terminals greater than the number of terminals of the first set of data terminals;

a set of control terminals for the first and second interface protocols;

A mode register buffer configured to buffer a mode register value input via the first set of data terminals or via a first portion of terminals of the set of control terminals, wherein at least one bit of the mode register value is used as an interface protocol selection signal;

And a control logic section including a first control logic module and a second control logic module that perform instruction decoding according to the first interface protocol and the second interface protocol, respectively, and configured to perform instruction decoding processing on instruction values input via the first group of data terminals or via the first partial terminals with a corresponding one of the first control logic module and the second control logic module according to the interface protocol selection signal.

Optionally, the first set of data terminals is configured to transmit access data, instruction values, address values, and mode register values in a time-sharing manner according to the first interface protocol, and the second set of data terminals is configured to transmit only access data according to the second interface protocol.

Optionally, the set of control terminals includes a first subset of control terminals for transmitting control signals other than the instruction value, the address value, and the mode register value required for the first interface protocol, and a second subset of control terminals for transmitting all control signals required for the second interface protocol, wherein the second subset of control terminals includes an instruction/address multiplexing terminal for time-sharing transmission of the instruction value, the address value, and the mode register value according to the second interface protocol as the first partial terminal;

The mode register value and the instruction value are both input via the first set of data terminals in case the IO interface is operating in the first interface protocol mode, and the mode register value and the instruction value are both input via the instruction/address multiplexing terminal in case the IO interface is operating in the second interface protocol mode.

Optionally, at least part of the first set of data terminals is further for time-sharing transmission of instruction values, address values and mode register values according to the second interface protocol;

The set of control terminals includes a first subset of control terminals for transmitting control signals other than command values, address values, and mode register values required by the first interface protocol, the first subset of control terminals also being for transmitting at least a portion of the control signals other than command values, address values, and mode register values required by the second interface protocol;

in the case where the IO interface operates in the first interface protocol mode and the second interface protocol mode, the mode register value and the instruction value are both input via the first set of data terminals.

Optionally, the first control logic module is configured to receive a first instruction/address value and a first clock signal, and according to the first interface protocol and the first clock signal, perform instruction decoding on an instruction value extracted from the first instruction/address value to obtain a first internal operation signal, and extract an address value from the first instruction/address value as the first address signal.

Optionally, the second control logic module is configured to receive a second instruction/address value, a second clock signal and a mode register value of a specified portion, and according to the second interface protocol and the second clock signal, to perform instruction decoding on an instruction value extracted from the second instruction/address value in combination with the mode register value of the specified portion to obtain a second internal operation signal, and to extract an address value from the second instruction/address value as a second address signal.

Optionally, in a first case where the first set of data terminals are used to time-share access data, command values, address values and mode register values according to the first interface protocol, and the first portion of terminals are used to time-share instruction values, address values and mode register values according to the second interface protocol, the first command/address values are sets of values obtained by sampling the inputs of the first set of data terminals at a first set of clock edges, the second command/address values are sets of values obtained by sampling the inputs of the first portion of terminals at a second set of clock edges, or in a second case where the first set of data terminals are used to time-share access data, command values, address values and mode register values according to the first interface protocol, and at least some of the first set of data terminals are also used to time-share instruction values, address values and mode register values according to the second interface protocol, the first command/address values and the second command/address values are sets of values obtained by sampling the inputs of the first set of data at a third set of clock edges and a fourth set of clock edges, respectively;

the first clock signal and the second clock signal are respectively input by a first clock terminal and a second clock terminal of the set of control terminals for respectively transmitting clock signals required by the first interface protocol and the second interface protocol, or are respectively input by clock terminals of the set of control terminals multiplexed with the clock signals required by the first interface protocol and the second interface protocol.

Optionally, the first control logic module includes:

A first instruction decoder configured to decode the first instruction/address value according to the first interface protocol to obtain a first decoded signal,

A first clock gating unit configured to convert the first clock signal into a first instruction clock signal and a first address clock signal according to the first interface protocol, which indicate sampling instants of instruction values and address values in the first instruction/address values, respectively,

A first internal operation signal buffer unit configured to sample and buffer the first decoding signal as the first internal operation signal at a timing indicated by the first instruction clock signal, and

A first address buffer unit configured to sample and buffer the first instruction/address value as the first address signal at a timing indicated by the first address clock signal.

Optionally, the second control logic module includes:

A second instruction decoder configured to decode the second instruction/address value in combination with the mode register value of the specified portion according to the second interface protocol to obtain a second decoded signal,

A second clock gating unit configured to convert the second clock signal into a second instruction clock signal and a second address clock signal according to the second interface protocol, which indicate sampling instants of instruction values and address values in the second instruction/address values, respectively,

A second internal operation signal buffer unit configured to sample and buffer the second decoding signal as the second internal operation signal at a timing indicated by the second instruction clock signal, and

And a second address buffer unit configured to sample and buffer the second instruction/address value as the second address signal at a timing indicated by the second address clock signal.

Optionally, in a case where the first set of data terminals is used for time-sharing transmission of access data, instruction values, address values and mode register values according to the first interface protocol, at least part of the first set of data terminals is also used for time-sharing transmission of instruction values, address values and mode register values according to the second interface protocol, and clock terminals of the set of control terminals are multiplexed with clock signals required for transmission of the first interface protocol and the second interface protocol, the control logic section further comprises:

a first demultiplexer having an input terminal receiving an instruction/address value obtained by sampling an input of the first set of data terminals at a third or fourth set of clock edges, a control terminal receiving the interface protocol selection signal, and two output terminals outputting the first and second instruction/address values, respectively, and

And a second demultiplexer whose input terminal receives the clock signal input from the clock terminal, whose control terminal receives the interface protocol selection signal, and whose two output terminals output the first clock signal and the second clock signal, respectively.

Optionally, the control logic further comprises:

an output module configured to receive the first internal operation signal, the second internal operation signal, the first address signal, and the second address signal, and output a final internal operation signal equal to one of the first internal operation signal and the second internal operation signal corresponding to the interface protocol selection signal and a final address signal equal to one of the first address signal and the second address signal corresponding to the interface protocol selection signal.

Optionally, in case the final internal operation signal indicates that a mode register write operation is performed, at least part of the final address signal is buffered into the mode register buffer as the latest mode register value.

Optionally, the control logic further comprises:

a first switch located between the first control logic module and a supply voltage for the first control logic module;

A second switch between the second control logic module and the power supply voltage used by the second control logic module, and

And the power supply control module is configured to output the interface protocol selection signal and the reverse phase signal thereof to the control ends of the first switch and the second switch respectively, so that the first switch is turned on and the second switch is turned off when the interface protocol selection signal indicates that the first interface protocol is currently selected, and the second switch is turned on and the first switch is turned off when the interface protocol selection signal indicates that the second interface protocol is currently selected.

Optionally, the IO interface further includes an IO buffer coupled to the first set of data terminals, the second set of data terminals, and the set of control terminals, and including a plurality of receivers for receiving signals input on the first set of data terminals, the second set of data terminals, and the set of control terminals, respectively, and a plurality of drivers for driving signals output on portions of the first set of data terminals, the second set of data terminals, and the set of control terminals, respectively.

Optionally, the IO buffer part is configured to shut down a receiver and/or a driver for an idle terminal according to the interface protocol selection signal, wherein the idle terminal is a terminal not used for transmitting a signal required by an interface protocol corresponding to the interface protocol selection signal.

Optionally, the IO interface further includes:

An internal access data bus for transferring access data between a memory array within the pseudo-static random access memory and the first set of data terminals and between the memory array and the second set of data terminals, the number of bits being equal to the number of terminals of the second set of data terminals, and

An access data IO section configured to splice a plurality of write data sampled at a fifth set of clock edges to input of the first set of data terminals into one internal write data to be output to the internal access data bus at the same timing, and split one internal read data received via the internal access data bus at the same timing into a plurality of read data to be output via the first set of data terminals in a plurality of times.

Optionally, the first set of data terminals transmit the read data and the write data using DDR timing, and the access data IO section includes:

a write driver configured to splice two write data obtained by sampling the input of the first group of data terminals at consecutive two clock edges of the fifth group of clock edges into one intermediate write data for output at the same timing;

A data interface configured to splice a plurality of the intermediate write data that are continuously output into the one internal write data;

a read data caching module configured to cache the one internal read data;

A read data multiplexer configured to split the buffered internal read data into a plurality of intermediate read data which are sequentially output, wherein the number of bits of the intermediate read data is twice the number of terminals of the first set of data terminals, and

A read driver configured to split one of the intermediate read data into two of the read data for respective output at two consecutive clock edges via the first set of data terminals.

Optionally, the set of control terminals comprises a first subset of control terminals for transmitting only at least part of the control signals required for the first interface protocol and a second subset of control terminals for transmitting only at least part of the control signals required for the second interface protocol, or the set of control terminals comprises at least one control terminal multiplexed with the first and second interface protocols.

Optionally, at least part of the first set of data terminals is also used for transmitting at least part of the control signals and/or access data required by the second interface protocol, or at least part of the second set of data terminals is also used for transmitting at least part of the control signals and/or access data required by the first interface protocol.

Optionally, the first interface protocol is xSPI protocols, and the second interface protocol is LPDDR protocols.

Optionally, the first set of data terminals has a terminal number of 8 and the second set of data terminals has a terminal number of 64.

According to a second aspect of the present disclosure, there is provided a pseudo-static random access memory, including the IO interface according to any one of the first aspect, a memory array, and an access processing section configured to perform a corresponding access operation on the memory array according to a result of instruction decoding processing performed by the control logic section in the IO interface.

According to a third aspect of the present disclosure, there is provided a method for accessing a pseudo static random access memory according to any one of the second aspects, comprising receiving the mode register values via the first set of data terminals or the first portion of terminals, receiving the instruction values via the first set of data terminals or the first portion of terminals, performing instruction decoding processing on the instruction values with a corresponding one of the first control logic module and the second control logic module according to the interface protocol selection signals in the mode register values, and performing corresponding access operations on the memory array with the access processing portion according to the result of the instruction decoding processing.

According to a fourth aspect of the present disclosure there is provided an electronic device comprising a pseudo-static random access memory according to any of the above second aspects, and a first host coupled to the first set of data terminals in the IO interface in the pseudo-static random access memory and a first subset of control terminals of the set of control terminals for transmitting control signals required for the first interface protocol, and configured to input the mode register value to the IO interface via the first set of data terminals or the first partial terminal when accessing the pseudo-static random access memory such that the interface protocol selection signal indicates that the first interface protocol mode is currently selected.

Optionally, the electronic device further includes:

A second host coupled to the second set of data terminals in the IO interface and a second subset of control terminals in the set of control terminals for transmitting control signals required for the second interface protocol and configured to input the mode register value to the IO interface via the first set of data terminals or the first portion of terminals when accessing the pseudo-static random access memory such that the interface protocol selection signal indicates that the second interface protocol mode is currently selected;

the first host and the second host respectively further comprise a first occupation state terminal and a second occupation state terminal, the first occupation state terminal and the second occupation state terminal are coupled together and used for interacting occupation states of the pseudo-static random access memory between the first host and the second host, so that the first host and the second host can access the pseudo-static random access memory in a time sharing mode.

Therefore, the IO interface design of the embodiment of the disclosure is compatible with two interface protocols, wherein one interface protocol can support larger data width, so that higher bandwidth can be realized, and switching between the interface protocols can be performed through the protocol selection signal, so that the IO interface design is suitable for wider application scenes.

Drawings

The foregoing and other objects, features and advantages of the disclosure will be apparent from the following more particular descriptions of exemplary embodiments of the disclosure as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout exemplary embodiments of the disclosure.

Fig. 1 illustrates an exemplary composition schematic of a PSRAM and IO interfaces therein according to some embodiments of the present disclosure.

Fig. 2 illustrates an exemplary composition schematic of a PSRAM and IO interfaces therein according to some embodiments of the present disclosure.

Fig. 3 illustrates an exemplary composition schematic of a control logic according to some embodiments of the present disclosure.

Fig. 4 illustrates an exemplary composition schematic of a control logic according to some embodiments of the present disclosure.

Fig. 5 illustrates an exemplary composition schematic of an IO buffer, according to some embodiments of the present disclosure.

Fig. 6 illustrates an exemplary composition schematic of an access data IO section according to some embodiments of the present disclosure.

Fig. 7 illustrates an exemplary schematic diagram of a PSRAM and a host accessing the PSRAM according to some embodiments of the present disclosure.

Fig. 8 illustrates an exemplary flowchart of a method of accessing PSRAM according to some embodiments of the present disclosure.

Fig. 9 illustrates an exemplary composition schematic of an electronic device according to some embodiments of the present disclosure.

Detailed Description

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The highest performance of the current general PSRAM is an operating frequency of 200M, and an IO (Input/Output) interface which operates according to SPI (SERIAL PERIPHERAL INTERFACE ) protocol is usually adopted. In the case of DDR (Double Data Rate) timing and x8 IO interface (i.e. the Data width of the IO interface is 8 and the Data received in parallel is 8 bits), the bandwidth is 400MBps at maximum, and in the case of DDR timing and x16 IO interface, the bandwidth is 800MBps at maximum, which cannot meet the current requirements of some high performance application scenarios for PSRAM. Herein, "SPI protocol" includes various extended serial peripheral interface protocols, such as multi-IO SPI protocol, including QSPI (Quad SERIAL PERIPHERAL INTERFACE, four-wire serial peripheral interface), OSPI (Octal SERIAL PERIPHERAL INTERFACE, eight-wire serial peripheral interface), xSPI (eXtended SERIAL PERIPHERAL INTERFACE ) protocol, and the like.

Therefore, the embodiment of the disclosure proposes a new IO interface design for PSRAM, which is compatible with two interface protocols, wherein one interface protocol can support a larger data width, thereby realizing a higher bandwidth, and can also switch between the interface protocols through a protocol selection signal, thereby being suitable for a wider application scenario.

For example, the IO interface according to the embodiments of the present disclosure may operate in a mode of an interface protocol (such as an SPI protocol) originally used by the PSRAM, or may operate in a mode of an interface protocol supporting a larger data width (such as an LPDDR (Low Power Double Data Rate, low power double data rate) protocol), so that a user may select to use an instruction format and an interface protocol originally used by the PSRAM in a general application scenario, and select to use an interface protocol having a larger data width in a high bandwidth application scenario to achieve a larger bandwidth. Therefore, the high-bandwidth performance can be realized on the PSRAM product form, and meanwhile, the application interface protocol originally supported by the PSRAM is reserved through mode switching.

In some embodiments, as described later, the IO interface according to the embodiments of the present disclosure may also support two hosts that employ different interface protocols to access the same PSRAM at the same time, so as to be applicable to more and more complex application scenarios.

The technical solution of the present disclosure will be described in detail below by taking an IO interface compatible with a xSPI protocol having a data width of 8 (corresponding to the first interface protocol described herein) and an LPDDR protocol having a data width of 64 (corresponding to the second interface protocol described herein) as an example, but it will be understood by those skilled in the art that the present disclosure is not limited thereto, but can be similarly applied to IO interfaces compatible with other two different interface protocols, and the data widths adopted by the two interface protocols are also merely exemplary and can be modified as needed.

Fig. 1 and 2 respectively show exemplary constituent diagrams of two PSRAMs and an IO interface therein according to an embodiment of the present disclosure, and the main difference between the two is that the IO interface of fig. 1 provides two sets of terminals for two interface protocols respectively, and the second interface protocol of the IO interface of fig. 2 multiplexes at least part of the terminals of the first interface protocol. The PSRAM and IO interfaces therein of the embodiments of the present disclosure are discussed in detail below in conjunction with fig. 1 and subsequent figures, and the differences between the terminal multiplexing embodiment and the terminal independent embodiment of fig. 1, for example, are described in conjunction with fig. 2.

As shown in fig. 1, the PSRAM includes an IO interface that selectively operates in a first interface protocol mode or a second interface protocol mode, and thus, the IO interface includes terminals for implementing two interface protocols. Those skilled in the art will appreciate that the terminals, portions or modules in the IO interface of fig. 1 are merely exemplary and not limiting, and may be increased or decreased or modified as appropriate in actual use.

In the example shown in fig. 1, for example, the first interface protocol is xSPI protocol, the second interface protocol is LPDDR protocol, and the two interface protocols use two sets of terminals that are independent of each other, for example, one set of terminals for the first interface protocol shown on the far right side of fig. 1, and one set of terminals for the second interface protocol shown on the far top side of fig. 1.

Each set of terminals may be divided into a data portion for transmitting at least access data (i.e., read data and write data) and a control portion for transmitting all control signals required by the corresponding interface protocol except for the signals transmitted by the data portion terminals. Herein, the "control signal" refers to signals required for the corresponding interface protocol other than access Data, for example, an instruction (Command) value, an address value (i.e., an address to which access Data corresponds), a Mode Register (Mode Register) value, a Clock (CLK) signal, a chip select (CHIP SELECT, CS) signal, a Data Strobe (DQS) signal, a Data Mask (Data Mask, DM) signal, a reset signal, and the like.

The data portion terminals for the first interface protocol may also be referred to as a first set of data terminals. In case the first interface protocol is xSPI protocol or similar, the first set of data terminals is used for time-sharing transmission of access data, instruction values, address values and mode register values according to the first interface protocol. That is, access data, instruction values, and address values according to the first interface protocol are time-division multiplexed with the same set of terminals for transmission. In addition, in the instruction format of the write mode register, the instruction value and the mode register value are also time-multiplexed and transmitted through the same set of terminals. In the example of FIG. 1, terminals A/DQ [7:0] may be used as the first set of data terminals, with a terminal number of 8.

The data portion terminals for the second interface protocol may also be referred to as a second set of data terminals, which have a larger number of terminals than the first set of data terminals, i.e. the number of bits for transmitting access data in parallel according to the second interface protocol is larger than the first interface protocol, so that a higher bandwidth can be achieved with the second interface protocol. In case the second interface protocol is the LPDDR protocol or a similar protocol, the second set of data terminals is for transmitting only access data according to the second interface protocol. That is, according to the second interface protocol, the access data and the instruction value/address value are each independently transmitted from different terminals, so that a faster access speed can be achieved with the second interface protocol. In the example of FIG. 1, terminals DQ [63:0] may be used as a second set of data terminals, i.e., a data width of 64 bits may be implemented, which may increase the bandwidth by a factor of 8 compared to the first interface protocol of x8, and in some cases terminals DQ [63:0] may also be downward compatible with the second interface protocol of x32 or x16, which may also increase the bandwidth by a factor of 4 or 2, respectively.

The control part terminals for the first interface protocol and the control part terminals for the second interface protocol may also be collectively referred to as a set of control terminals for the first and second interface protocols for transmitting at least part of the control signals required for the first interface protocol and the second interface protocol, since in some cases part of the control signals may also be transmitted time-division by the data terminals, for example the aforementioned command values, address values and mode register values according to the first interface protocol, etc. The set of control terminals may be divided into a first subset of control terminals for transmitting at least part of the control signals required for the first interface protocol and a second subset of control terminals for transmitting at least part of the control signals required for the second interface protocol. In the case of the two interface protocols illustrated in fig. 1, each having a respective independent terminal, the first subset of control terminals is used only for the first interface protocol, while the second subset of control terminals is used only for the second interface protocol. In the case of two interface protocol multiplexing part terminals illustrated in fig. 2 described later, the set of control terminals includes at least one control terminal multiplexed to the first and second interface protocols. That is, at least part of the first subset of control terminals may also be used for transmitting at least part of the control signals required for the second interface protocol, or at least part of the second subset of control terminals may also be used for transmitting at least part of the control signals required for the first interface protocol, or the first subset of control terminals and the second subset of control terminals may be fully coincident in case the set of control terminals are all multiplexed for the first and second interface protocols. In some cases, at least part of the first set of data terminals may be multiplexed with at least part of the control signals and/or access data required for transmission of the second interface protocol, or at least part of the second set of data terminals may be multiplexed with at least part of the control signals and/or access data required for transmission of the first interface protocol, in addition to or instead of the control terminals.

In the example illustrated in fig. 1, the first subset of control terminals is used to transmit control signals required by the first interface protocol, other than command values, address values and mode register values, such as shown in fig. 1, which may include control terminals, i.e., terminals cs1#, CLK1, DQS/DM, RESET1#, for transmitting chip select signals, clock signals, data strobe signals/data mask signals, RESET signals, respectively.

The second subset of control terminals is used to transmit all control signals required by the second interface protocol, such as shown in FIG. 1, which may include control terminals, terminals DQS [7:0], CA [5:0], CLK2, CS2#, RESET2#, respectively, for transmitting data strobe signals, command/address values or mode register values, clock signals, chip select signals, RESET signals. It will be appreciated that CA [5:0] is an instruction/address multiplexing terminal for time-sharing transmission of instruction values, address values and mode register values according to the second interface protocol. In addition, although not shown in FIG. 1, in some examples, the second subset of control terminals may also include control terminals for inputting data mask signals, i.e., terminals DM [7:0].

As shown in FIG. 1, the control terminals are unidirectional terminals that can only input signals, except that terminals DQS/DM and DQS [7:0] are bidirectional terminals that can both input signals and output signals.

Those skilled in the art will appreciate that the types and numbers of control terminals shown in fig. 1 are merely exemplary, and that the types and numbers of control terminals may be set according to the interface protocol used in actual use. The first set of data terminals and the first subset of control terminals may support various instruction operations of xSPI, and the second set of data terminals and the second subset of control terminals may support various instruction operations of LPDDR, and specific instruction formats, operation timings, etc. will be understood by those skilled in the art and will not be described herein.

The interface protocol selection signal Mode Sel may be used to select whether the IO interface operates in the first interface protocol Mode or the second interface protocol Mode. The signal Mode Sel may be acted upon by a one bit value in the Mode register, for example, indicating that the IO interface is currently operating in the first interface protocol Mode when it is 0 and indicating that the IO interface is currently operating in the second interface protocol Mode when it is 1. The signal mode_sel can be used to control the corresponding components in the IO interface to operate according to the corresponding interface protocol, thereby implementing the corresponding interface protocol Mode.

Thus, as shown in fig. 1, the IO interface may further include a mode register cache portion and a control logic portion.

The Mode register buffer is configured to buffer a Mode register value MR input via a first set of data terminals (e.g., terminals a/DQ [7:0 ]) or via a first portion of the terminals (e.g., terminals CA [5:0 ]) of the set of control terminals, wherein at least one bit is used as an interface protocol selection signal mode_sel for indicating whether to select the first interface protocol or the second interface protocol. Mode_reg in fig. 1 may be the remainder of the MR except mode_sel. The mode register cache may include, for example, a plurality of latches or registers, etc.

In some examples, the interface protocol selection signal mode_sel may be fixed to a specific value before shipping the PSRAM according to the user's needs, which cannot be changed later when used by the user. For example, the interface protocol selection signal mode_sel may be written and fixed in the chip during a chip test phase by performing a specific MR write operation using the first set of data terminals or the first portion of terminals described above. Thus, only the pads (bond) of those terminals used by a corresponding one of the interface protocols may also be bonded (bond) to the package leads when packaging the PSRAM.

In other examples, the value of the interface protocol selection signal mode_sel may be configured by a host using the PSRAM. For example, the host may use only one of the interface protocols, thereby being coupled only with the terminals of the corresponding interface protocol, and write the value of the corresponding interface protocol selection signal mode_sel with the MR write instruction. Or, for example, the host may switch between these two interface protocols depending on the use scenario, thus being coupled to all terminals of the PSRAM, and switch the value of the interface protocol selection signal mode_sel with a corresponding MR write instruction.

The control logic section includes a first control logic module and a second control logic module that perform instruction decoding according to a first interface protocol and a second interface protocol, respectively, and is configured to perform instruction decoding processing on instruction values input via the first group of data terminals or via the first partial terminal with a corresponding one of the first control logic module and the second control logic module according to the interface protocol selection signal mode_sel.

For example, when the signal mode_sel indicates that the first interface protocol is selected, an instruction value is input via the first set of data terminals, and the instruction value is decoded by the first control logic module according to the first interface protocol, so as to obtain a set of internal operation signals to control an access processing unit (for example, including an RA & CA control logic module, an IO control module, a row decoder, a column access control module, and the like as shown in fig. 1) in the PSRAM to perform a corresponding access operation on the memory array. Where RA and CA are short for "Row Address" and "Column Address", respectively. Those skilled in the art will appreciate that the RA & CA control logic module, the IO control module, the row decoder, and the column access control module shown in fig. 1 are merely exemplary, and the access processing section according to the present disclosure is not limited thereto. The access processing section may be configured to perform a corresponding access operation to the memory array according to a result of the instruction decoding processing performed by the control logic section in the IO interface.

For example, when the signal mode_sel indicates that the second interface protocol is selected, an instruction value is input through the first part of terminals, and the instruction value is decoded by the second control logic module according to the second interface protocol, so as to obtain a set of internal operation signals to control the access processing part in the PSRAM to perform corresponding access operation on the memory array.

In some examples, the MR may be entered via the first set of data terminals in a mode register write instruction format of the first interface protocol if the first interface protocol is currently selected, and the MR may be entered via the first portion of terminals in a mode register write instruction format of the second interface protocol if the second interface protocol is currently selected.

In some cases, it is necessary that the control logic unit decodes the command to know that MR is input in the current command format and update MR, so that when switching the interface protocol, mode_sel can be rewritten by using the Mode register write command format of the interface protocol before switching, thereby switching to the currently required interface protocol, and then various operations can be performed by using the interface protocol after switching. In other cases, the IO interface may be designed to rewrite the value of mode_sel by using the currently required interface protocol (i.e., the interface protocol after switching) when switching the interface protocol, and then perform various operations by using the interface protocol after switching.

In the example shown in fig. 1, the above-mentioned mode register value MR and instruction value are both input via a first set of data terminals, e.g. terminals a/DQ [7:0], in case the IO interface is operating in the first interface protocol mode, whereas the above-mentioned mode register value MR and instruction value are both input via instruction/address multiplexing terminals, e.g. terminals CA [5:0], in case the IO interface is operating in the second interface protocol mode.

In the case where such instruction values and address values/mode register values are time-multiplexed by the same set of terminals, a combination of sets of values obtained by sampling the inputs of the set of terminals at a specified plurality of clock edges (which may also be referred to as a set of clock edges) may be referred to as an instruction/address value. It will be appreciated that this statement is a common expression in the art, and for the sake of brevity of description "mode register value" is omitted, whereas "address value" in "instruction/address value" actually includes the mode register value. The values sampled at clock edges specified in the respective instruction formats supported by the protocol may be instruction values, address values, or mode register values. Depending on the instruction, it is possible to input an address value or a mode register value on the same clock edge. For example, in an access instruction, a certain address value is input at the nth clock edge after the start of transmission, and in a mode register write instruction, a mode register value is input at the same clock edge.

The specified plurality of clock edges may be determined according to the interface protocol (e.g., the various instruction formats it employs, SDR or DDR transmission timing, etc.), and may be, for example, a consecutive number of valid clock edges after the chip select signal is valid (i.e., after transmission is initiated). The "effective clock edge" refers to a clock edge at which sampling is performed, which is specified in terms of transmission timing or the like. In the case of DDR transfer timing, sampling is performed twice in one clock cycle, and the effective clock edge includes a rising edge and a falling edge of the clock signal.

The instruction/address value is fed to the control logic for processing, from which the control logic can extract the instruction value and address value (or mode register value) at different times for processing, respectively.

In an example such as shown in FIG. 1 where two sets of separate terminals are employed to support two interface protocols, there is a first command/address value Cmd/Addr1 that is a plurality of sets of values sampled at a first set of clock edges to inputs (e.g., A/DQ [7:0] _v) of a first set of data terminals (e.g., terminals A/DQ [7:0 ]), and a second command/address value Cmd/Addr2 that is a plurality of sets of values sampled at a second set of clock edges to inputs (e.g., CA [5:0] _v) of a first portion of terminals (e.g., terminals CA [5:0 ]). The first set of clock edges and the second set of clock edges are determined according to the first interface protocol and the second interface protocol, respectively, and the number and the corresponding transmission order may be the same or different. In addition, the first clock signal clk1_v and the second clock signal clk2_v are input from the first clock terminal and the second clock terminal, respectively, for transmitting clock signals required for the first interface protocol and the second interface protocol, respectively. The first set of clock edges are all clock edges of the first clock signal clk1_v and the second set of clock edges are all clock edges of the second clock signal clk2_v.

In an alternative embodiment, as shown in the example of FIG. 1, the IO interface may further include an instruction/address buffer configured to buffer a first instruction/address value Cmd/Addr1 input via a first set of data terminals (e.g., terminals A/DQ [7:0 ]) and a second instruction/address value Cmd/Addr2 input via a first portion of terminals (e.g., terminals CA [5:0 ]), and output the first instruction/address value Cmd/Addr1 and the second instruction/address value Cmd/Addr2 to the control logic. For example, in fig. 1, the instruction/address buffer may receive a value a/DQ [7:0] v input via a terminal a/DQ [7:0] and a first control clock clk1_ctrl, and sample and buffer the value a/DQ [7:0] v input via the terminal a/DQ [7:0] at an active clock edge of the first control clock clk1_ctrl, resulting in a first instruction/address value Cmd/Addr1, where the first control clock clk1_ctrl may be generated by the first IO buffer module according to the input clock clk1_v and the first interface protocol. Similarly, the instruction/address buffer may also receive the value CA [5:0] _v input via the terminal CA [5:0] and the second control clock clk2_ctrl, and sample and buffer the value CA [5:0] _v input via the terminal CA [5:0] at the active clock edge of the second control clock clk2_ctrl to obtain the second instruction/address value Cmd/Addr2, where the second control clock clk2_ctrl may be generated by the second IO buffer module according to the input clock clk2_v and the second interface protocol. The command/address buffer may have two different buffer areas for storing the first command/address value Cmd/Addr1 and the second command/address value Cmd/Addr2, respectively.

In some examples, the first control logic module may be configured to receive the first instruction/address value Cmd/Addr1 and the first clock signal clk1_v, and according to the first interface protocol and the first clock signal clk1_v, to instruction decode the instruction value extracted from the first instruction/address value Cmd/Addr1 to obtain a first internal operation signal, and to extract the address value from the first instruction/address value as the first address signal.

In some examples (e.g., examples compatible with certain LPDDR protocols), the second control logic module also considers the mode register value when performing instruction decoding. For example, the second control logic module determines an internal operation signal corresponding to the read instruction or the write instruction based on the read delay (RD LATENCY) or the write delay (WR LATENCY) set by the mode register. Thus, the second control logic module may be configured to receive the second command/address value Cmd/Addr2, the second clock signal clk2_v, and the mode register value of the specified portion, and according to the second interface protocol and the second clock signal clk2_v, to command-decode the command value extracted from the second command/address value Cmd/Addr2 in combination with the mode register value of the specified portion to obtain a second internal operation signal, and to extract the address value from the second command/address value Cmd/Addr2 as the second address signal. The mode register value of the designated portion may be determined in accordance with the second interface protocol, and may be, for example, a designated one-bit or multi-bit mode register value.

In the case that the input instruction is a mode register write instruction, that is, the first internal operation signal or the second internal operation signal indicates that a mode register write operation is performed, the extracted address value is actually a mode register value and optionally other relevant values, so that at least part of the corresponding first or second address signal may be cached in the mode register cache portion as the latest mode register value, that is, the mode register value is updated.

Fig. 3 shows a composition diagram of one specific example of the control logic section in fig. 1.

As shown in fig. 3, the first control logic module includes a first instruction decoder, a first clock gating unit, a first internal operation signal buffer unit, and a first address buffer unit.

The first instruction decoder is configured to decode the first instruction/address value Cmd/Addr1 according to a first interface protocol to obtain a first decoded signal Dec1.

The first clock gating unit is configured to convert the first clock signal clk1_v into a first command clock signal cmd_clk1 and a first address clock signal addr_clk1, which respectively indicate sampling instants of command values and address values in the first command/address values Cmd/Addr1, according to a first interface protocol.

The first Internal operation signal buffering unit is configured to sample and buffer the first decoding signal Dec1 as a first Internal operation signal international_oper1 at a timing indicated by the first command clock signal cmd_clk1.

The first address buffer unit is configured to sample and buffer the first instruction/address value Cmd/Addr1 as the first address signal Addr 1at a time indicated by the first address clock signal addr_clk 1.

Similarly, the second control logic module includes a second instruction decoder, a second clock gating unit, a second internal operation signal buffering unit, and a second address buffering unit.

The second instruction decoder is configured to decode the second instruction/address value Cmd/Addr2 according to the second interface protocol in combination with the Mode register value mode_reg_p of the designated portion to obtain a second decoded signal Dec2.

The second clock gating unit is configured to convert the second clock signal CLK2 v into a second command clock signal cmd_clk2 and a second address clock signal addr_clk2 according to a second interface protocol, which indicate the sampling instants of the command value and the address value in the second command/address value cmd_clk2, respectively.

The second Internal operation signal buffering unit is configured to sample and buffer the second decoding signal Dec2 as a second Internal operation signal international_oper2 at a timing indicated by the second instruction clock signal cmd_clk2.

The second address buffer unit is configured to sample and buffer the second instruction/address value Cmd/Addr2 as the second address signal Addr2 at a time indicated by the second address clock signal addr_clk 2.

The first or second instruction decoder, the first or second clock gating unit may be implemented by digital logic circuits. For example, the circuitry of the first or second instruction decoder may be designed based on the correspondence between the code value of each instruction used by the first or second interface protocol and the internal operation signal required by each instruction. The first or second internal operation signal may be one or more signals to be sent to one or more subsequent internal processing modules, for controlling the internal processing modules to perform corresponding operations, so as to implement the indication of the corresponding instruction to the PSRAM. For example, in the example of fig. 1, the final internal operation signal (which is equal to the first or second internal operation signal) output by the control logic is input to the subsequent RA & CA control logic module and IO control module. Since the IO control module is only used to control the input and output of access data under the first interface protocol on its data terminals, as will be detailed later, the second internal operation signal does not enable the IO control module.

For example, the circuitry of the first or second clock gating cell may be designed according to the clock edge settings that convey the instruction value and address value/mode register value in each instruction format used by the first or second interface protocol. For example, in the case where the first interface protocol employing DDR timing uses the instruction formats each of which is the first and second valid clock edges (i.e., the rising edge and the falling edge of the first clock cycle) to transfer the instruction value, and the third to sixth valid clock edges (i.e., the rising edge and the falling edge of the second and third clock cycles) to transfer the address value or a part of the valid clock edges thereof to transfer the mode register value, the first gating section may be provided in the first clock gating unit so that clk1_v is transferred to its output only in the first clock cycle, becoming the first instruction clock signal cmd_clk1, and the second gating section may be provided so that clk1_v is transferred to its output only in the second and third clock cycles, becoming the first address clock signal addr_clk1.

The first or second internal operation signal buffering unit and the first or second address buffering unit may comprise, for example, a set of latches or registers, respectively, which may sample and buffer the signals input thereto, i.e. the first or second decoded signal and the first or second instruction/address value, respectively, at the active clock edges of the first or second instruction clock signal and the first or second address clock signal, respectively. For example, these buffer cells may be triggered to sample buffer operations at both the rising and falling edges of the input clock signal, i.e., the active clock edge of the clock signal may include both the rising and falling edges.

In addition, in an alternative embodiment, the control logic may further include an output module for combining the output of the first control logic module and the output of the second control logic module.

In one example, the output module may be configured to receive a first Internal operation signal international_oper1, a second Internal operation signal international_oper2, a first address signal Addr1, and a second address signal Addr2, and output a final Internal operation signal international_oper and a final address signal Addr.

Wherein the final Internal operation signal internal_oper is equal to one of the first Internal operation signal internal_oper1 and the second Internal operation signal internal_oper2 corresponding to the interface protocol selection signal mode_sel, and the final address signal Addr is equal to one of the first address signal Addr1 and the second address signal Addr2 corresponding to the interface protocol selection signal mode_sel. Here, the "final" signal refers to a signal output to the outside by the output module.

For example, the output module may include an OR gate OR1 and a multiplexer MUX1 shown in fig. 3. The two input ends of the OR gate OR1 respectively receive the first Internal operation signal internal_Oper1 and the second Internal operation signal internal_Oper2, and the output end of the OR gate OR1 outputs a final Internal operation signal internal_Oper2. The multiplexer MUX1 has two inputs receiving the first address signal Addr1 and the second address signal Addr2, respectively, a control terminal receiving the interface protocol selection signal mode_sel, and an output terminal outputting the final address signal Addr. For example, when mode_sel is 0, the selection of the first interface protocol is instructed, the multiplexer MUX1 outputs the first address signal Addr1 as the final address signal Addr, and when mode_sel is 1, the selection of the second interface protocol is instructed, the multiplexer MUX1 outputs the second address signal Addr2 as the final address signal Addr. It will be appreciated that in the case where the two inputs to the OR gate OR1 OR the multiplexer MUX1 each contain a plurality of bits (bits), the OR gate OR1 OR the multiplexer MUX1 also includes a plurality of OR gate units OR multiplexer units that perform an OR operation OR a multiplexing operation on the corresponding bits of the two inputs.

In this case, the internal operation signals output by the control logic modules that do not work are all low level, so the final internal operation signal obtained through the OR gate OR1 is the internal operation signal output by the control logic modules that do work. However, the address signals outputted from the inactive control logic module are not necessarily all low level, and therefore, a multiplexer is required to select one of the input signals corresponding to the interface protocol selection signal mode_sel to output. However, in other cases, the reset processing may be performed on both control logic modules before the start, and the address signals output by the control logic modules that do not work at this time are both low level, so that another or gate may be used for the two address signals instead of the multiplexer MUX1 to obtain the finally output address signal.

In addition, in an alternative embodiment, the power to the currently inactive control logic module may also be turned off to save power consumption.

In the example as in fig. 3, the control logic may further include a first switch M1, a second switch M2, and a power control module. It will be appreciated that although a PMOS (P-CHANNEL METAL-Oxide-Semiconductor) transistor is shown in fig. 3 as the switch, the present disclosure is not limited thereto and other devices may be employed to implement the first and second switches as desired.

The first switch M1 is located between the first control logic block and the power supply voltage VDD used by the first control logic block. The second switch M2 is located between the second control logic module and the power supply voltage VDD used by the second control logic module. For example, the first or second switch may be provided between a power line used by each circuit device inside the first or second control logic module and a power line externally transmitting VDD. It is thus possible to determine whether each control logic module is connected to the power supply by the on/off of the switch.

The power control module is configured to output an interface protocol selection signal mode_sel and an inverse signal thereof to control terminals of the first switch M1 and the second switch M2, respectively, such that the first switch M1 is turned on and the second switch M2 is turned off when the interface protocol selection signal mode_sel indicates that the first interface protocol is currently selected, and the second switch M2 is turned on and the first switch M1 is turned off when the interface protocol selection signal mode_sel indicates that the second interface protocol is currently selected.

For example, in the example of fig. 3, the power control module may include a buffer (buffer) and an inverter. The buffer and the inverter are input with the interface protocol selection signal mode_sel to obtain power_en1 and power_en2, respectively, which correspond to the interface protocol selection signal mode_sel and its inverse. Power_en1 is output to the gate of PMOS transistor M1, while the source and drain of M1 are coupled to VDD and the first control logic block (e.g., its internal POWER supply lines), respectively. Power_en2 is output to the gate of PMOS transistor M2, while the source and drain of M2 are coupled to VDD and a second control logic block (e.g., its internal POWER supply lines), respectively. When the mode_sel is 0, the selection of the first interface protocol is indicated, and at the moment, M1 is conducted and M2 is disconnected, so that the power of the first control logic module is turned on and the power of the second control logic module is turned off, and when the mode_sel is 1, the selection of the second interface protocol is indicated, and at the moment, M2 is conducted and M1 is disconnected, so that the power of the second control logic module is turned on and the power of the first control logic module is turned off.

Returning to fig. 1. In an alternative embodiment, as shown in fig. 1, the IO interface may further include an IO buffer. In fig. 1, for convenience of illustration, the IO buffer part is split into a first IO buffer module and a second IO buffer module, which are used for all terminals used by the first interface protocol and all terminals used by the second interface protocol, respectively.

The IO buffer may be coupled to the first set of data terminals, the second set of data terminals, and the set of control terminals described above, and include a plurality of receivers for receiving signals input on the first set of data terminals, the second set of data terminals, and the set of control terminals, respectively, and a plurality of drivers for driving signals output on portions of the first set of data terminals, the second set of data terminals, and the set of control terminals, respectively. Thus, signal transmission between the IO interface and the host outside the PSRAM can be better realized. In some cases, the transmission may be performed using a differential signal technique, for example, the first clock signal clk1_v is input using a pair of differential signals such as clk1_t and clk1_c as shown in fig. 6 later. At this time, the receiver and/or the driver in the IO buffer part may correspondingly include a differential signal receiver and/or transmitter.

In the example of FIG. 1, the IO buffers provide a receiver and driver for each of terminals A/DQ [7:0], terminals DQ [63:0], and terminals DQS/DM and DQS [7:0] as bi-directional terminals. For the other remaining terminals as unidirectional terminals, the IO buffer provides only a receiver for each of the terminals.

In addition, in order to save power consumption, the receiver and/or the driver of the terminal not used for transmitting the signal required for the currently selected interface protocol (i.e., corresponding to the interface protocol selection signal mode_sel) may also be turned off. These terminals may also be referred to as idle terminals. The IO buffer part may be configured to turn off the receiver and/or the driver for the idle terminal according to the interface protocol selection signal mode_sel.

For example, the second IO buffer module may be powered down, such as similarly to the control logic of FIG. 3 described above, when the first interface protocol is currently selected, such as Mode_Sel being 0, and the first IO buffer module may be powered down, such as similarly powered down, when the second interface protocol is currently selected, such as Mode_Sel being 1.

FIG. 5 illustrates an exemplary composition schematic of an IO buffer portion in accordance with some embodiments of the present disclosure with bi-directional terminals A/DQ [7:0] and uni-directional terminals CS1 #.

As shown in FIG. 5, for bi-directional terminals A/DQ [7:0], the IO buffer provides a receiver and driver and a set of ODT (On-Die Termination) resistors Rttp, rttn, and Rttw for each of the terminals. For unidirectional terminal cs1#, the IO buffer provides it with a receiver and a set of ODT resistances Rttp, rttn, and Rttw. The resistances Rttp, rttn, and Rttw have respectively different resistance values. It is to be understood that the number of ODT resistances per set is not limited to 3, but may be determined as desired.

In addition, the IO buffer section further includes an ODT control unit and an OCD (Off-CHIP DRIVER ) control unit. The ODT control unit is for controlling which resistor of a set of ODT resistors for each terminal is enabled so as to match the transmission line impedance, etc. The OCD control unit is used to control the output impedance of each driver so as to match the transmission line impedance and the like.

The portions of the IO buffer portion for the remaining terminals are shown in the ellipses in fig. 5, and it will be understood that the specific structure thereof may be the same as the structure for the bidirectional terminal or the unidirectional terminal described above, and will not be described herein.

Returning to fig. 1. As shown in FIG. 1, in an alternative embodiment, the IO interface may also include an internal access data bus DBUS [63:0] and access data IO portion.

Internal access data bus DBUS [63:0] is used to transfer access data between the memory array and terminals A/DQ [7:0] and between the memory array and terminals DQ [63:0] within the PSRAM, the number of bits being equal to the number of terminals DQ [63:0 ]. Thus, the first interface protocol and the second interface protocol can share the same data bus to exchange access data with the memory array, and the data bit width of the second interface protocol is the same as the bit width of the internal access data bus, so that the conversion of the bit width is avoided.

In the first interface protocol, since the data bit width does not match the bit width of the internal access data bus, the access data IO section is required to perform conversion of the bit width.

The access data IO section is configured to stitch a plurality of write data sampled at the input of the fifth set of clock edges to the first set of data terminals, for example, terminals a/DQ [7:0], into one internal write data for output to the internal access data bus DBUS [63:0] at the same timing, and split one internal read data received via the internal access data bus DBUS [63:0] at the same timing into a plurality of read data for output via the first set of data terminals, for example, terminals a/DQ [7:0] in a plurality of divisions.

For example, 8 write data consecutively input on a first set of data terminals, e.g., terminals A/DQ [7:0], may be sequentially spliced into one 64-bit internal write data at the time of a write operation, and the 64-bit internal read data read out simultaneously at the time of a read operation may be split into 8 read data to be sequentially output 8 times on the first set of data terminals, e.g., terminals A/DQ [7:0 ]. The fifth set of clock edges described above may be 8 consecutive valid clock edges determined according to the write instruction format of the first interface protocol.

In some examples, a first set of data terminals, such as terminals A/DQ [7:0], transmit access data using DDR timing, and the access data IO section may include a write driver, a data interface, a read data cache module, a read data multiplexer, and a read driver. Wherein the write driver (e.g., the write driver shown in subsequent FIG. 6 and the write driver in the input logic module) is configured to stitch two write data sampled from inputs of a first set of data terminals, e.g., terminals A/DQ [7:0], at consecutive two of the fifth set of clock edges into one intermediate write data for output at the same time. A data interface (e.g., the data interface shown in subsequent fig. 6) is configured to splice a plurality of the intermediate write data that are continuously output into the one internal write data. The read data buffer module (e.g., the read data FIFO (First-In First-Out buffer) shown In fig. 6, which follows) and the read data FIFO In the MUX module are configured to buffer the one internal read data. The read data multiplexer (e.g., the subsequent read data FIFO and MUX module of the MUX modules shown in fig. 6) is configured to split the buffered internal read data into a number of intermediate read data that is twice the number of terminals of the first set of data terminals, e.g., terminals a/DQ [7:0], for sequential output. A read driver (e.g., the read driver shown in subsequent fig. 6) is configured to split one of the intermediate read data into two of the read data for output via a first set of data terminals, such as terminals a/DQ [7:0], respectively, at two successive clock edges.

FIG. 6 illustrates an exemplary composition diagram of an access data IO portion in accordance with some embodiments of the present disclosure using DDR transmission timing with terminals A/DQ [7:0 ].

As shown in fig. 6, the access data IO section includes a write driver and input logic module, a data interface, a read data FIFO and MUX module, and a read driver. In addition, in some examples, the access data IO section may further include a DLL (Delay-Locked Loop) for ensuring synchronization of the output clock clk1_v with an externally received clock. Although the DLL is shown to receive a pair of differential signals clk1_t and clk1_c, it will be appreciated that, as previously described, the pair of differential signals may be converted to a single-ended clock signal via the differential signal receiver in the first IO buffer module and then input to the DLL.

During a write operation, the write driver and the input logic portion of the input logic may determine the fifth set of clock edges according to the input clock clk1_v and the first interface protocol, thereby controlling the write driver portion to sequentially splice two 8-bit write data obtained by sampling the input of the terminal a/DQ [7:0] with each two consecutive clock edges into one 16-bit intermediate write data for outputting at the same time. In addition, the write driver and the input logic module can also receive the DM signal input on the terminal DQS/DM to perform corresponding write data shielding processing.

After receiving the consecutive 4 intermediate write data from the write driver and the input logic module, the data interface concatenates the 4 intermediate write data into one 64-bit internal write data and outputs to the internal access data bus DBUS [63:0].

During the reading operation, the read data FIFO and the read data FIFO (first-in first-out buffer) in the MUX module can sequentially receive and buffer a plurality of 64-bit internal read data from the internal access data bus DBUS [63:0], and sequentially output the internal read data to the MUX module for splitting according to the input sequence. The MUX module splits one 64-bit internal read data into 4 16-bit intermediate read data for sequential output.

The read driver splits each intermediate read data received from the MUX module into two 8-bit read data for output via terminals A/DQ [7:0] at two consecutive clock edges, respectively. In addition, the read driver may also simultaneously output the DQS signal for synchronizing read data to the terminal DQS/DM.

An embodiment in which part of the terminals are multiplexed to two interface protocols will be described below in connection with fig. 2. As shown in the rightmost terminal of fig. 2, the second interface protocol multiplexes at least a portion of the terminals of the first interface protocol.

It will be appreciated that the present disclosure is not limited to this manner of multiplexing terminals, but may also multiplex at least a portion of the terminals of the second interface protocol, for example, by the first interface protocol. As previously described, the set of control terminals may comprise at least one control terminal multiplexed with the first and second interface protocols, and/or at least part of the first set of data terminals may also be used for transmitting at least part of the control signals and/or access data required by the second interface protocol, or at least part of the second set of data terminals may also be used for transmitting at least part of the control signals and/or access data required by the first interface protocol, for example.

By multiplexing the terminals, the number of terminals required can be reduced, thereby reducing the chip size and saving the packaging cost.

The following will mainly describe the portions of fig. 2 that are different from fig. 1, and the remaining identical portions may be referred to the related description above in connection with fig. 1, and will not be repeated here.

As shown in FIG. 2, in comparison with FIG. 1, terminals CS2#, RESET2#, CLK2, CA [5:0], DQS [0] originally used for the second interface protocol are omitted, and the functions are realized by terminals CS1#, RESET1#, CLK1, A/DQ [7:0], DQS/DM, respectively, originally used for the first interface protocol. For ease of illustration, these terminals, which are also used for both interface protocols, are more named CS#, RESET#, CLK, A/DQ [7:0]/CA [5:0], DQS/DM/DQS [0] in FIG. 2. It will be appreciated that CA [5:0] multiplexes only 6 terminals in A/DQ [7:0], such as the terminal corresponding to the lowest 6 bits.

It can be said that in the IO interface in FIG. 2, at least some of the first set of data terminals are also used to time-share transfer instruction values, address values, and mode register values according to the second interface protocol, such as terminals A/DQ [7:0]/CA [5:0] in FIG. 2. Thus, in the case of the IO interface of FIG. 2 operating in the first interface protocol mode and the second interface protocol mode, both the mode register value and the instruction value are input via a first set of data terminals, such as terminals A/DQ [7:0]/CA [5:0].

The set of control terminals described above comprises a first subset of control terminals for transmitting control signals required for the first interface protocol in addition to the command value, the address value and the mode register value, and at least part of the control signals required for the second interface protocol in addition to the command value, the address value and the mode register value, for example comprising terminals cs#, reset#, CLK, DQS/DM/DQS [0] in fig. 2. In the example of fig. 2, the set of control terminals may also include a second subset of control terminals for transmitting the remaining control signals required by the second interface protocol, including for example terminal DQS [7:1] in fig. 2.

In other examples, to better achieve signal matching, instead of multiplexing terminals DQS/DM to transmit DQS [0], terminals may be provided independently of DQS [7:1] to transmit DQS [0], so the second subset of control terminals described above may include terminals DQS [7:0].

In addition, in FIG. 2, the command/address buffer only needs to buffer the command/address values Cmd/Addr input via a first set of data terminals, such as terminals A/DQ [7:0]/CA [5:0], and output the command/address values Cmd/Addr to the control logic. It will be appreciated that the different instruction formats of the two interface protocols may result in different input times of the instruction/address values Cmd/Addr under the different interface protocols. For example, when operating in a first interface protocol, the corresponding command/address values Cmd/Addr may be sets of values sampled at a third set of clock edges for inputs (e.g., A/DQ [7:0]/CA [5:0] _ v) to a first set of data terminals, e.g., terminals A/DQ [7:0]/CA [5:0] _ v), and when operating in a second interface protocol, the corresponding command/address values Cmd/Addr may be sets of values sampled at a fourth set of clock edges for inputs (e.g., A/DQ [7:0]/CA [5:0] _ v) to the first set of data terminals, e.g., terminals A/DQ [7:0]/CA [5:0] _. The third set of clock edges and the fourth set of clock edges, which may be the same or different, may be determined by a control clock clk_ctrl, which may be generated by the first IO buffer module according to the currently input clock clk_v and the currently selected interface protocol.

In addition, the clock signals operating in both protocols are also input from the clock terminal CLK which is multiplexed to transmit the clock signals required for the first interface protocol and the second interface protocol.

Thus, the command/address values Cmd/Addr and the clock signal clk_v input to the control logic are both signals multiplexed to the two interface protocols, which need to be demultiplexed into first and second command/address values, and first and second clock signals in the control logic for use by the first and second control logic modules, respectively, as shown in fig. 4.

Fig. 4 shows a schematic diagram of the composition of a specific example of the control logic, which differs from fig. 3 in that a first demultiplexer DEMUX1 and a second demultiplexer DEMUX2 are added.

As shown in fig. 4, the input end of the first demultiplexer DEMUX1 receives the command/address value Cmd/Addr, the control end thereof receives the interface protocol selection signal mode_sel, and the two output ends thereof respectively output the first command/address value Cmd/Addr1 and the second command/address value Cmd/Addr2. As described above, the command/address value Cmd/Addr is a plurality of sets of values sampled at the third or fourth set of clock edges from the inputs (e.g., A/DQ [7:0]/CA [5:0] _v) to the first set of data terminals, e.g., terminals A/DQ [7:0]/CA [5:0 ].

The second demultiplexer DEMUX2 has an input terminal receiving the clock signal clk_v input from the clock terminal, a control terminal receiving the interface protocol selection signal mode_sel, and two output terminals outputting the first clock signal clk1_v and the second clock signal clk2_v, respectively.

For example, when mode_sel is 0, the selection of the first interface protocol is instructed, the first demultiplexer DEMUX1 outputs the input command/address value Cmd/Addr to the first output terminal as the first command/address value Cmd/Addr1, the second demultiplexer DEMUX2 outputs the input clock signal clk_v to the first output terminal as the first clock signal clk1_v, and when mode_sel is 1, the selection of the second interface protocol is instructed, the first demultiplexer DEMUX1 outputs the input command/address value Cmd/Addr to the second output terminal as the second command/address value Cmd/Addr2, and the second demultiplexer DEMUX2 outputs the input clock signal clk_v to the second output terminal as the second clock signal clk2_v.

The rest of the control logic of fig. 4 is the same as the corresponding part of fig. 3, and reference is made to the related description of fig. 3, and the detailed description is omitted here.

An access method of the PSRAM according to an embodiment of the present disclosure will be described below with reference to fig. 7 and 8.

As shown in fig. 7, the PSRAM includes the IO interface, the access processing section, and the memory array according to the foregoing embodiments. The access processing unit is configured to perform a corresponding access operation on the memory array according to a result of the instruction decoding processing performed by the control logic unit in the IO interface, as described above. The specific structure of the IO interface may be referred to the foregoing drawings and descriptions thereof, and will not be described herein.

In addition, the host is coupled to the IO interface to interact with the PSRAM to implement access operations. The host may be coupled to multiple terminals in the IO interface as needed. For example, in case the host desires to access the PSRAM with the first interface protocol, the host may be coupled to all terminals in the IO interface for the first interface protocol, i.e. the first set of data terminals and the control terminals for transmitting control signals required for the first interface protocol. In case the host desires to access the PSRAM with the second interface protocol, the host may be coupled to all terminals in the IO interface for the second interface protocol, i.e. the second set of data terminals and the control terminals for transmitting control signals required for the second interface protocol. In the event that the host desires to switchably access the PSRAM between the first interface protocol and the second interface protocol, the host may be coupled to all terminals of the IO interface.

The host exchanges data with the PSRAM via the IO interface to enable access to the PSRAM. For example, the host transmits various data necessary for access as described above to the PSRAM via the IO interface and receives read-related data as described above from the PSRAM.

Fig. 8 depicts the access method of the PSRAM from the PSRAM side, i.e., the execution body of the method of fig. 8 is the PSRAM. It will be appreciated that the other party exchanging data via the terminals of the IO interface in the method of fig. 8 is the host. Details of the operation in fig. 8 can be found in the descriptions of the foregoing drawings, and are not repeated here.

As shown in fig. 8, at step S810, a mode register value is received via a first set of data terminals or a first portion of terminals in the IO interface. Then, at step S820, an instruction value is received via the first set of data terminals or the first partial terminal.

Then, at step S830, according to the interface protocol selection signal in the mode register value, instruction decoding processing is performed on the instruction value by using a corresponding one of the first control logic module and the second control logic module in the IO interface.

Then, at step S840, according to the result of the instruction decoding process, a corresponding access operation is performed on the memory array by the access processing section.

For example, in the case where the IO interface adopts the structure shown in fig. 1, and the host desires to access the PSRAM using the LPDDR protocol as the second interface protocol, the host may sequentially input the mode register value and the instruction value via the terminals CA [5:0] in a manner prescribed by the LPDDR protocol, and accordingly, the PSRAM sequentially receives the mode register value and the instruction value via the terminals CA [5:0 ]. Based on the value of the interface protocol selection signal in the received mode register value, the PSRAM determines that the access operation will be performed next using the LPDDR protocol, and therefore performs instruction decode processing on the received instruction value using the corresponding second control logic module. The PSRAM may transmit the result of the instruction decoding process to the access processing section so as to control the access processing section to perform a corresponding access operation to the memory array.

An embodiment of PSRAM according to the present disclosure that supports two hosts simultaneously accessing using different interface protocols will be described below in conjunction with fig. 9.

Fig. 9 shows an exemplary composition schematic of an electronic device according to some embodiments of the present disclosure, wherein the electronic device includes a PSRAM, a first host, and a second host according to previous embodiments.

As shown in fig. 9, the IO interface in the PSRAM includes a first interface protocol terminal for a first interface protocol and a second interface protocol terminal for a second interface protocol. Wherein the first interface protocol terminals comprise the aforementioned first set of data terminals and a first subset of control terminals of a set of control terminals for transmitting control signals required for the first interface protocol. The second interface protocol terminals include the aforementioned second set of data terminals and a second subset of control terminals of the set of control terminals for transmitting control signals required by the second interface protocol. In addition, the first interface protocol terminal may further comprise a multiplexed second set of data terminals in the presence of multiplexed data terminals and/or the second interface protocol terminal may further comprise a multiplexed first set of data terminals, and the first and second subsets may overlap in the presence of multiplexed control terminals, i.e. the control terminals multiplexed in both protocols belong to both the first and second subsets.

The first host is coupled to the first interface protocol terminal and is configured to input the Mode register value MR to the IO interface via the first set of data terminals or the first portion of terminals when accessing the PSRAM, such that the interface protocol selection signal mode_sel indicates that the first interface protocol Mode is currently selected. The first host may interact with the PSRAM using a first interface protocol to implement the access operation.

The second host is coupled to the second interface protocol terminal and is configured to input the Mode register value MR to the IO interface via the first set of data terminals or the first portion of terminals when accessing the PSRAM, such that the interface protocol selection signal mode_sel indicates that the second interface protocol Mode is currently selected. The second host may interact with the PSRAM using a second interface protocol to implement the access operation.

In addition, the first host further comprises a first occupancy state terminal 91 and the second host further comprises a second occupancy state terminal 92. The first and second occupancy state terminals 91, 92 are coupled together and are used to interact with each other's occupancy state of the PSRAM between the first and second hosts to ensure that the first and second hosts access the PSRAM in a time sharing manner. The occupancy state to the PSRAM may include information indicating whether it is currently in the process of interacting with the PSRAM. In some examples, the first occupancy state terminal 91 and the second occupancy state terminal 92 may also be referred to as BUSY terminals, between which BUSY signals are interacted to indicate respective occupancy states of the PSRAM.

For example, the first host may learn from the second occupancy state terminal 92 the occupancy state of the second host for the PSRAM before initiating interaction with the PSRAM, which may be initiated if it is unoccupied. After initiating interaction with the PSRAM, the first host changes the occupied state of the first host to the occupied state of the PSRAM, and the second host is prevented from interacting with the PSRAM.

Therefore, the PSRAM can support two interface protocols to work simultaneously, and access conflict of two hosts to the PSRAM can be avoided by adopting a time-sharing multiplexing method, so that only one host can be accessed at a time, and the PSRAM is suitable for more and more complex application scenes.

The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An IO interface for a pseudo-static random access memory selectively operating in a first interface protocol mode or a second interface protocol mode, the IO interface comprising:

A first set of data terminals for the first interface protocol;

a set of control terminals for the first and second interface protocols;

2. The IO interface of claim 1, wherein the first set of data terminals is configured to time-share transfer access data, instruction values, address values, and mode register values according to the first interface protocol, and

The second set of data terminals is for transmitting only access data according to the second interface protocol.

3. The IO interface of claim 2, wherein the set of control terminals includes a first subset of control terminals for transmitting control signals other than command values, address values, and mode register values required by the first interface protocol, and a second subset of control terminals for transmitting all control signals required by the second interface protocol, wherein the second subset of control terminals includes, as the first partial terminals, command/address multiplexing terminals for time-sharing transmission of command values, address values, and mode register values according to the second interface protocol;

4. The IO interface of claim 2 wherein at least a portion of the first set of data terminals is further configured to time-share transfer instruction values, address values, and mode register values according to the second interface protocol;

5. The IO interface of claim 1, wherein the first control logic module is configured to receive a first instruction/address value and a first clock signal and to instruction decode an instruction value extracted from the first instruction/address value to obtain a first internal operation signal and to extract an address value from the first instruction/address value as a first address signal according to the first interface protocol and the first clock signal, and/or

The second control logic module is configured to receive a second instruction/address value, a second clock signal, and a specified portion of the mode register values, and to instruction decode an instruction value extracted from the second instruction/address value in combination with the specified portion of the mode register values according to the second interface protocol and the second clock signal to obtain a second internal operation signal, and to extract an address value from the second instruction/address value as a second address signal.

6. The IO interface of claim 5 wherein,

In a first case where the first set of data terminals are used to time-share access data, instruction values, address values and mode register values according to the first interface protocol, and the first portion of terminals are used to time-share instruction values, address values and mode register values according to the second interface protocol, the first instruction/address values are sets of values obtained by sampling the inputs of the first set of data terminals at a first set of clock edges, the second instruction/address values are sets of values obtained by sampling the inputs of the first portion of terminals at a second set of clock edges, or in a second case where the first set of data terminals are used to time-share access data, instruction values, address values and mode register values according to the first interface protocol, and at least some of the first set of data terminals are also used to time-share instruction values, address values and mode register values according to the second interface protocol, the first instruction/address values and the second instruction/address values are sets of values obtained by sampling the inputs of the first set of data terminals at a third set of clock edges and a fourth set of clock edges, respectively;

7. The IO interface of claim 5, wherein the first control logic module comprises:

A first address buffer unit configured to sample and buffer the first instruction/address value as the first address signal at a timing indicated by the first address clock signal, and/or

Wherein the second control logic module comprises:

8. The IO interface of claim 5, wherein, in the case where the first set of data terminals is used to time-share transfer of access data, instruction values, address values, and mode register values according to the first interface protocol, at least some of the first set of data terminals is further used to time-share transfer of instruction values, address values, and mode register values according to the second interface protocol, and clock terminals of the set of control terminals are multiplexed with clock signals required to transfer the first interface protocol and the second interface protocol, the control logic further comprises:

9. The IO interface of claim 5, wherein the control logic further comprises:

10. The IO interface of claim 9, wherein at least a portion of the final address signals are buffered into the mode register buffer as the most current mode register value in the event that the final internal operation signal indicates a mode register write operation.

11. The IO interface of claim 1, wherein the control logic further comprises:

12. The IO interface of claim 1, further comprising:

An IO buffer coupled to the first set of data terminals, the second set of data terminals, and the set of control terminals, and including a plurality of receivers for receiving signals input on the first set of data terminals, the second set of data terminals, and the set of control terminals, respectively, and a plurality of drivers for driving signals output on portions of the first set of data terminals, the second set of data terminals, and the set of control terminals, respectively.

13. The IO interface of claim 12, wherein the IO buffer is configured to shut down a receiver and/or driver for an idle terminal according to the interface protocol selection signal, wherein the idle terminal is a terminal not used for transmitting a signal required for an interface protocol to which the interface protocol selection signal corresponds.

14. The IO interface of claim 1, further comprising:

15. The IO interface of claim 14, wherein the first set of data terminals transmit the read data and the write data with DDR timing, and the access data IO section comprises:

a read data caching module configured to cache the one internal read data;

16. The IO interface of claim 1, wherein the set of control terminals includes a first subset of control terminals for transmitting only at least a portion of the control signals required by the first interface protocol and a second subset of control terminals for transmitting only at least a portion of the control signals required by the second interface protocol, or the set of control terminals includes at least one control terminal multiplexed with the first and second interface protocols, and/or

At least part of the first set of data terminals is also used for transmitting at least part of control signals and/or access data required by the second interface protocol, or at least part of the second set of data terminals is also used for transmitting at least part of control signals and/or access data required by the first interface protocol, and/or

The first interface protocol is xSPI protocol, the second interface protocol is LPDDR protocol, and/or

The number of terminals of the first set of data terminals is 8 and the number of terminals of the second set of data terminals is 64.

17. A pseudo-static random access memory, comprising:

the IO interface of any one of claims 1-16;

A memory array;

And the access processing part is configured to perform corresponding access operation on the storage array according to the result of instruction decoding processing performed by the control logic part in the IO interface.

18. A method for accessing the pseudo-static random access memory according to claim 17, comprising:

receiving the mode register value via the first set of data terminals or the first portion of terminals;

receiving the instruction value via the first set of data terminals or the first portion of terminals;

according to the interface protocol selection signal in the mode register value, utilizing corresponding one of the first control logic module and the second control logic module to implement instruction decoding processing on the instruction value, and

And according to the result of the instruction decoding processing, performing corresponding access operation on the storage array by using the access processing part.

19. An electronic device, comprising:

The pseudo-static random access memory of claim 17, and

A first host coupled to the first set of data terminals in the IO interface in the pseudo-static random access memory and a first subset of control terminals in the set of control terminals for transmitting control signals required for the first interface protocol and configured to input the mode register value to the IO interface via the first set of data terminals or the first portion of terminals when accessing the pseudo-static random access memory such that the interface protocol selection signal indicates that the first interface protocol mode is currently selected.

20. The electronic device of claim 19, further comprising: