CN121237145A

CN121237145A - Storage control module, memory controller and 3D stacked memory

Info

Publication number: CN121237145A
Application number: CN202511332388.XA
Authority: CN
Inventors: 董俞鹏
Original assignee: Beijing Qingyun Technology Co ltd
Current assignee: Beijing Qingyun Technology Co ltd
Priority date: 2025-06-10
Filing date: 2025-06-10
Publication date: 2025-12-30
Also published as: CN120319284B; CN120319284A

Abstract

This invention provides a storage control module, a memory controller, and a three-dimensional stacked memory. When managing the execution of multiple operation instructions for corresponding storage units (including multiple stacked storage arrays, each with a latching circuit) in a memory stack, it can handle the timing of these operation instructions. If the previous operation instruction of the first storage array is not completed and the next operation instruction of the second storage array is received, the chip select signal is switched in advance. After the chip select signal is switched, while the second storage array is executing the next operation instruction, the first storage array will continue to execute the previous operation instruction according to its latched execution line address. This allows for parallel access to the multiple storage arrays of the memory, relatively saving some unavoidable internal latency of the memory, reducing access bubbles, and improving the bandwidth utilization of the memory.

Description

Memory control module, memory controller and three-dimensional stacked memory

Information about the divisional application

The application is a divisional application of a parent application with the application number of CN202510772555.6, the application date of 2025, 06 and 10, and the application name of a memory control module, a memory controller and a three-dimensional stacked memory.

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a memory control module, a memory controller, and a three-dimensional stacked memory.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a commonly used memory whose bandwidth utilization is often one of the key parameters for evaluating memory performance, which is decisive for the overall performance of the system. With the progress of process technology, the novel memory architecture formed by the Through Silicon Via (TSV) hybrid bonding technology and the like continuously improves the bandwidth utilization rate of the three-dimensional (3D) stacked DRAM, but the conventional DRAM controller adopts a single-layer scheduling strategy, cannot effectively coordinate parallel access of the multi-layer stack, and naturally restricts the bandwidth utilization rate due to unavoidable delays such as tRCD (RAS to CASDelay, row-to-column delay), tRP (Row PRECHARGE TIME) and the like in the DRAM.

Therefore, how to improve the bandwidth utilization of the three-dimensional stacked memory such as DRAM is one of the hot technical problems to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a memory control module, a memory controller and a three-dimensional stacked memory, which can relatively save some unavoidable delay in the memory when managing execution of a plurality of operation instructions to corresponding memory units in a memory stack, thereby improving the bandwidth utilization rate of the memory.

In order to achieve the above object, the present invention provides a memory control module for controlling execution of a plurality of operation instructions of a corresponding memory cell in a memory stack, the memory cell including a plurality of stacked memory array banks, each of the memory array banks having a latch circuit, the memory control module being configured to:

Activating a chip selection signal corresponding to the storage unit according to the decoding information of each operation instruction so as to select a corresponding storage array body in the storage unit for access, latching the execution address of the operation instruction through a latch circuit in the selected storage array body, and enabling the selected storage array body to execute the operation instruction;

And under the condition that a first storage array body in the plurality of storage array bodies is selected to execute a last operation instruction, and the last operation instruction is not executed and a next operation instruction is received, switching a chip selection signal corresponding to the next operation instruction in advance to select a second storage array body in the plurality of storage array bodies, and further after the chip selection signal is switched, continuously executing the last operation instruction by the first storage array body according to the latched execution address while executing the next operation instruction by the second storage array body.

Optionally, the storage control module includes:

A user interface, configured to receive decoding information of each operation instruction in the plurality of operation instructions, where the decoding information of each operation instruction includes an execution address of the operation instruction and a line activation start signal;

And the storage control logic is coupled with the user interface and the storage interface of the storage unit and is used for providing corresponding chip selection signals, row address signals, column address signals, row activation signals and column enabling signals for the storage unit according to the decoding information of each operation instruction, so that the selected first storage array bank or second storage array bank executes the corresponding operation instruction and simultaneously realizes the switching of the chip selection signals.

Optionally, the memory control logic is configured to perform the following:

At a first moment, the storage control logic receives an execution address of the last operation instruction according to a row activation start signal of the last operation instruction, and activates a last chip selection signal corresponding to the first storage array body to select the first storage array body to access after a first delay;

At a second moment, the storage control logic receives an execution address of the next operation instruction according to a row activation start signal of the next operation instruction, activates a next chip selection signal corresponding to the second storage array body to select the second storage array body to access after a first delay, and during the period, the first storage array body continues to execute the previous operation instruction according to the execution address latched by the first storage array body;

At a third moment, the first storage array body executes the last operation instruction, the storage control logic finishes accessing the first storage array body, and after a second delay, the storage control logic closes the last chip selection signal;

At a fourth moment, the storage control logic receives an execution address of a next operation instruction according to a row activation start signal of the next operation instruction, and activates a next chip selection signal corresponding to the storage unit after a first delay so as to select a third storage array body in the storage unit to access, wherein the second storage array body continues to execute the next operation instruction according to the latched execution address of the third storage array body, and the third storage array body is identical to or different from the first storage array body;

and at a fifth moment, the second storage array body executes the next operation instruction, the storage control logic finishes accessing the second storage array body, and after a second delay, the storage control logic closes the next chip selection signal.

Optionally, the storage control logic analyzes information of the last chip select signal and/or the next chip select signal from a high-order address of an execution address of the last operation instruction and/or the next operation instruction.

Optionally, the first delay and the second delay are each measured in units of clock cycles, and the first delay is equal to 1 clock cycle.

Optionally, the last operation instruction is a read instruction, the second delay is a read precharge delay, after the user interface sends the execution column address of the last operation instruction, the user column enable signal received by the user interface is pulled down, and after the second delay, the line activation end signal received by the user interface is pulled up to indicate that the last operation instruction is executed, and/or the next operation instruction is a read instruction, the second delay is a read precharge delay, after the user interface sends the execution column address of the next operation instruction, the user column enable signal received by the user interface is pulled down, and after the second delay, the line activation end signal received by the user interface is pulled up to indicate that the next operation instruction is executed.

Optionally, a latch circuit in the first memory array bank is activated in response to the last chip select signal to latch an execution address of the last operation instruction and cause the first memory array bank to start executing the last operation instruction, and/or a latch circuit in the second memory array bank is activated in response to the next chip select signal to latch an execution address of the next operation instruction and cause the second memory array bank to start executing the next operation instruction.

Optionally, the memory control module simultaneously manages a plurality of memory cells in the memory stack, each memory cell includes a stacked plurality of memory array banks, and each memory array bank includes a plurality of word lines corresponding to a plurality of rows and a plurality of bit lines corresponding to a plurality of columns.

Based on the same inventive concept, the present invention also provides a memory controller for controlling execution of a plurality of operation instructions of a corresponding memory stack, each memory unit in the memory stack including a stacked multi-chip memory array, each of the memory array having a latch circuit, the memory controller including a plurality of host interfaces, a memory control management module, and a plurality of memory control modules according to the present invention, wherein:

Each main equipment interface is in communication connection with a corresponding main equipment and is used for receiving an operation instruction to be executed, wherein each main equipment interface is a multi-IO parallel interface;

The memory control management module is coupled with the main equipment interface and each memory control module, and is used for analyzing each operation instruction received by the main equipment interface to generate corresponding decoding information, judging a memory control module and a memory unit hit by each operation instruction according to the decoding information, and further providing the decoding information of the operation instruction for the hit memory control module;

Each storage control module is coupled with at least one storage unit in the storage stack body and is used for receiving corresponding decoding information, accessing the storage unit coupled with the storage control module according to the decoding information, and controlling the storage unit to execute corresponding operation instructions.

Optionally, the memory control management module includes a control manager and an address decoder;

The control manager is coupled to each host device interface, each address decoder and each storage control module, and is configured to send an address of an operation instruction to be executed received by the host device interface to the address decoder for address resolution, so as to determine a storage control module hit by each operation instruction to be executed, a hit storage unit and a hit row in the hit storage unit, and further send a row address of the hit row resolved by the address decoder to the hit storage control module.

Optionally, the memory controller is disposed on a buffer die, the memory stack includes stacked multi-layer memory dies, each memory array in each memory cell is a portion of the memory die of the corresponding die, and the multi-layer memory dies and the buffer die are bonded together through a through-silicon via.

Optionally, the master device is located on a logic die, the buffer die, and the memory stack are stacked in sequence, and the logic die and the buffer die are bonded together through a through silicon via hybrid.

Based on the same inventive concept, the invention also provides a three-dimensional stacked memory, which comprises a memory stack body and a memory controller according to the invention, wherein the memory controller is arranged on a buffer bare chip, the memory stack body comprises three-dimensional stacked multi-layer memory bare chips, and the multi-layer memory bare chips and the buffer bare chips are bonded through silicon through holes in a mixed mode.

Compared with the prior art, the memory control module, the memory controller and the three-dimensional stacked memory provided by the invention can process the execution time sequence of a plurality of operation instructions of a memory stack body when the corresponding memory unit (comprising a plurality of stacked memory array bodies, each memory array body is provided with a latch circuit) is managed, and under the condition that the execution of the last operation instruction of a first memory array body is not completed and the next operation instruction of a second memory array body is received, the chip selection signal corresponding to the next operation instruction can be switched in advance, and further after the chip selection signal is switched, the first memory array body can continue to execute the last operation instruction according to the execution address latched by the second memory array body while the next operation instruction is executed, so that a plurality of memory array bodies of the memory can be accessed in parallel, some unavoidable internal delays (such as tRP, tRCD and the like) of the memory are relatively saved, and the effects of reducing the access bubbles and improving the bandwidth utilization rate of the memory are achieved.

Drawings

Those of ordinary skill in the art will appreciate that the figures are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Wherein:

FIG. 1 is a schematic diagram of an operation instruction processing method of a conventional DRAM controller.

FIG. 2 is a schematic diagram illustrating a memory control module according to an embodiment of the invention.

Fig. 3 to 5 are timing diagrams illustrating the execution of the memory control module according to an embodiment of the invention.

FIG. 6 is a schematic diagram illustrating a memory control module according to another embodiment of the invention.

FIG. 7 is a schematic diagram of a memory controller according to an embodiment of the invention.

Fig. 8 is a schematic diagram of a package structure of a three-dimensional stacked memory according to an embodiment of the invention.

FIG. 9 is a schematic diagram of a memory array bank in a three-dimensional stacked memory according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention. It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element is referred to as being "connected to," "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Referring to fig. 1, when the current DRAM controller receives A, B, C read operation instructions, the three read operation instructions are sent to the DRAM interface (i.e., the memory interface for implementing the communication between the memory array and the DRAM controller) in the sequence of A, B, C. This is due to the inevitable delays of DRAM internal tRDD (Row to Row Delay), tRCD (RAS to CAS Delay, row to column Delay), tRAS (min) (MIN RAS ACTIVE TIME, minimum Row activation time), tRP (Row PRECHARGE TIME ), tRC (min) (min Row CYCLE TIME, minimum Row cycle time), tRTP (Read to PRECHARGE DELAY ), etc., which require 54 clock cycles (1 clock cycle may be denoted as "1 CLK") for the DRAM controller to send A, B, C these 3 Read instructions all to the DRAM interface. Obviously, delays such as tRP, tRCD and the like in the DRAM are unavoidable, and naturally constraint is imposed on the bandwidth utilization of the DRAM interface, and the efficiency is low.

Where tRCD represents the minimum delay time from a row "activate command (or" activate instruction ") to a column address command (i.e., the execution column address of a send read/write instruction), measured in clock cycles CLK. When a memory controller of a memory activates a row (opens a row), it is necessary to wait tRCD time before performing a read or write operation on that row. This is to ensure that the capacitive charge of the cells in the row is stable, thereby reliably accessing the data.

TRP represents the latency, measured in clock cycles CLK, required to re-activate a new row in the same Bank after the current row (row) is turned off by executing a Precharge command (or "Precharge command"). The precharge closes the currently open row and prepares for the next row activation. the tRP ensures that the capacitance of the cell has enough time to recover to the initial state, avoiding data collision. After closing the current line (via the Precharge command), it is necessary to wait for the tRP time before a new ACTIVE command can be sent.

TRTP represents the minimum delay time measured in clock cycles CLK from the time the "read" instruction is sent to the time the "Precharge" instruction is allowed to be sent. tRTP ensures that after the read operation is completed (i.e., the read instruction is completed), data has been transferred from the memory unit DU to the sense amplifier (SENSE AMPLIFIER) and the current row is turned off. Note that tRTP is only for read operations (i.e., only for read instructions), the write operation may be directly followed by a precharge (without tRTP waiting).

Based on this, please refer to fig. 2 to 9, an embodiment of the present invention provides a memory control module IP for controlling execution of a plurality of operation instructions (i.e. a plurality of operation instructions to be executed, such as a plurality of read instructions) of a corresponding memory unit DU (which may also be referred to as a "data unit") in the memory stack 3, the memory unit DU includes a plurality of stacked memory array banks, each memory array bank has a latch circuit (latch) 30b, and the memory control module IP is configured to:

According to the decoding information (such as row address signal mc_radd and row activation start signal mc_ WLACT) of each operation instruction, activating a chip selection signal du_cs corresponding to the memory unit DU to select a corresponding one of the memory array banks for access, and further latching the execution address (such as row address signal mc_radd and column address signal mc_cadd) of the operation instruction by the latch circuit 30b in the selected memory array bank, and making the selected memory array bank execute the operation instruction;

When a first memory array bank of the multi-chip memory array banks of the memory unit DU is selected to execute a previous operation instruction, and the previous operation instruction is not executed and a next operation instruction is received, a chip selection signal corresponding to the next operation instruction is switched in advance to select a second memory array bank of the multi-chip memory array banks of the memory unit DU, and after the chip selection signal is switched (for example, from du_cs0 to du_cs1), the first memory array bank continues to execute the previous operation instruction according to an execution address latched by the second memory array bank while the second memory array bank executes the next operation instruction.

Therefore, the storage control module IP can parallelize access to the multi-chip storage array of the storage unit DU, thereby relatively saving some unavoidable delays (such as saving tRP and tRCD) in the storage, achieving the effects of reducing access bubbles and improving the bandwidth utilization rate of the storage, thereby improving the bandwidth utilization rate, and being simpler in algorithm realization.

The plurality of operation instructions may be read (read) instructions, write (write) instructions, a mixture of read and write instructions, or other operation instructions such as refresh instructions.

Referring to fig. 2 and 7-8, in an example, the memory stack 3 includes j+1 memory dies (Die) 300-30 j, j being greater than or equal to 1 and being an integer, and the j+1 memory dies 300-30 j can be three-dimensionally stacked together by means of through-silicon via (TSV) Hybrid Bonding. Thus, each memory unit DU in the memory stack 3 includes a stacked j+1-chip memory array, each of which is part of a corresponding one of the memory dies (Die) 300-30 j, and thus each memory unit DU corresponds to j+1 chip select signals DU_CS 0-DU_CSj (the chip select signals are not all shown in FIGS. 2 and 6). The j+1 pieces of memory array bodies in each memory unit DU are also bonded together through the silicon through holes in a mixed mode, so that corresponding silicon through hole mixed bonding paths are formed.

In addition, each memory die 300-30 j may be any suitable type of memory die structure, such as DRAM. The DRAM may be any of a wide I/O DRAM such as Synchronous DRAM (SDRAM), among others. The memory stack 3 may be implemented as an Unbuffered Dual Inline Memory Module (UDIMM), a Registered DIMM (RDIMM), a reduced load DIMM (LRDIMM), a Fully Buffered DIMM (FBDIMM), a small outline DIMM (sodim), or the like.

The through silicon via hybrid bonding technology expands the capacity of the storage unit DU managed by the storage control module IP on one hand, and further expands the capacity of the memory stack 3 managed by the corresponding memory controller, and reduces the chip area, on the other hand, the storage control module IP can load (load) corresponding information or data into the interior of the storage unit DU or into each storage unit DU managed by the storage control module IP through the through silicon via TSV through way, so as to solve the problem of occupying a large amount of wires when loading the information through special routing (e.g., EFUSE bus wires) in the prior art.

Referring to fig. 2 and 9, each memory array body of each memory unit DU has a corresponding memory array (array) in addition to the latch circuit 30b, the memory array is formed by a plurality of word lines WL (each word line may be regarded as a row), a plurality of bit lines BL (each bit line may be regarded as a column), and a plurality of cells (cell cells) defined by crossing the word lines WL and the bit lines BL, each cell is located at the crossing point of the corresponding one word line WL and one bit line BL, that is, corresponding to one memory address, each word line WL (word line) is addressed by a Row Address (RADD) in the corresponding memory address, and each bit line BL (bit line) is addressed by a column address (column address, CADD) in the corresponding memory address. One of the storage units DU may be any suitable level of management unit higher than the cell level, such as one storage block (block) or one sector (sector) or one page (page) of the memory stack 3. One page includes a plurality of bytes (an address range of which may be determined by a plurality of word lines and a plurality of bit lines), one sector includes a plurality of pages, one memory block includes a plurality of sectors, and a plurality of memory units DU may form one memory array Bank (Bank).

In an example, referring to fig. 2, the storage control module IP includes a user interface IPa and storage control logic IPb.

Referring to fig. 7, the user interface IPa may be coupled to the memory control management module 21 in the memory controller 2 to receive decoding information of each operation instruction provided by the memory control management module 21 and other related information such as the row activation END signal mc_ WLACT _end, wherein the decoding information of each operation instruction includes an execution address of the operation instruction (including a row address mc_radd and a column address mc_cadd accessed by the operation instruction), a row activation START signal mc_ WLACT _start, and so on. The row activation START signal mc_ WLACT _start is used to indicate that an operation command to the storage unit DU STARTs to be executed, and the row activation END signal mc_ WLACT _end is a notification signal used to indicate that an operation command of the storage unit DU ENDs to be normally pulled up at a time delayed by tRTP at the time when the user column enable signal mc_ COLEN is pulled down, while the pull-down time of mc_ COLEN is a time when all CADDs of the operation command are received, and the pull-up time of mc_ COLEN is a time when the pull-up time of mc_ WLACT _start is delayed by tRCD.

In addition, when the operation instruction is a read instruction, the decoding information received by the user interface IPa further includes a user column enable signal mc_ COLEN, where mc_ COLEN is used to instruct the user interface IPa to send the execution column address mc_cadd of the read instruction. The user interface IPa outputs the data signals read out by the memory control logic IPb from the memory cells DU (i.e. mc_dout=dout < >). In addition, referring to fig. 3, when receiving the decoding information of the corresponding read command, the user interface IPa receives the row address mc_radd of the read command, and receives the row activation START signal mc_ WLACT _start of the read command after the delay of the tRA2 WLp.

When the operation command is a write command, the decoding information received by the user interface IPa further includes a user write enable signal mc_we, a user column enable signal mc_ COLEN, a data signal mc_din to be written into the memory unit DU, and the like. The user write enable signal mc_we is used to indicate that data is allowed to be written into the storage unit DU, and the user column enable signal mc_ COLEN is used to indicate that the user interface has sent the execution column address mc_cadd of a corresponding one of the operation instructions.

The storage control logic IPb is coupled to the user interface IPa and the storage interface 30a of the storage unit DU, and based on the decoding information received by the user interface IPa, provides and switches the corresponding chip selection signal du_cs, the row address signal du_radd, the column address signal du_cadd, the row activation signal du_ WLACT, the column activation signal du_ COLEN, and the like to the storage unit DU, so as to select a corresponding one of the storage array banks in the storage unit to access, and latches an execution address (e.g., the row address signal du_radd) of the corresponding operation command through the latch circuit 30b in the selected storage array bank, so that the selected storage array bank performs the corresponding operation command according to the latched execution address.

When a first memory array bank of the memory unit DU (for example, corresponding to the chip select signal du_cs0) performs a previous operation instruction, but in the case that the previous operation instruction is not performed, the memory unit DU receives a next operation instruction again, the memory control logic IPb switches the chip select signal corresponding to the next operation instruction (for example, corresponding to the chip select signal du_cs1) in advance to select a second memory array bank of the memory unit DU for accessing, and further after the chip select signal is switched (for example, from du_cs0 to du_cs1), the first memory array bank still continues to perform the previous operation instruction according to the latched execution address while the second memory array bank performs the next operation instruction.

Optionally, the high-order address of the execution address (for example, the execution row address RADD) of each operation instruction received by the user interface IPa carries chip selection information, and the storage control logic IPb may parse the chip selection signal du_cs corresponding to the operation instruction from the high-order address of the execution address of the corresponding operation instruction received by the storage control logic IPb. In other embodiments of the present invention, the storage control logic IPb may also generate the chip select signal du_cs corresponding to the operation instruction according to the decoding information of the corresponding operation instruction received by the user interface IPa in any other suitable manner.

Referring to fig. 3-5 (where the timings of fig. 3-5 are consecutive), and in conjunction with fig. 2 and 7, the storage control logic IPb is further configured to perform the following sequences to achieve the above functions:

At a first time (i.e., instant 1), the row activation START signal mc_ WLACT _start is pulled high and the RADD1 maps to a piece of memory array bank (i.e., a "first memory array bank", denoted as "die0", for example, 300 in the memory unit DU0 shown in fig. 7) in the decoding information of the current operation instruction (i.e., the "last operation instruction", denoted as CMD1, for example, the read instruction), at which time, the memory control logic IPb receives the execution row address mc_radd of the last operation instruction CMD1 according to the mc_ WLACT _start and outputs the row address signal mc_radd=radd1, and after a first delay (for example, equal to 1), activates (or "generates") the piece select signal (i.e., the last piece select signal, denoted as "du_cs0") of the first memory array bank die0 to select the corresponding memory array bank DU0 to access the corresponding memory array DU0 of the memory unit DU WLACT.

Optionally, the storage control logic IPb parses the information of the du_cs0 from the upper address of the execution row address RADD1 of the last operation command CMD1, thereby generating the du_cs0.

Alternatively, after the generation of du_cs0, mc_ WLACT _start may be changed from high to low to be indicative of the arrival of a subsequent corresponding operation instruction (e.g., a further next operation instruction hereinafter).

Referring to fig. 3, the rising edge of the chip select signal du_cs0 and the rising edge of the row activate signal du_ WLACT are aligned with the falling edge corresponding to the row activate START signal mc_ WLACT _start (i.e., the first falling edge of mc_ WLACT _start in fig. 3-5). After the row activation signal DU_ WLACT is transferred into the first memory array bank die0, the resulting row activation signal is denoted as "WLACT _die0_core", the rising edge of which WLACT _die0_core is aligned with the rising edge of DU_ WLACT, and the falling edge of WLACT _die0_core is aligned with the rising edge of the row activation END signal MC_ WLACT _END (i.e., the rising edge of MC_ WLACT _END in the timing sequence shown in FIG. 4) received by the subsequent user interface IPa.

Further, the latch circuit 30b in the first memory array die0 latches the execution row address RADD1 of the last operation command CMD1 in response to the chip select signal du_cs0 of the last operation command CMD1 being activated.

For example, the latch circuit 30b in the first memory array bank die0 latches the execution row address RADD1 of the last operation command CMD1 at a time 1' (i.e., a falling edge of the internal row latch signal radd_die0_lat) after the time 1, whereby the internal latch row address signal radd_die0_core=radd1 of the first memory array bank die 0.

Referring to fig. 3, the delay of the rising edge of the internal row latch signal radd_die0_lat of the first memory array bank die0 with respect to the rising edge of WLACT _die0_core is the internal delay "core internal delay" of the first memory array bank die0, and the delay of the rising edge of the instant 1' with respect to WLACT _die0_core is the sum of the high-level durations (i.e., the latch time periods) of the internal delay "core internal delay" and radd_die0_lat, which may be equal to the first delay (e.g., equal to 1 CLK) or may not be equal to the first delay, for example.

In addition, when the operation command is a read command, after time 1', the user interface IPa sequentially receives each of the execution column addresses mc_cadd of the previous operation command CMD1, and the received user column enable signal mc_ COLEN is then pulled up, the rising edge of mc_ COLEN is delayed with respect to the rising edge of mc_ WLACT by tRCD, and the storage control logic IPb further sends the read enable signal du_re, each column address signal du_cadd (corresponding to the execution column address mc_cadd), the column enable signal du_ COLEN, the read clock signal du_rdqs, etc. to the first storage array die0 through the storage interface 30a of the storage unit DU according to the received user column enable signal mc_ COLEN and each execution column address mc_cadd of the previous operation command, and further starts to read the data on the corresponding row and the corresponding column, i.e., dio=dout, through the storage interface IPa.

In fig. 3, the delay of the first rising edge of du_ COLEN with respect to the rising edge of du_ WLACT is tRCD, the delay of the first falling edge of the read clock signal du_rdqs with respect to the first rising edge of du_ COLEN is denoted "tCOL RDQS", and the delay of the moment when du_dio starts outputting the data signal DOUT with respect to the first falling edge of the read clock signal du_rdqs is denoted "tRDQS DOUT".

It is noted that, when the CMD1 executed by the first memory array die0 is a read command and the previous operation command CMD0 executed before the CMD1 is a write command, there is a delay tWERE between the rising edge of the read enable signal du_re corresponding to the CMD1 and the falling edge of the write enable signal du_we corresponding to the previous operation command CMD 0.

After that, when the CMD1 is executed for a certain period of time (for example, the time of reaching the time 2-tRAWLp in fig. 4, when CMD1 has not yet been executed), the user interface IPa starts to receive the execution row address mc_radd=radd2 in the decoded information of the next operation instruction (denoted as CMD2, for example, a read instruction).

At a second time (i.e., time 2, which is a time after time 1'), the line activation START signal mc_ WLACT _start in the decoding information of the next operation command CMD2 received by the user interface IPa is pulled high, and the RADD2 maps the second memory array bank (denoted as "die1" in the corresponding memory unit DU (e.g., DU 0), for example, 301 in the memory unit DU0 shown in fig. 7), at this time, the memory control logic IPb receives the execution line address mc_radd of the next operation command CMD2 according to the mc_ WLACT _start, and outputs the line address signal du_radd=radd2, and after a first delay (e.g., equal to 1 CLK), activates (or "generates") the chip select signal of the second memory array bank die1 (i.e., the next chip select signal denoted as "du_cs1") to select the corresponding line access of the second memory array bank die1 in the memory unit DU.

Optionally, the storage control logic IPb parses the information of the du_cs1 from the higher address of the execution row address RADD2 of the next operation command CMD2, thereby generating the du_cs1.

Alternatively, after the generation of du_cs1, mc_ WLACT _start may be changed from high to low again to wait for the arrival of the next operation instruction.

Referring to fig. 4, the row address signal du_radd=radd2 STARTs from the rising edge of the row activation START signal mc_ WLACT _start, and the rising edge of the chip select signal du_cs1 is aligned with the falling edge of the row activation START signal mc_ WLACT _start. After the row activation signal DU_ WLACT is transferred into the second memory array bank die1, the resulting row activation signal is denoted as "WLACT _die1_core", the rising edge of the WLACT _die1_core is aligned with the rising edge of the DU_ WLACT, and the falling edge of WLACT _die1_core is aligned with the rising edge of the row activation END signal MC_ WLACT _END (i.e., the rising edge of MC_ WLACT _END in the timing sequence shown in FIG. 5) received by the subsequent user interface IPa.

Still further, referring to fig. 4 in combination with fig. 2 and 7, the latch circuit 30b in the second memory array die1 latches the execution row address RADD2 of the next operation command CMD2 in response to the chip select signal du_cs1 of the next operation command CMD2 being activated.

For example, the latch circuit 30b in the second memory array bank die1 latches the execution row address RADD2 of the next operation command CMD2 at a time 2' (i.e., a falling edge of the signal radd_die1_lat) after the time 2, thereby latching the internal latch row address signal radd_die1_core=radd2 of the second memory array bank die 1.

With continued reference to fig. 4, the delay of the rising edge of the internal row latch signal radd_die1_lat of the second memory array die1 with respect to the rising edge of WLACT _die1_core is the internal delay "core internal delay" of the second memory array die1, and the delay of the rising edge of the instant 2' with respect to WLACT _die1_core is the sum of the high-level durations (i.e., the latching time periods) of the internal delay "core internal delay" and radd_die1_lat of the second memory array die1, which may be equal to the first delay (e.g., equal to 1 CLK).

With continued reference to fig. 4 and fig. 2 and 7, when the next operation command CMD2 is a read command, after time 2', the user interface IPa sequentially receives each of the execution column addresses mc_cadd of the next operation command CMD2, and then pulls up the received user column enable signal mc_ COLEN, the rising edge of mc_ COLEN is delayed with respect to the rising edge of mc_ WLACT by tRCD, and the storage control logic IPb generates the read enable signal du_re, each of the column address signals du_cadd, the column enable signal du_ COLEN, the read clock signal du_rdqs, and so on according to the user column enable signal mc_ COLEN and each of the execution column addresses mc_cadd of the next operation command CMD2, thereby starting to read the data on the corresponding row and the corresponding column in the second storage array die1, i.e., the data mc_dio=dout, which is fed back through the user interface IPa.

With continued reference to fig. 4 and fig. 2 and 7, during the execution of the CMD2 read command by the second memory array die1, the first memory array die0 continues to execute the previous operation command CMD1 according to the row address RADD1 latched by the latch circuit 30b therein.

When the column address mc_cadd of the last operation command CMD1 is sent to the user interface IPa, the user column enable signal mc_ COLEN received by the user interface IPa is pulled down, and after a second delay (e.g. the precharge delay tRTP is read), the row activation END signal mc_ WLACT _end received by the user interface IPa is pulled up to indicate that the last operation command CMD1 is executed, and then, referring to fig. 4 in combination with fig. 2 and 7, the access of the storage control logic IPb to the first storage array die0 is ended, and the storage control logic IPb may close the du_cs0 (i.e. the du_cs0 is turned low) based on the pulled up mc_ WLACT _end.

During the period mc_ COLEN is low, the column address signal du_cadd received by the first memory array die0 is continuously empty, and the column enable signal du_ COLEN is continuously low.

After that, when the CMD2 is executed for a certain period of time (for example, the time of reaching the time 4-tRAWLp in fig. 4, when CMD1 is already executed and CMD2 is not yet executed), the user interface IPa starts to receive the execution row address mc_radd=radd3 in the decoding information of the next operation instruction (denoted as CMD3, for example, a read instruction).

At a fourth time (i.e. time 4, which is a time after time 3), please refer to fig. 5 and combine fig. 2 and 7, in which the user interface IPa receives the execution row address mc_radd=radd3 in the decoding information of the next operation command CMD3, the row activation START signal mc_ WLACT _start is pulled up again, and the RADD3 maps one of the memory array banks (e.g. still the first memory array bank 0) except the second memory array bank 1 in the corresponding memory unit DU (e.g. DU 0), in other examples, it may also be other memory array banks except die 0-die 1, hereinafter taking die0 as an example), at this time, the memory control logic IPb receives the execution row address mc_radd of the next operation command CMD3 according to the row activation START signal mc_ WLACT _start of the next operation command CMD3, and outputs a corresponding row address signal du_radd=radd 3 after the first memory array bank is delayed (e.g. corresponding to die 0) and the corresponding memory array bank 3 is accessed (e.g. corresponding to die 0) in the memory array cell (e.g. corresponding to die 0). Alternatively, after the chip select signal is generated, mc_ WLACT _start may be changed from high to low again to be instructed to come again by the next operation instruction.

Referring to fig. 5, the row address signal du_radd=radd3 STARTs from the rising edge corresponding to the row activation START signal mc_ WLACT _start, and the rising edge of the chip select signal du_cs0 is aligned with the falling edge of the row activation START signal mc_ WLACT _start.

Optionally, the storage control logic IPb parses the information of du_cs0 from the higher address of the execution row address RADD3 of the next operation command CMD3, and further generates du_cs0 again.

Further, referring to fig. 5 in conjunction with fig. 2 and 7, after the first memory array die0 corresponding to cmd3 is selected again, the row activation signal WLACT _die0_core is generated again inside the first memory array die0, and the rising edge of the WLACT _die0_core is aligned with the rising edge of the chip select signal du_cs0.

Still further, referring to fig. 5 in combination with fig. 2 and 7, the latch circuit 30b in the first memory array die0 latches the execution row address RADD3 of the next operation command CMD2 in response to the chip select signal du_cs0 of the next operation command CMD3 being activated. For example, the latch circuit 30b in the first memory array bank die0 latches the execution row address RADD3 of the further next operation command CMD3 at a time 3' (i.e., a falling edge of the internal row latch signal radd_die0_lat) after the time 4, whereby the internal latch row address signal radd_die0_core=radd3 of the first memory array bank die 0.

With continued reference to fig. 5 and fig. 4, 2 and 7, when the next operation command CMD3 is a read command, after time 3', the user interface IPa sequentially receives each of the execution column addresses mc_cadd of the next operation command CMD3, and the received user column enable signal mc_ COLEN is then pulled high, the rising edge of mc_ COLEN is delayed with respect to the rising edge of mc_ WLACT by tRCD, and the storage control logic IPb generates a read enable signal du_re, each of the column address signals du_cadd, du_ COLEN, a read clock signal du_rdqs, and the like according to the user column enable signal mc_ COLEN and each of the execution column addresses mc_cadd of the next operation command CMD3, thereby starting to read the data on the corresponding row and the corresponding column in the first storage array die0, i.e., i.d_dio=dout, and feeding back the read data mc_dout=dout through the user interface IPa.

With continued reference to fig. 5 and fig. 2 and 7, during the execution of the CMD3 read command by the first memory array die0, the second memory array die1 continues to execute the next operation command CMD2 according to the row address RADD2 latched by the latch circuit 30b therein.

When the execution column address mc_cadd of the next operation command CMD2 is sent to the user interface IPa, the user column enable signal mc_ COLEN received by the user interface IPa is pulled down, and after a second delay (e.g. the precharge delay tRTP is read), the row activation END signal mc_ WLACT _end received by the user interface IPa is pulled up to indicate that the next operation command CMD2 is executed, and at this time, please refer to fig. 5 in combination with fig. 2 and 7, the access of the storage control logic IPb to the second storage array die1 is ended, and the storage control logic IPb may close the du_cs1 (i.e. the du_cs1 is turned low) based on the pulled up mc_ WLACT _end.

And the following principle is that the execution of the following operation instructions of the storage unit DU is continued according to the time sequence principle, and the cut-layer access of the storage array bodies in the storage unit DU is realized according to the operation instructions and the time sequence control.

Therefore, the execution of the operation instructions of the storage array bodies of different slices in the storage unit can be processed, the execution time sequence of the operation instructions can be processed, under the condition that the execution of the last operation instruction of the first storage array body is not finished and the next operation instruction of the second storage array body is received, the slice selection signal corresponding to the next operation instruction is switched in advance, further after the slice selection signal is switched, the second storage array body executes the next operation instruction, and meanwhile, the first storage array body can continue to execute the last operation instruction according to the latched execution address of the second storage array body, so that multiple storage array bodies of the storage can be accessed in parallel, some unavoidable internal delays (such as tRP, tRCD and the like) of the storage can be relatively saved, the data stream MC_DOUT returned by the user interface IPa can be continuous as far as possible, and the effects of reducing the access bubbles and improving the bandwidth utilization rate of the storage can be achieved.

The above examples are all exemplified by the storage control module IP controlling one storage unit DU, but the technical solution of the present invention is not limited thereto. In other examples, referring to fig. 6 and 7, one storage control module IP may further control k+1 storage units DU 0-DUk, where k is an integer and k is greater than or equal to 1. Each memory cell includes a plurality of word lines corresponding to a plurality of rows and a plurality of bit lines corresponding to a plurality of columns. The storage control module IP may find a hit (hit) storage unit according to the execution address of each operation instruction received by the user interface IPa, so as to perform the above timing control on the execution of the operation instruction of the storage array banks of different slices in the hit storage unit, so as to parallelize access to the multiple storage array banks of the hit storage unit, thereby relatively saving some unavoidable internal delays.

Based on the same inventive concept, please refer to fig. 6 and 7, an embodiment of the present invention further provides a memory controller 2 for controlling execution of a plurality of operation instructions of a corresponding memory stack 3, wherein each memory unit DU in the memory stack 3 includes a plurality of stacked memory array banks, each memory array bank has a latch circuit 30b, and the memory controller 2 includes m master interfaces 20_0-20_m-1, a memory control management module 21, and n+1 memory control modules IP 0-IPn according to the present invention.

The Master interface 20_0 to 20_m-1 is used for being in communication connection with a Master (i.e. a device accessing a memory) 1, realizing interface conversion between the Master 1 and the memory stack 3, receiving an operation instruction sent by the Master 1 and data to be written into the memory stack 3, and returning the read data to the Master 1. The master device interface 20_0-20_m-1 may be any suitable parallel communication protocol interface supporting multiple IOs, for example, AXI (Advanced eXtensible Interface) interfaces, where the AXI interface is an on-chip bus interface facing to a high-performance, high-bandwidth and low-latency master-slave architecture, and its address, instruction and data phases are separated, supporting misaligned data transmission, and in burst transmission, only a first address is needed, and meanwhile, a separate read-write data channel is needed, and supporting larger to-be-executed instructions outstanding (for example, the number of outstanding transactions such as read-write instructions) to transmit access and out-of-order access, and being easier to perform timing convergence, so that the device is suitable for high-speed memory access. It should be noted that although the AXI protocol is illustrated in the drawings, the present invention is not limited thereto, and any other suitable high-bandwidth interface protocol may be adopted by the master interfaces 20_0 to 20_m-1, such as the AHB (ADVANCED HIGH-performance Bus) protocol or the CHI (Coherent Hub Interface) protocol.

The host device 1 may comprise a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a network processor, an Application Processor (AP), a Field Programmable Gate Array (FPGA), a dedicated processor, or any type of processing device with computing processing capabilities that may be configured to execute instructions or software (including code, an operating system, an application program, etc.), firmware, or a combination thereof that is executable with one or more computers.

The memory control management module 21 is coupled to each of the master interfaces 20_0-20_m-1 and each of the memory control modules IP 0-IPn, and is configured to parse each operation command received by the master interfaces 20_0-20_m-1 to generate corresponding decoding information, further determine the memory control module IP and the memory unit DU hit by each operation command according to the decoding information, and further provide the decoding information of the operation command and the data to be written mc_din to the hit memory control module IP, which includes mc_radd, mc_ WLACT _start, mc_ WLACT _end, mc_we, mc_colen, mc_cadd, and the like.

Each storage control module IP is coupled to at least one storage unit DU in the corresponding memory stack 3, and is configured to receive corresponding decoding information, and further implement access to the storage unit DU coupled thereto according to the decoding information, and control the storage unit DU to execute a corresponding operation instruction.

Optionally, referring to fig. 7, the memory control management module 21 includes a control manager 211 and an address decoder 212. The control manager 211 is coupled to each of the master interfaces 20_0-20_m-1, the address decoder 212, and each of the storage control modules IP 0-IPn, and the control manager 211 is configured to send the address of the operation instruction to be executed received by the master interfaces 20_0-20_m-1 to the address decoder 212 for address resolution, so as to determine the storage control module IP hit by each of the operation instructions to be executed, the hit storage unit DU, and the row hit in the hit storage unit, and further transmit the row address of the hit row resolved by the address decoder 212 to the hit storage control module IP.

Optionally, referring to fig. 8, the memory controller 2 is disposed on the buffer die 200, the memory stack 3 includes stacked j+1 layers of memory dies 300-30 j, and each memory array in each memory unit DU is a part of the memory dies of the corresponding chip, so that each memory unit DU has stacked j+1 pieces of memory arrays and corresponds to j+1 pieces of chip select signals du_cs0-du_csj one by one, and the multi-layer memory dies 300-30 j and the buffer die 200 are bonded together through silicon vias.

Alternatively, referring to fig. 7 and 8, the master 1 is located on a logic die 100, the buffer die 200, and the memory stack 3 are stacked in sequence, and the logic die 100 and the buffer die 200 are bonded by through-silicon via hybrid.

It should be understood that the memory controller 2 may implement the conversion of the interface between the host device 1 and the j+1 layer memory die 300-30 j, and complete the address decoding between the host device 1 and the j+1 layer memory die 300-30 j, the conversion of the data format (such as the data bit width), and the conversion of the operation instructions sent by the host device 1 into the signals that can be identified by the j+1 layer memory die 300-30 j, such as the read, write, refresh, etc., so as to implement the necessary control (including the control of the address signal, the data signal, and the various instruction signals) of the host device 1 to the refresh operation, the read/write operation, etc. of the j+1 layer memory die 300-30 j, so that the host device 1 can access (or "use", "operate") the memory resources (i.e. the corresponding memory cells) on the j+1 layer memory die 300-30 j according to the needs of the user, so that the internal circuit of the memory controller 2 may not be limited to the host device interface 20-20 m-1, the memory management module 21-21 and the memory module 21-21 may not be limited to any other specific modules or any other modules may be controlled by the IP-management modules, and any other modules may not need to be controlled by the IP-21.

Based on the same inventive concept, please refer to fig. 7 and 8, an embodiment of the present invention further provides a three-dimensional stacked memory, which includes a memory stack 3 and a memory controller 2 according to the present invention, wherein the memory controller 2 is disposed on the buffer die 200, and the memory stack 3 includes j+1 layers of memory dies 300-30 j stacked in three dimensions, wherein the memory dies 300-30 j and the buffer die 200 are bonded through a through-silicon via hybrid.

The memory controller and the three-dimensional stacked memory provided by the invention adopt the memory control module, so that the memory control module is used for controlling the switching of chip selection signals in the three-dimensional stacked memory, and in cooperation with the latching of the latch circuit in the three-dimensional stacked memory, a plurality of channels (namely, multi-layer bare chips) of the three-dimensional stacked memory are accessed in a parallelization manner, the influence of some internal delays of the three-dimensional stacked memory is reduced, and the purposes of reducing access bubbles, improving the interface data continuity of the memory controller and improving the bandwidth utilization rate are achieved.

The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present invention.

Claims

1. A memory control module for controlling execution of a plurality of operation instructions of a corresponding memory cell in a memory stack, the memory cell comprising a plurality of stacked memory array banks, each of the memory array banks having a latch circuit, the memory control module being configured to:

activating a chip selection signal corresponding to the storage unit according to the decoding information of each operation instruction so as to select a corresponding storage array body in the storage unit for access, latching an execution row address of the operation instruction through a latch circuit in the selected storage array body, and enabling the selected storage array body to execute the operation instruction;

And under the condition that a first storage array body in the plurality of storage array bodies is selected to execute a last operation instruction, and the last operation instruction is not executed and a next operation instruction is received, switching a chip selection signal corresponding to the next operation instruction in advance so as to select a second storage array body in the plurality of storage array bodies, and further after the chip selection signal is switched, continuously executing the last operation instruction by the first storage array body according to the latched execution row address while executing the next operation instruction by the second storage array body.

2. The storage control module of claim 1, comprising:

a memory control logic coupled to the user interface and the memory interface of the memory unit, and configured to provide the memory unit with corresponding chip select signals, row address signals, column address signals, row activation signals, and column enable signals according to the decoding information of each of the operation instructions, to enable the selected first memory array bank or the second memory array bank to execute the corresponding operation instruction while implementing the switching of the chip select signals, and/or

The execution address of the operation instruction comprises the execution row address and the execution column address accessed by the operation instruction.

3. The memory control module of claim 2, wherein the memory control logic is configured to perform the following:

At a first moment, the storage control logic receives an execution row address of the last operation instruction according to a row activation start signal of the last operation instruction, and activates a last chip selection signal corresponding to the first storage array body to select the first storage array body to access after a first delay;

At a second moment, the storage control logic receives an execution row address of the next operation instruction according to a row activation start signal of the next operation instruction, activates a next chip selection signal corresponding to the second storage array body to select the second storage array body to access after a first delay, and during the period, the first storage array body continues to execute the previous operation instruction according to the execution row address latched by the first storage array body;

At a fourth moment, the storage control logic receives an execution row address of a next operation instruction according to a row activation start signal of the next operation instruction, and activates a next chip selection signal corresponding to the storage unit after a first delay so as to select a third storage array body in the storage unit to access, wherein the second storage array body continues to execute the next operation instruction according to the execution row address latched by the second storage array body, and the third storage array body is identical to or different from the first storage array body;

4. A memory control module according to claim 3, wherein the memory control logic is adapted to parse information of the last chip select signal and/or the next chip select signal from a higher address of an execution row address of the last operation instruction and/or the next operation instruction.

5. The memory control module of claim 3 wherein the first delay and the second delay are each measured in units of clock cycles and the first delay is equal to 1 clock cycle.

6. The memory control module of claim 3 wherein said last operation instruction is a read instruction, said second delay is a read precharge delay, after said user interface has sent an execution column address of said last operation instruction, a user column enable signal received by said user interface is pulled low, and after said second delay, a row activation end signal received by said user interface is pulled high to indicate that said last operation instruction has been executed, and/or said next operation instruction is a read instruction, said second delay is a read precharge delay, an execution column address of said next operation instruction is sent at said user interface, said user column enable signal received by said user interface is pulled low, and after said second delay, said row activation end signal received by said user interface is pulled high to indicate that said next operation instruction has been executed.

7. The memory control module of claim 3 wherein the latch circuit in the first memory array bank is activated in response to the last chip select signal to latch an execution row address of the last operation instruction and to cause the first memory array bank to begin executing the last operation instruction, and/or wherein the latch circuit in the second memory array bank is activated in response to the next chip select signal to latch an execution row address of the next operation instruction and to cause the second memory array bank to begin executing the next operation instruction.

8. The memory control module of any of claims 1-7, wherein the memory control module simultaneously manages a plurality of memory cells in the memory stack, each of the memory cells comprising a stacked plurality of memory array banks, each of the memory array banks comprising a plurality of word lines corresponding to a plurality of rows and a plurality of bit lines corresponding to a plurality of columns.

9. A memory controller for controlling execution of a plurality of operating instructions of a corresponding memory stack, wherein each memory cell in the memory stack comprises a stacked multi-chip memory array having latch circuitry, the memory controller comprising a plurality of master interfaces, a memory control management module, and a plurality of memory control modules as recited in any one of claims 1-8, wherein:

10. The memory controller of claim 9, wherein the memory control management module comprises a control manager and an address decoder;

11. The memory controller of claim 9 or 10, wherein the memory controller is disposed at buffer die, the memory stack comprises stacked multi-layer memory die, each memory array bank in each of the memory cells is part of the memory die of a corresponding die, and the multi-layer memory die and the buffer die are bonded together by a hybrid of through-silicon vias.

12. The memory controller of claim 11, wherein the master device is located at a logic die, the buffer die, and the memory stack are stacked in sequence, and the logic die and the buffer die are hybrid bonded by through silicon vias.

13. A three-dimensional stacked memory comprising a memory stack and a memory controller as claimed in any one of claims 9-12, the memory controller being disposed at a buffer die, the memory stack comprising three-dimensionally stacked multi-layer memory dies, wherein the multi-layer memory dies are bonded together and with the buffer die by a hybrid through-silicon-via bond.