CN121237148A - Memory refresh control methods, memory refresh control circuits, and electronic devices - Google Patents

Abstract

The application provides a memory refresh control method, a memory refresh control circuit and electronic equipment, wherein the method comprises the steps of obtaining command information of a plurality of read-write commands of a current memory bank, wherein the current memory bank is any one of a plurality of memory banks; and determining the refresh time sequence of the current memory bank during the execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank. In addition, the command information of the read-write command and the refresh time interval of the current memory bank are comprehensively considered, so that the extra time loss caused by the interruption of the read-write command can be effectively reduced, and the effective bandwidth of the read-write access of the memory is improved.

Description

Memory refresh control method, memory refresh control circuit and electronic device

Technical Field

The present application relates to the field of chip memory control technologies, and in particular, to a memory refresh control method, a memory refresh control circuit, and an electronic device.

Background

Double-rate synchronous dynamic random access memory (Double DATA RATE SDRAM, DDR) is widely used on System on Chips (SoC), and the effective access bandwidth of DDR is one of the important factors restricting the performance of the System on Chips.

In order to maintain the stability of the internal data, the DDR controller needs to perform a refresh operation by sending a refresh command to the memory bank at a certain interval. While the refresh mechanism of DDR greatly affects the effective access bandwidth of DDR. Specifically, there are two modes of DDR memory refresh that are currently most commonly used. The first is to refresh all banks at once, and the second is to refresh only one Bank at a time, and the refreshing of all banks is done in multiple passes.

In the latter case, the refresh command doubles assuming more banks in the DDR memory. In practice, since the read-write access cannot be performed during the refresh, under the condition of more refresh commands and banks, the condition that the read-write operation and the refresh operation occur simultaneously is easy to occur, so that the read-write operation can be performed only after the refresh operation is waited, but the effective bandwidth of the read-write operation is reduced in this way.

Disclosure of Invention

The application provides a memory refresh control method, a memory refresh control circuit and electronic equipment, which are used for solving the technical problem that the effective bandwidth of read-write access is reduced when memory bank refresh is carried out in the prior art.

The application provides a memory refresh control method, wherein the memory comprises a plurality of memory banks, and the method comprises the following steps:

Obtaining command information of a plurality of read-write commands of a current repository, wherein the current repository is any one of a plurality of the repositories;

and determining the refresh time sequence of the current memory bank during the execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

In some embodiments, the determining the current bank refresh timing during execution of the read-write commands according to command information of the read-write commands and a refresh time interval of the current bank includes:

According to the command information of the read-write commands and the refreshing time interval of the current memory bank, evaluating the refreshing priority of the memory of the current memory bank to obtain evaluation information;

And determining the current memory bank refreshing time sequence during the execution of a plurality of read-write commands according to the evaluation information.

In some embodiments, the evaluating the priority of the current memory bank refresh according to the command information of the read-write commands and the refresh time interval of the current memory bank to obtain evaluation information includes:

According to command information of a plurality of read-write commands, primarily evaluating the priority of memory refreshing of the current memory bank to obtain primarily evaluated information;

And adjusting the preliminary evaluation information according to the refreshing time interval of the current memory bank to obtain the evaluation information.

In some embodiments, the performing preliminary evaluation on the priority of the current memory bank memory refresh according to the command information of the plurality of read-write commands to obtain preliminary evaluation information includes at least one of the following:

when the command information indicates that a plurality of read-write commands comprise read-write commands with row address switching and/or read-write commands with read-write switching, the preliminary evaluation information indicates that the memory of the current memory bank is refreshed with high priority;

When the command information indicates that a plurality of read-write commands with unchanged row addresses are included in the read-write commands, the preliminary evaluation information indicates that the memory of the current memory bank is refreshed with low priority;

When the command information indicates that the read-write command does not exist in the current memory bank, the preliminary evaluation information indicates that memory refresh of the current memory bank has no timing restriction.

In some embodiments, the adjusting the preliminary evaluation information according to the refresh time interval of the current bank to obtain the evaluation information includes:

The evaluation information is adjusted to a highest priority by the preliminary evaluation information when the refresh time interval of the current bank approaches a time interval threshold.

In some embodiments, the determining the current bank refresh timing during execution of a number of the read-write commands according to the evaluation information includes:

And in response to the evaluation information, inserting a refresh command into a read-write command stream of the current memory bank to form the current memory bank refresh time sequence, wherein the read-write command stream consists of a plurality of read-write commands according to time sequences.

In some embodiments, after determining the current bank refresh timing during execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current bank, the method further comprises:

And carrying out command arbitration on the current memory bank refreshing time sequence during the execution of a plurality of read-write commands.

The application provides a memory refresh control circuit, which comprises a read-write command buffer and a command evaluation module, wherein,

The read-write command buffer is used for buffering a plurality of read-write commands in a current memory bank and command information of the read-write commands, and the current memory bank is any one of a plurality of memory banks;

The command evaluation module is used for timing the refresh time interval of the current memory bank, and triggering the refresh inserter to insert the refresh time sequence of the current memory bank during the execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

In some embodiments, the command evaluation module includes a refresh timer and a read-write command evaluator;

The read-write command evaluator is used for primarily evaluating the priority of the memory refreshing of the current memory bank according to command information of a plurality of read-write commands to obtain primary evaluation information;

The refresh timer is further configured to adjust the preliminary evaluation information according to a refresh time interval of the current memory bank to obtain the evaluation information, so as to trigger the refresh inserter to insert the refresh timing sequence of the current memory bank according to the evaluation information during execution of the plurality of read/write commands.

The application provides electronic equipment which executes the memory refresh control method or comprises the memory refresh control circuit.

According to the memory refresh control method, the memory refresh control circuit and the electronic device, the command information of a plurality of read-write commands of the current memory bank is obtained, the current memory bank is any one of a plurality of memory banks, and then the refresh time sequence of the current memory bank during the execution of the plurality of read-write commands is determined according to the command information of the plurality of read-write commands and the refresh time interval of the current memory bank.

The refresh time sequence of the current memory Bank of the single memory Bank is determined according to the read-write command information of the memory banks and the refresh time interval of the current memory Bank, namely, the single memory Bank can be understood to have a set of respective refresh time sequence determination scheme of the current memory Bank. Moreover, because the command information of the read-write command and the refresh time interval of the current memory bank are comprehensively considered, the refresh time sequence of the current memory bank inserted in the process of executing a plurality of read-write commands can not interrupt the execution of the read-write command, and the extra time loss caused by the interruption of the read-write command can be effectively reduced, thereby improving the effective bandwidth of the read-write access of the memory.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the application or the technical solutions of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a memory refresh control method provided by the application.

Fig. 2 is a schematic diagram of a memory refresh control circuit according to the present application.

Fig. 3 is a schematic diagram of a memory controller according to the present application.

Fig. 4 is a schematic structural diagram of an electronic device provided by the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like herein are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or units or modules is not necessarily limited to those steps or units or modules that are expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a flow chart of a memory refresh control method provided by the present application, as shown in fig. 1, the method includes a step 110 and a step 120.

Step 110, obtaining command information of a plurality of read-write commands of a current repository, wherein the current repository is any one of a plurality of repositories;

Step 120, determining a refresh timing sequence of the current memory bank during executing the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

In this embodiment, since the refresh timing of the current Bank of the single Bank is determined according to the read-write command information cached in the located Bank and the refresh time interval of the current Bank, it can be understood that the single Bank has a set of respective refresh timing determination schemes of the current Bank, and the refresh mode of the single Bank is independently performed, that is, the read-write commands of each Bank are separately processed, which is favorable for realizing efficient refresh, and in addition, the refresh timing of the current Bank of each Bank is independently evaluated and determined, so that the hardware logic circuit of the memory refresh control is simple to implement and is favorable for realizing high-speed clock frequency, thereby forming a high-speed logic circuit. Moreover, because the command information of the read-write command and the refresh time interval of the current memory bank are comprehensively considered, the refresh time sequence of the current memory bank inserted in the process of executing a plurality of read-write commands can not interrupt the execution of the read-write command, and the extra time loss caused by the interruption of the read-write command can be effectively reduced, thereby improving the effective bandwidth of the read-write access of the memory.

In particular, the memory needs to be periodically refreshed, recharged to maintain the correctness of the data, for example, the memory may refer to a dynamic random access memory. A bank refers to a repository in memory. One memory may be divided into a plurality of banks for data storage. The application scenario of the memory refresh control method provided by the embodiment of the application is to refresh each memory bank in the memory.

The embodiment of the application performs separate processing on each memory bank in the memory, for example, a corresponding memory refresh control circuit can be independently arranged for each memory bank, so that the memory banks and the memory refresh control circuits are in one-to-one correspondence, and in some examples, a single memory bank can also correspond to a plurality of independent sets of memory refresh control circuits.

The memory refresh control circuit corresponding to each memory Bank can set the time for inserting the refresh command into the read-write command sequence according to circuit logic in combination with command information in the corresponding memory Bank and refresh time interval of the memory, namely, the current memory refresh time sequence of the memory Bank during the execution of a plurality of read-write commands is determined, so that the read-write commands of each Bank can be subjected to channel separation processing based on a mode of refreshing only one Bank at a time, and the time of reading, writing and refreshing is reasonably evaluated by adopting the memory refresh control circuit corresponding to each memory refresh control circuit, so that the reasonable insertion of the refresh command is realized, the problem that the same Bank read-write access operation needs to wait for refresh completion is effectively avoided, and the effective access bandwidth of DDR is improved.

The method provided by the embodiment of the present application will be described below with reference to fig. 2 and 3 by taking a current bank (the current bank is any one of a plurality of banks) as an example.

The read-write command buffer in the memory refresh control circuit can buffer a plurality of read-write commands of the current memory bank to generate a read-write command sequence of the current memory bank. The read-write command sequence arranges the read-write commands according to the execution time sequence. The read-write command is used for reading data in the current memory bank or writing data in the current memory bank.

In addition, command information of the read/write command, such as column address and row address information of the read/write command, is recorded in the read/write command buffer. In some examples, the command information includes a command type (read command or write command) of a read-write command, an execution order (whether continuous), a row address (whether switching of a row address exists), time information, and the like.

The read-write command evaluator/command evaluation module in the memory refresh control circuit can acquire command information of a plurality of read-write commands of the current memory Bank from the read-write command buffer, so that whether the corresponding Bank has idle or not and whether gaps exist between read-write command sequences can be estimated.

A refresh interval, also referred to as a refresh period, refers to an interval of time during which data stored in a memory needs to be periodically refreshed to avoid being lost. In an embodiment of the present application, each memory bank has an independent refresh time interval. Each Bank can be provided with a corresponding refresh timer, can count the refresh time interval of the current Bank, can also receive the instruction of a read-write command evaluator or the reference of gaps (time), evaluates the refresh emergency degree of the current Bank in combination with the refresh time interval of the Bank to form final determined gap information, and can send a refresh command to a refresh inserter according to the gap information, thereby realizing staggered refresh of each Bank, avoiding the read-write operation and refresh operation of each Bank, and solving the problem of reduced effective access bandwidth. In the read/write command, the command information may include time information. The time information refers to information related to execution time of each read-write command in the memory, for example, the time information may include related information such as sending time, finishing time, interval duration, delay duration, and the like of the read-write command.

The read-write command evaluator and/or command evaluation module may determine that a gap time exists between the read-write commands according to time information of the read-write commands on the basis of considering information such as a command type (read command or write command), an execution sequence (whether continuous), a row address (whether switching of the row address exists) of the read-write commands, and the like. The insertion timing of the refresh command, i.e. said current bank refresh timing of the current bank, may also be determined in connection with the refresh time interval.

The above-mentioned current memory bank refresh timing refers to the sending/executing time sequence of the memory refresh command, specifically refers to the timing formed by inserting the refresh command of the current memory bank into the gap time during the execution of several read/write commands. The single memory refresh control circuit, or the read-write command evaluator and/or the refresh timer therein, may determine the refresh timing of the current memory bank during execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank, that is, may insert the refresh command into the gap time between the read-write commands to be executed when the refresh command is sent to the current memory bank.

Because the gap time and the refresh time interval are considered, the refresh command can be accurately inserted into the gap between the read-write commands, so that the refresh command can be executed by utilizing the gap time between the read-write commands, the situation that the refresh command breaks the continuous read-write command sequence is effectively avoided, fewer refresh commands can be inserted at proper time under the condition that the intensive read-write command needs to be executed, the influence of memory refresh on data read-write is reduced, and the effective bandwidth of DDR read-write access is improved.

On the other hand, the read-write commands of all banks are independently processed by the sub-channel sub-circuits, the whole logic circuit is simple to realize, and the design of the high-efficiency refreshing and high-clock logic circuit is facilitated.

It should be noted that each embodiment of the present application may be freely combined, exchanged in order, or separately executed, and does not need to rely on or rely on a fixed execution sequence.

In some embodiments, determining the current bank refresh timing during execution of the read/write commands according to the command information of the read/write commands and the refresh time interval of the current bank in step 120 includes:

According to command information of a plurality of read-write commands and the refreshing time interval of the current memory bank, evaluating the refreshing priority of the memory of the current memory bank to obtain evaluation information; and determining the current memory bank refreshing time sequence during the execution of a plurality of read-write commands according to the evaluation information.

Specifically, the priority of memory refresh refers to the priority of performing memory refresh relative to performing read/write commands.

In some examples, different command sequence types or different command types can be determined according to the command information, and then the cost and the influence degree of the refresh command insertion under the current type are determined according to the different types, so that the priority degree of the memory refresh relative to the execution of the read-write command is evaluated.

The priority of the memory refresh of the current memory bank can be evaluated according to the command information of a plurality of read-write commands and the refresh time interval of the current memory bank, so as to obtain evaluation information. The current bank refresh timing during execution of several read-write commands may be determined based on evaluation information, e.g. the evaluation information may be used to indicate that a memory refresh of the current bank has a high priority or a low priority, etc.

In the memory refresh control method provided in this embodiment, according to command information of a plurality of read-write commands and a refresh time interval of a current bank, the priority of the memory refresh of the current bank is evaluated, and the refresh time sequence of the current bank is determined, so that the interaction between memory refresh and execution of read-write commands can be considered, the proper refresh time sequence of the current bank is determined, and further, the refresh efficiency of the memory is improved.

In some embodiments, the evaluation may be performed in two layers, the first evaluation performs the evaluation of the interaction between the basic memory refresh and the execution of the read-write command, and the second evaluation considers that the refresh command cannot be delayed indefinitely, and in the case that the maximum delay time is about to be reached, the refresh command needs to be executed urgently to ensure that the DDR function is normal.

Namely, the above command information according to the plurality of read-write commands and the refresh time interval of the current memory bank, the evaluating the priority of the memory refresh of the current memory bank to obtain the evaluation information may include:

according to the command information of several read-write commands, making preliminary evaluation on the priority of memory refreshing of current memory bank to obtain preliminary evaluation information, according to the refreshing time interval of current memory bank making regulation on the preliminary evaluation information so as to obtain evaluation information.

Specifically, according to command information of a plurality of read-write commands, information such as whether column address switching, row address switching and the like occur among the plurality of read-write commands can be obtained, and according to the information, preliminary evaluation can be performed on the priority of current bank memory refreshing, so that preliminary evaluation information is obtained.

In addition, the refresh time interval of the current bank needs to be considered. For DDR4 memory, for example, it is typically required to refresh all memory rows every 64 milliseconds. The protocol specification of DDR memory requires refresh commands to be sent in a certain period. Some time transmission may be delayed or advanced, but the total number cannot be changed. The delay cannot be delayed infinitely, and when the maximum delay time is up, the refresh command is sent out anyway, so that the DDR function is ensured to be normal.

Therefore, the preliminary evaluation information needs to be adjusted according to the refresh time interval of the current memory bank to obtain the final evaluation information.

According to the memory refresh control method provided by the embodiment of the application, a two-stage evaluation method is set, the multi-dimensional self-adaptive adjustment of the current memory bank is realized by combining the command information and the refresh time interval, and particularly, the preliminary evaluation information is readjusted according to the refresh time interval of the current memory bank, so that the normal operation of the memory is ensured, and the refresh efficiency of the memory is improved.

In some embodiments, the process of performing preliminary evaluation on the priority of the current bank memory refresh according to the command information of the plurality of read-write commands to obtain preliminary evaluation information includes at least one of the following:

When the command information indicates a read-write command comprising row address switching and/or a read-write command comprising read-write switching in a plurality of read-write commands, the preliminary evaluation information indicates a high priority of memory refreshing of the current memory bank;

when the command information indicates that a plurality of read-write commands comprise read-write commands with unchanged row addresses, the preliminary evaluation information indicates that the memory of the current memory bank is refreshed with low priority;

When the command information indicates that the current memory bank does not have a read-write command, the preliminary evaluation information indicates that memory refresh of the current memory bank has no timing restriction.

Specifically, the row address refers to a row address of a memory address accessed by a read/write command, and the column address information refers to a column address of a memory address accessed by a read/write command. The row address is an identifier used to select a row in the memory array. The row address determines which row of memory cells is activated and accessed. A column address is an identifier used to select a certain column position in a particular row. The column address determines which particular data bit or memory cell is to be read or written in the activated row.

Whether the row address or column address is hit or there is a switch determines whether to precharge or reactivate the memory, affecting the memory refresh.

The preliminary evaluation information may be determined according to the following three cases.

In the first case, the command information of the plurality of read-write commands indicates that the plurality of read-write commands comprise read-write commands with row address switching and/or read-write commands with read-write switching, then preliminary evaluation is performed on the priority of memory refreshing of the current memory bank, the preliminary evaluation information indicates that the memory refreshing of the current memory bank has high priority, and the preliminary evaluation information indicates that a gap time exists between the plurality of read-write commands, so that the memory refreshing can be performed.

This is because the refresh operation is usually performed in rows, the time gap between read and write commands for switching row addresses is long, and the time gap between read and write commands for switching read and write is also long, so that a proper time gap can be selected to insert the refresh operation, thereby avoiding data loss and minimizing performance impact.

And secondly, the command information indicates that the read-write commands with unchanged row addresses are included in the plurality of read-write commands, the priority of the memory refreshing of the current memory bank is primarily evaluated, the primary evaluation information indicates that the memory refreshing of the current memory bank has low priority, and the fact that no gap time exists between the plurality of read-write commands is indicated, and the memory refreshing cannot be performed.

This is because the refresh operation is typically performed on a row-by-row basis, the time gap between read and write commands with column address switching (where the row address is unchanged) is very short, and inserting a refresh command interrupts current access, resulting in performance loss.

And thirdly, the command information indicates that the current memory bank does not have a read-write command, the priority of the memory refreshing of the current memory bank is primarily evaluated, and the primary evaluation information indicates that the memory refreshing of the current memory bank of the memory of the current memory bank has no time sequence limitation.

The method is characterized in that the current memory bank is in an idle state, the current memory operation is not disturbed by refreshing, the memory performance is not influenced, and the memory can be refreshed at any time.

According to the memory refreshing control method provided by the embodiment of the application, the priority of the memory refreshing of the current memory bank is initially evaluated according to the command information of a plurality of read-write commands, so that the interaction between the read-write commands and the memory refreshing is fully considered, and the memory refreshing efficiency is improved.

In some embodiments, the adjusting the preliminary evaluation information according to the refresh time interval of the current memory bank to obtain the evaluation information includes:

When the refresh time interval of the current bank approaches the time interval threshold, the evaluation information is adjusted to the highest priority by the preliminary evaluation information.

Specifically, the memory refresh needs to be performed in a certain period. The refresh time interval may be represented by a count by a time interval counter. A refresh command may be generated based on the refresh time interval of the current bank. Some time transmission may be deferred or some time transmission may be advanced.

The time interval threshold is the time that the refresh command is allowed to defer. If the refresh time interval of the current memory bank is close to the time interval threshold value, a refresh command must be sent out at the moment, and the evaluation information can be adjusted to the highest priority from the preliminary evaluation information at the moment, so that the function of refreshing the basic interval is ensured to be satisfied. And then inserting the refresh command into a plurality of read-write commands according to the gap time, and sending the refresh command.

It should be noted that, the above-mentioned approaching time interval threshold refers to that the refresh time of the current bank is about to reach the time interval threshold, and the judgment criterion may be that the difference between the time interval threshold and the refresh time interval is smaller than a preset value, or a certain critical value before the refresh time interval reaches the time interval threshold.

Correspondingly, if the refresh time interval of the current bank is not close to the time interval threshold, the priority may not be adjusted and may directly participate in the insertion of the refresh command as final evaluation information.

According to the memory refresh control method provided by the embodiment of the application, when the refresh time interval of the current memory bank is close to the time interval threshold, the evaluation information is adjusted to the highest priority level by the preliminary evaluation information, so that the priority level of the refresh command is improved, and the security of data is guaranteed.

In some embodiments, determining the current bank refresh timing during execution of a number of read and write commands includes:

And in response to the evaluation information, inserting a refresh command into a read-write command stream of the current memory bank to form a refresh time sequence of the current memory bank, wherein the read-write command stream consists of a plurality of read-write commands according to the time sequence.

In particular, in response to different evaluation information, a priority of refresh commands relative to read and write commands may be determined, such that refresh commands are inserted in a gap time during read and write command stream execution of a current bank to constitute the current bank refresh timing. The read-write command stream here consists of several read-write commands according to the time sequence.

In some embodiments, after determining the current bank refresh timing during execution of the read-write commands according to command information of the read-write commands and a refresh time interval of the current bank, further comprising:

And carrying out command arbitration on the current memory bank refreshing time sequence during the execution of a plurality of read-write commands.

Specifically, according to the memory access condition (such as read-write conflict, system load, etc.), the refresh command is scheduled, and the refresh command needs to be inserted at a proper time, so as to ensure that the data of the memory is refreshed at a correct time, and avoid data loss. Thus, command arbitration is required for the current bank refresh timing during execution of several read and write commands.

In particular, the cooperation between the memory bank command arbiter and the refresh inserter is very important for optimizing memory access and ensuring data integrity. The arbiter is responsible for scheduling the refresh command according to the memory access condition (such as read-write conflict, system load, etc.), and the refresh inserter inserts the refresh command at a proper time to ensure that the data of the memory is refreshed at a correct time, thereby avoiding the data loss. The cooperation of the two can ensure that the memory system meets the refresh cycle requirement and simultaneously reduces the influence on the memory access performance as much as possible.

In some embodiments, the method further comprises:

Determining a refresh time interval for the current bank based on the refresh time counter for the current bank;

Wherein the refresh time counters of the respective banks have different count start times.

Specifically, the refresh time interval of the current memory bank and the rest memory banks can be adjusted, the refresh operation of each memory bank is staggered, and the effective bandwidth of the whole memory read-write access can be improved.

The refresh time interval of the current bank may be determined by a refresh time counter. The count start times of the refresh time counters of the respective banks may be differently set so that the count start times are all different, and thus the refresh time intervals of the respective banks are also different in the same refresh period.

The apparatus provided by the embodiments of the present application will be described below, and the apparatus described below and the method described above may be referred to correspondingly.

Fig. 2 is a schematic diagram of a memory refresh control circuit according to the present application, and as shown in fig. 2, a memory refresh control circuit 200 includes a read/write command buffer 210, a command evaluation module 201, and a refresh inserter 230.

A read-write command buffer 210 for buffering a number of read-write commands in a current bank, which is any one of the plurality of banks, and command information of the read-write commands;

The command evaluation module 201 is configured to clock a refresh time interval of a current bank, and trigger the refresh inserter 230 to determine a refresh timing of the current bank during execution of the read/write commands according to command information of the read/write commands and the refresh time interval of the current bank.

The memory refresh control circuit provided by the embodiment of the application realizes the memory refresh function by adopting a mode that a single memory bank independently refreshes, is beneficial to realizing higher clock frequency in the memory, improves the refresh efficiency of the memory, and can effectively reduce extra time loss caused by the interruption of the read-write command due to comprehensively considering the command information of the read-write command and the refresh time interval of the current memory bank, so that the memory refresh is performed during the execution of a plurality of read-write commands without interrupting the execution of the read-write command, thereby improving the effective bandwidth of the read-write access of the memory.

In some embodiments, command evaluation module 201 includes a refresh timer 220 and a read-write command evaluator 240;

The read-write command evaluator 240 is configured to perform preliminary evaluation on the priority of the current bank memory refresh according to command information of a plurality of read-write commands, so as to obtain preliminary evaluation information;

The refresh timer 220 is further configured to adjust the preliminary evaluation information according to a refresh time interval of the current memory bank, so as to obtain evaluation information, and trigger the refresh inserter 230 to determine a refresh timing of the current memory bank during execution of a plurality of read/write commands according to the evaluation information.

Fig. 3 is a schematic diagram of a memory controller according to the present application, and as shown in fig. 3, a memory controller 300 includes a memory refresh control circuit 200 and a memory bank command arbiter 320, which can implement management of a memory bank 310.

Memory refresh control circuit 200 is in one-to-one correspondence with memory bank 310.

In the memory controller 300 provided by the embodiment of the application, the memory refresh control circuit 200 corresponds to the memory banks one by one, a single memory bank refresh mode is adopted to realize the memory refresh function, read-write commands of each memory bank are separately processed, higher clock frequency is facilitated to be realized in the realization of a memory chip, and meanwhile, the logic circuit of the memory refresh control circuit is simplified.

In some embodiments, a bank command arbiter is coupled to the refresh inserters in the respective memory refresh control circuits for arbitrating read and write commands and refresh commands sent by the refresh inserters.

In particular, the cooperation between the memory bank command arbiter and the refresh inserter is very important for optimizing memory access and ensuring data integrity. The arbiter is responsible for scheduling a refresh command according to the condition of memory access (such as read-write collision, system load and the like), and the refresh inserter inserts the refresh command at a proper time to form a current memory bank refresh time sequence so as to ensure that the data of the memory is refreshed at the correct time and avoid data loss. The cooperation of the two can ensure that the memory system meets the refresh cycle requirement and simultaneously reduces the influence on the memory access performance as much as possible.

In some embodiments, the memory is a double rate synchronous dynamic random access memory.

In particular, double rate synchronous dynamic random access memory is a type of memory that is widely used in computers, servers and other electronic devices. It is a modified version of the synchronous dynamic random access memory that increases the data transfer rate by transferring two times per clock cycle.

Fig. 4 is a schematic structural diagram of an electronic device provided in the present application, as shown in fig. 4, the electronic device may include a Processor (Processor) 410, a communication interface (Communications Interface) 420, a Memory (Memory) 430, and a communication bus (Communications Bus) 440, where the Processor 410, the communication interface 420, and the Memory 430 complete communication with each other through the communication bus 440. The processor 410 may invoke logic commands in the memory 430 to perform the methods described in the above embodiments, such as:

and determining the refresh time sequence of the current memory bank during executing the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

In addition, the logic commands in the memory described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in the form of a software product stored in a storage medium, comprising several commands for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.

The processor in the electronic device provided by the embodiment of the application can call the logic instruction in the memory to realize the method, and the specific implementation mode is consistent with the implementation mode of the method, and the same beneficial effects can be achieved, and the detailed description is omitted here.

It should be noted that, the electronic device may be implemented by a hardware method, so that the electronic device performs the memory refresh control method, or the electronic device may include the memory refresh control circuit.

The specific embodiment is consistent with the foregoing method embodiment, and the same beneficial effects can be achieved, and will not be described herein.

The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.

It should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present application, and not for limiting the same, and although the present application has been described in detail with reference to the above-mentioned embodiments, it should be understood by those skilled in the art that the technical solution described in the above-mentioned embodiments may be modified or some technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiments of the present application.

Claims (10)

1. A memory refresh control method, wherein the memory comprises a plurality of banks, the method comprising:

Obtaining command information of a plurality of read-write commands of a current repository, wherein the current repository is any one of a plurality of the repositories;

and determining the refresh time sequence of the current memory bank during the execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

2. The memory refresh control method of claim 1, wherein determining the current bank refresh timing during execution of the read-write commands based on command information of the read-write commands and a refresh time interval of the current bank comprises:

According to the command information of the read-write commands and the refreshing time interval of the current memory bank, evaluating the refreshing priority of the memory of the current memory bank to obtain evaluation information;

And determining the current memory bank refreshing time sequence during the execution of a plurality of read-write commands according to the evaluation information.

3. The memory refresh control method according to claim 2, wherein the evaluating the priority of the memory refresh of the current bank according to the command information of the plurality of read-write commands and the refresh time interval of the current bank, to obtain the evaluation information, includes:

According to command information of a plurality of read-write commands, primarily evaluating the priority of memory refreshing of the current memory bank to obtain primarily evaluated information;

And adjusting the preliminary evaluation information according to the refreshing time interval of the current memory bank to obtain the evaluation information.

4. The memory refresh control method of claim 3, wherein the preliminary evaluation of the priority of the current memory bank memory refresh is performed according to command information of the plurality of read-write commands, to obtain preliminary evaluation information, including at least one of:

when the command information indicates that a plurality of read-write commands comprise read-write commands with row address switching and/or read-write commands with read-write switching, the preliminary evaluation information indicates that the memory of the current memory bank is refreshed with high priority;

When the command information indicates that a plurality of read-write commands with unchanged row addresses are included in the read-write commands, the preliminary evaluation information indicates that the memory of the current memory bank is refreshed with low priority;

When the command information indicates that the read-write command does not exist in the current memory bank, the preliminary evaluation information indicates that memory refresh of the current memory bank has no timing restriction.

5. The memory refresh control method of claim 3, wherein the adjusting the preliminary evaluation information according to the refresh time interval of the current bank to obtain the evaluation information includes:

The evaluation information is adjusted to a highest priority by the preliminary evaluation information when the refresh time interval of the current bank approaches a time interval threshold.

6. The memory refresh control method of claim 2, wherein determining the current memory bank refresh timing during execution of the plurality of read-write commands based on the evaluation information comprises:

And in response to the evaluation information, inserting a refresh command into a read-write command stream of the current memory bank to form the current memory bank refresh time sequence, wherein the read-write command stream consists of a plurality of read-write commands according to time sequences.

7. The memory refresh control method according to any one of claims 1 to 6, wherein after determining the current bank refresh timing during execution of the plurality of read-write commands based on command information of the plurality of read-write commands and a refresh time interval of the current bank, further comprising:

And carrying out command arbitration on the current memory bank refreshing time sequence during the execution of a plurality of read-write commands.

8. A memory refresh control circuit is characterized by comprising a read-write command buffer and a command evaluation module, wherein,

The read-write command buffer is used for buffering a plurality of read-write commands in a current memory bank and command information of the read-write commands, and the current memory bank is any one of a plurality of memory banks;

The command evaluation module is used for timing the refresh time interval of the current memory bank, and triggering the refresh inserter to insert the refresh time sequence of the current memory bank during the execution of the read-write commands according to the command information of the read-write commands and the refresh time interval of the current memory bank.

9. The memory refresh control circuit of claim 8, wherein the command evaluation module comprises a refresh timer and a read-write command evaluator;

The read-write command evaluator is used for primarily evaluating the priority of the memory refreshing of the current memory bank according to command information of a plurality of read-write commands to obtain primary evaluation information;

The refresh timer is further configured to adjust the preliminary evaluation information according to a refresh time interval of the current memory bank to obtain the evaluation information, so as to trigger the refresh inserter to insert the refresh timing sequence of the current memory bank according to the evaluation information during execution of the plurality of read/write commands.

10. An electronic device, characterized in that the electronic device performs the memory refresh control method according to any one of claims 1 to 7, or the electronic device comprises the memory refresh control circuit according to claim 8 or 9.