CN121237773A - Semiconductor structure and its formation method - Google Patents
Semiconductor structure and its formation methodInfo
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- CN121237773A CN121237773A CN202410867282.9A CN202410867282A CN121237773A CN 121237773 A CN121237773 A CN 121237773A CN 202410867282 A CN202410867282 A CN 202410867282A CN 121237773 A CN121237773 A CN 121237773A
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Abstract
一种半导体结构及其形成方法，其中形成方法包括：提供基底，基底包括电容区和非电容区；在电容区上形成电容结构；在基底形成的第一介质层；在第一介质层内形成第一电互连结构。通过在第一介质层内形成第一电互连结构和电容结构，使得电容区和非电容区之间的器件结构密度和高度趋于一致，能够保证后续形成的第二介质层的顶部表面具有较好的平坦度，能够减少第二介质层的顶部表面的金属材料残留，有效降低后续形成的第二电互连结构发生短接漏电的问题。第一电互连结构和电容结构形成在同一工艺层，能够减少半导体结构堆叠的层数，以此减少半导体结构中产生的寄生电容，降低RC延迟。
A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate comprising a capacitive region and a non-capacitive region; forming a capacitive structure on the capacitive region; forming a first dielectric layer on the substrate; and forming a first electrical interconnect structure within the first dielectric layer. By forming the first electrical interconnect structure and the capacitive structure within the first dielectric layer, the device structure density and height between the capacitive and non-capacitive regions tend to be consistent. This ensures that the top surface of the subsequently formed second dielectric layer has good flatness, reduces residual metal material on the top surface of the second dielectric layer, and effectively reduces the problem of short-circuit leakage in the subsequently formed second electrical interconnect structure. The first electrical interconnect structure and the capacitive structure are formed on the same process layer, which reduces the number of stacked layers in the semiconductor structure, thereby reducing parasitic capacitance generated in the semiconductor structure and lowering RC delay.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Capacitors are passive components commonly used in very large scale integrated circuits. The capacitor mainly includes a polysilicon-Insulator-polysilicon (PIP, polysilicon-Insulator-Polysilicon) capacitor, a Metal-Insulator-Silicon (MIS) capacitor, a Metal-Insulator-Metal (MIM) capacitor, and the like.
With the rapid development of wireless communication technology, it is strongly desired to implant high performance decoupling and bypass capacitors suitable for system on a chip (SoC) into copper interconnect termination processes of integrated circuits to obtain powerful radio frequency systems. This further requires that the implanted capacitor should have high capacitance density, ideal voltage linearity, accurate capacitance control, high reliability, etc., and conventional PIP, MIS and MOS structures have been difficult to meet performance requirements.
Since MIM capacitors have low interference with transistors and can provide good Linearity and Symmetry, the use of MIM capacitors will be a trend in radio frequency and analog/mixed signal integrated circuits.
However, the prior art still has problems in forming MIM capacitors.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, and improves the performance of a device structure.
In order to solve the problems, the invention provides a semiconductor structure, which comprises a substrate, a capacitor structure, a first dielectric layer, a first electrical interconnection structure and a second electrical interconnection structure, wherein the substrate comprises a capacitor region and a non-capacitor region, the capacitor structure is arranged on the capacitor region and comprises a lower electrode plate layer, an insulating layer arranged on the lower electrode plate layer and an upper electrode plate layer arranged on the insulating layer, the first dielectric layer is arranged on the substrate and covers the capacitor structure, the first electrical interconnection structure is arranged in the first dielectric layer and is arranged on the non-capacitor region.
Optionally, the semiconductor device further comprises a second dielectric layer positioned on the first dielectric layer and a second electric interconnection structure positioned in the first dielectric layer and the second dielectric layer, wherein the second electric interconnection structure is electrically connected with the first electric interconnection structure and the capacitor structure respectively.
Optionally, the lower pole plate layer is a composite laminate.
Optionally, the lower electrode plate layer comprises a first sub-electrode plate layer, a second sub-electrode plate layer positioned on the first sub-electrode plate layer and a third sub-electrode plate layer positioned on the second sub-electrode plate layer.
Optionally, the material of the second sub-electrode plate layer comprises aluminum, and the material of the first sub-electrode plate layer and the material of the third sub-electrode plate layer comprise titanium nitride.
Optionally, the material of the upper electrode plate layer comprises titanium nitride.
Optionally, the first electrical interconnection structure comprises a first conductive plug and a first conductive layer positioned on the first conductive plug and electrically connected with the first conductive plug.
Optionally, the second electrical interconnection structure comprises a second conductive plug in the second dielectric layer, wherein the second conductive plug is electrically connected with the first conductive layer, a third conductive plug in the first dielectric layer and the second dielectric layer, the third conductive plug is electrically connected with the lower polar plate layer, and a fourth conductive plug in the first dielectric layer and the second dielectric layer, and the fourth conductive plug is electrically connected with the upper polar plate layer.
Optionally, the material of the first electrical interconnect structure comprises copper.
Optionally, the material of the second electrical interconnect structure comprises copper.
Optionally, the material of the first dielectric layer comprises silicon oxide.
Optionally, the material of the second dielectric layer comprises silicon oxide.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a capacitor structure on the capacitor region, forming a first dielectric layer formed on the substrate, wherein the first dielectric layer covers the capacitor structure, forming a first electric interconnection structure in the first dielectric layer, and the first electric interconnection structure is positioned on the non-capacitor region, wherein the capacitor structure comprises a lower electrode plate layer, an insulating layer positioned on the lower electrode plate layer and an upper electrode plate layer positioned on the insulating layer.
Optionally, after the first electrical interconnection structure is formed, a second dielectric layer is formed on the first dielectric layer, and a second electrical interconnection structure is formed in the first dielectric layer and the second dielectric layer, wherein the second electrical interconnection structure is electrically connected with the first electrical interconnection structure and the capacitor structure respectively.
Optionally, the forming method of the capacitor structure comprises the steps of forming a lower electrode plate material layer on the substrate, forming an insulating material layer on the lower electrode plate material layer, forming an upper electrode plate material layer on the insulating material layer, and carrying out patterned etching treatment on the upper electrode plate material layer, the insulating material layer and the lower electrode plate material layer to form an upper electrode plate layer, an insulating layer and a lower electrode plate layer, wherein the capacitor structure is formed by the upper electrode plate layer, the insulating layer and the lower electrode plate layer.
Optionally, the method for carrying out patterned etching treatment on the upper electrode plate material layer, the insulating material layer and the lower electrode plate material layer comprises the steps of adopting a first etching process to etch the upper electrode plate material layer and part of the insulating material layer to form the upper electrode plate layer, depositing a first anti-reflection layer, wherein the first anti-reflection layer covers the exposed surface of the upper electrode plate layer and the surface of the insulating material layer, and adopting a second etching process to etch the first anti-reflection layer, the rest part of the insulating material layer and the lower electrode plate material layer to form the insulating layer and the lower electrode plate layer.
Optionally, the lower pole plate layer is a composite laminate.
Optionally, the lower electrode plate layer comprises a first sub-electrode plate layer, a second sub-electrode plate layer positioned on the first sub-electrode plate layer and a third sub-electrode plate layer positioned on the second sub-electrode plate layer.
Optionally, the first electrical interconnection structure comprises a first conductive plug and a first conductive layer positioned on the first conductive plug and electrically connected with the first conductive plug.
Optionally, the method for forming the first electric interconnection structure comprises the steps of forming a first conductive through hole and a first conductive groove in the first dielectric layer by adopting a Damascus process, wherein the first conductive groove exposes the first conductive through hole, forming a first conductive material layer in the first conductive through hole, in the first conductive groove and on the first dielectric layer, carrying out planarization treatment on the first conductive material layer until the top surface of the first dielectric layer is exposed, forming a first conductive plug in the first conductive through hole, and forming the first conductive layer in the first conductive groove.
Optionally, the second electrical interconnection structure comprises a second conductive plug in the second dielectric layer, wherein the second conductive plug is electrically connected with the first conductive layer, a third conductive plug in the first dielectric layer and the second dielectric layer, the third conductive plug is electrically connected with the lower polar plate layer, and a fourth conductive plug in the first dielectric layer and the second dielectric layer, and the fourth conductive plug is electrically connected with the upper polar plate layer.
Optionally, the forming method of the second electric interconnection structure comprises the steps of forming a second conductive through hole in the second dielectric layer, wherein the second conductive through hole exposes the surface of the first conductive layer, forming a third conductive through hole in the first dielectric layer and the second dielectric layer, wherein the third conductive through hole exposes the surface of the lower electrode plate layer, forming a fourth conductive through hole in the first dielectric layer and the second dielectric layer, wherein the fourth conductive through hole exposes the surface of the upper electrode plate layer, forming a second conductive material layer in the second conductive through hole, in the third conductive through hole, in the fourth conductive through hole and on the second dielectric layer, flattening the second conductive material layer until the top surface of the second dielectric layer is exposed, and forming the second conductive plug in the second conductive through hole, the third conductive plug in the third conductive through hole and the fourth conductive plug in the fourth conductive through hole.
Compared with the prior art, the technical scheme of the invention has the following advantages:
In the semiconductor structure of the technical scheme of the invention, the first electric interconnection structure and the capacitor structure are simultaneously positioned in the first dielectric layer, so that the density and the height of the device structure between the capacitor region and the non-capacitor region in the first dielectric layer tend to be consistent, therefore, the top surface of the second dielectric layer can be ensured to have better flatness when the second dielectric layer is formed later, and the metal material residue on the top surface of the second dielectric layer can be reduced when the second electric interconnection structure is formed later, thereby effectively reducing the problem of short circuit and electric leakage of the second electric interconnection structure and improving the performance of the semiconductor structure. In addition, by forming the first electric interconnection structure and the capacitor structure in the same process layer, the number of layers of the semiconductor structure stack can be reduced, so that parasitic capacitance generated in the semiconductor structure is reduced, RC delay is reduced, and performance of the semiconductor structure is improved.
According to the method for forming the semiconductor structure, the first electric interconnection structure and the capacitor structure are formed in the first dielectric layer, so that the density and the height of the device structure between the capacitor region and the non-capacitor region in the first dielectric layer tend to be consistent, the top surface of the second dielectric layer can be guaranteed to have better flatness when the second dielectric layer is formed later, and the metal material residue on the top surface of the second dielectric layer can be reduced when the second electric interconnection structure is formed later, so that the problem of short circuit and electric leakage of the second electric interconnection structure can be effectively reduced, and the performance of the semiconductor structure is improved. In addition, by forming the first electric interconnection structure and the capacitor structure in the same process layer, the number of layers of the semiconductor structure stack can be reduced, so that parasitic capacitance generated in the semiconductor structure is reduced, RC delay is reduced, and performance of the semiconductor structure is improved.
Further, the method for carrying out patterned etching treatment on the upper electrode plate material layer, the insulating material layer and the lower electrode plate material layer comprises the steps of adopting a first etching process to etch the upper electrode plate material layer and part of the insulating material layer to form the upper electrode plate layer, depositing a first anti-reflection layer, wherein the first anti-reflection layer covers the exposed surface of the upper electrode plate layer and the surface of the insulating material layer, and adopting a second etching process to etch the first anti-reflection layer, the rest part of the insulating material layer and the lower electrode plate material layer to form the insulating layer and the lower electrode plate layer. And in the first etching process, partial insulating material layer is reserved, so that plasma in the first etching process is prevented from directly contacting with the lower polar plate layer with metal attribute, the problem of point discharge between the plasma and the lower polar plate layer is reduced, and the damage of the whole wafer is further caused.
Drawings
FIGS. 1-2 are schematic diagrams illustrating steps of a method for forming a semiconductor structure;
Fig. 3 to 10 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, the prior art semiconductor structure still has many problems during the test process. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, wherein the substrate 100 includes a capacitor region I and a non-capacitor region II, a first dielectric layer 101 is formed on the substrate 100, a first electrical interconnection structure 102 is formed on the first dielectric layer 101, the first electrical interconnection structure 102 is located on the non-capacitor region II, a capacitor structure 103 is formed on the first dielectric layer 101, the capacitor structure 103 is located on the capacitor region I, and the capacitor structure 103 includes a lower plate layer, an insulating layer located on the lower plate layer, and an upper plate layer (not labeled) located on the insulating layer.
Referring to fig. 2, a second dielectric layer 104 is formed on the first dielectric layer 101, the second dielectric layer 104 covers the capacitor structure 103, and a second electrical interconnection structure 105 is formed in the second dielectric layer 104, and the second electrical interconnection structure 105 is electrically connected to the first electrical interconnection structure 102 and the capacitor structure 103, respectively.
In this embodiment, before the second dielectric layer 104 is deposited, the capacitor structure 103 is formed on the capacitor region I and no device structure is formed on the non-capacitor region II in the first dielectric layer 101, so that there is a problem of device density difference and height difference between the two regions, and therefore the formed second dielectric layer 104 cannot have its top surface polished flat by planarization treatment, so that there is a problem of flatness on the top surface of the second dielectric layer 104.
With continued reference to fig. 2, in this embodiment, the second electrical interconnection structure 105 is a plurality of conductive plugs (not labeled) electrically connecting the first electrical interconnection structure 102, the lower electrode plate layer of the capacitor structure 103, and the upper electrode plate layer, and in the process of forming each conductive plug, since the top surface of the second dielectric layer 104 has a flatness problem, residues of metal materials may occur in the chemical mechanical polishing process of each conductive plug, so that short-circuit leakage between the conductive plugs (as in a portion a in fig. 2) is easily caused, thereby affecting the performance of the device structure.
On the basis, the invention provides the semiconductor structure and the forming method thereof, and the first electric interconnection structure and the capacitor structure are formed in the first dielectric layer, so that the density and the height of the device structure between the capacitor region and the non-capacitor region in the first dielectric layer tend to be consistent, and therefore, when the second dielectric layer is formed subsequently, the top surface of the second dielectric layer can be ensured to have better flatness, and when the second electric interconnection structure is formed subsequently, the metal material residue on the top surface of the second dielectric layer can be reduced, and further, the problem that short circuit and leakage occur in the second electric interconnection structure can be effectively reduced, and the performance of the semiconductor structure is improved. In addition, by forming the first electric interconnection structure and the capacitor structure in the same process layer, the number of layers of the semiconductor structure stack can be reduced, so that parasitic capacitance generated in the semiconductor structure is reduced, RC delay is reduced, and performance of the semiconductor structure is improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 10 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided, and the substrate 200 includes a capacitive region I and a non-capacitive region II.
In this embodiment, the base 200 includes a substrate and a device layer on the substrate, where a plurality of device structures (not shown) are located in the device layer.
In this embodiment, the substrate is made of silicon, and in other embodiments, the substrate may be made of germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, the device structure includes one or more of a transistor structure, a capacitor structure, a resistor structure, and an inductor structure.
It should be noted that, in the subsequent process, a capacitor structure is formed on the capacitor region I, and a capacitor structure is not formed on the non-capacitor region II.
After providing the substrate 200, further comprising forming a capacitive structure on the capacitive region I, the capacitive structure comprising a lower pole plate layer, an insulating layer on the lower pole plate layer, and an upper pole plate layer on the insulating layer. For specific processes, please refer to fig. 4 to fig. 5.
Referring to fig. 4, a lower plate material layer 201 is formed on the substrate 200, an insulating material layer 202 is formed on the lower plate material layer 201, and an upper plate material layer 203 is formed on the insulating material layer 202.
In this embodiment, the lower pole plate layer is a composite laminate. The corresponding lower plate material layer 201 includes a first sub-plate material layer 2011, a second sub-plate material layer 2012 disposed on the first sub-plate material layer 2011, and a third sub-plate material layer 2013 disposed on the second sub-plate material layer 2012.
In other embodiments, the lower pole plate layer may also be a single layer structure.
In this embodiment, the material of the first sub-plate material layer 2011 is titanium nitride, the material of the second sub-plate material layer 2012 is aluminum, and the material of the third sub-plate material layer 2013 is titanium nitride.
In this embodiment, the insulating material layer 202 is made of silicon nitride.
In this embodiment, the material of the upper plate material layer 203 is titanium nitride.
With continued reference to fig. 4, in this embodiment, a second anti-reflection layer 204 is further formed on the upper electrode plate material layer 203. By adding the second anti-reflection layer 204, a clearer and more accurate exposure profile can be obtained in the process of forming the capacitor structure through the subsequent patterned etching treatment.
In this embodiment, the material of the second anti-reflection layer 204 is silicon oxynitride.
With continued reference to fig. 4, in this embodiment, before forming the bottom plate material layer 201, a first etching stopper layer 205 is further formed on the substrate 200.
In this embodiment, the material of the first etching stopper layer 205 is silicon nitride.
After the lower electrode plate material layer 201, the insulating material layer 202 and the upper electrode plate material layer 203 are formed, the method further comprises the step of performing patterned etching treatment on the upper electrode plate material layer 203, the insulating material layer 202 and the lower electrode plate material layer 201 to form the upper electrode plate layer, the insulating layer and the lower electrode plate layer, and the capacitor structure is formed by the upper electrode plate layer, the insulating layer and the lower electrode plate layer. For specific procedures, please refer to fig. 5 to fig. 6.
Referring to fig. 5, the upper plate material layer 203 and a portion of the insulating material layer 202 are etched by a first etching process to form the upper plate layer 206.
In this embodiment, the first etching process is a dry etching process.
By retaining a portion of the insulating material layer 202 in the first etching process, the plasma in the first etching process is prevented from directly contacting the lower plate layer with metal properties, so that the problem of tip discharge between the plasma and the lower plate layer is reduced, and the damage of the whole wafer is further caused.
Referring to fig. 6, a first anti-reflection layer 207 is deposited, the first anti-reflection layer 207 covers the exposed surface of the upper electrode plate layer 206 and the surface of the insulating material layer 202, and a second etching process is used to etch the first anti-reflection layer 207, the rest of the insulating material layer 202 and the lower electrode plate layer 201, so as to form the insulating layer 208 and the lower electrode plate layer 209.
By adding the first anti-reflection layer 207, a clearer and more accurate exposure profile can be obtained in the process of forming the capacitor structure through a patterning etching process.
In this embodiment, the material of the first anti-reflection layer 207 is silicon oxynitride.
It should be noted that, in this embodiment, the projection area of the upper electrode layer 206 toward the substrate 200 is located within the projection area of the lower electrode layer 209 toward the substrate 200, and the area of the lower electrode layer 209 larger than the upper electrode layer 206 is used for subsequent metal connection, so that shorting with the metal connection of the lower electrode layer 209 and the upper electrode layer 206 is avoided.
In this embodiment, the bottom plate layer 209 includes a first sub-plate layer 2091, a second sub-plate layer 2092 on the first sub-plate layer 2091, and a third sub-plate layer 2093 on the second sub-plate layer 2092.
In this embodiment, the second etching process is a dry etching process.
Referring to fig. 7, a first dielectric layer 210 is formed on the substrate 200, where the first dielectric layer 210 covers the capacitor structure.
In this embodiment, the material of the first dielectric layer 210 is silicon oxide.
With continued reference to fig. 7, in this embodiment, before forming the first dielectric layer 210, forming a second etch stop layer 215 on the exposed surface of the capacitor structure and the exposed surface of the first etch stop layer 205 is further included.
In this embodiment, the material of the second etching stop layer 215 is silicon nitride.
Referring to fig. 8, a first electrical interconnection structure 211 is formed in the first dielectric layer 210, and the first electrical interconnection structure 211 is located on the non-capacitive region II.
In this embodiment, the first electrical interconnect structure 211 includes a first conductive plug 2111 and a first conductive layer 2112 on the first conductive plug 2111 and electrically connected to the first conductive plug 2111.
In this embodiment, the method for forming the first electrical interconnection structure 211 includes forming a first conductive via and the first conductive trench (not labeled) in the first dielectric layer 210 by using a damascene process, forming a first conductive material layer (not shown) in the first conductive via, in the first conductive trench and on the first dielectric layer 210, planarizing the first conductive material layer until a top surface of the first dielectric layer 210 is exposed, forming the first conductive plug 2111 in the first conductive via, and forming the first conductive layer 2112 in the first conductive trench.
In this embodiment, the first electrical interconnect structure 211 is electrically connected to the device structures in the device layer. Specifically, the first conductive via penetrates the first etch stop layer 205 and the second etch stop layer 215 to expose the device structure in the device layer, and the first conductive plug 2111 is electrically connected to the device structure in the device layer.
In this embodiment, the material of the first electrical interconnection structure 211 is copper.
In this embodiment, a chemical mechanical polishing process is used for the planarization process of the first conductive material layer.
Referring to fig. 9, a second dielectric layer 212 is formed on the first dielectric layer 210.
In this embodiment, the second dielectric layer 212 is made of silicon oxide.
With continued reference to fig. 9, in this embodiment, before forming the second dielectric layer 212, a third etching stop layer 213 is further formed on the first dielectric layer 210.
In this embodiment, the material of the third etching stop layer 213 is silicon nitride.
Referring to fig. 10, a second electrical interconnection structure 214 is formed in the first dielectric layer 210 and the second dielectric layer 212, and the second electrical interconnection structure 214 is electrically connected to the first electrical interconnection structure 211 and the capacitor structure, respectively.
By forming the first electrical interconnection structure 211 and the capacitor structure in the first dielectric layer 210, the density and the height of the device structure between the capacitor region I and the non-capacitor region II in the first dielectric layer 210 tend to be consistent, so that when the second dielectric layer 212 is formed, the top surface of the second dielectric layer 212 can be ensured to have better flatness, and when the second electrical interconnection structure 214 is formed, the metal material residue on the top surface of the second dielectric layer 212 can be reduced, so that the problem of short circuit and leakage of the second electrical interconnection structure 214 can be effectively reduced, and the performance of the semiconductor structure is improved. In addition, by forming the first electrical interconnection structure 211 and the capacitor structure in the same process layer, the number of stacked layers of the semiconductor structure can be reduced, so as to reduce parasitic capacitance generated in the semiconductor structure, reduce RC delay, and improve performance of the semiconductor structure.
In this embodiment, the second electrical interconnect structure 214 includes a second conductive plug 2141 located in the second dielectric layer 212, the second conductive plug 2141 being electrically connected to the first conductive layer 2112, a third conductive plug 2142 located in the first dielectric layer 210 and the second dielectric layer 212, the third conductive plug 2142 being electrically connected to the bottom plate layer 209, and a fourth conductive plug 2143 located in the first dielectric layer 210 and the second dielectric layer 212, the fourth conductive plug 2143 being electrically connected to the top plate layer 206.
In this embodiment, the second electrical interconnection structure 214 is formed by forming a second conductive via (not shown) in the second dielectric layer 212, the second conductive via exposing a surface of the first conductive layer 2112, forming a third conductive via (not shown) in the first dielectric layer 210 and the second dielectric layer 212, the third conductive via exposing a surface of the lower electrode layer 209, forming a fourth conductive via (not shown) in the first dielectric layer 210 and the second dielectric layer 212, the fourth conductive via exposing a surface of the upper electrode layer 206, forming a second conductive material layer (not shown) in the second conductive via, in the third conductive via, in the fourth conductive via, and on the second dielectric layer 212, planarizing the second conductive material layer until a top surface of the second dielectric layer 212 is exposed, forming the second conductive plug 2141 in the second conductive via, forming the third conductive via in the third conductive via, and forming the fourth conductive plug 2142 in the fourth conductive via 2143.
In this embodiment, the material of the second electrical interconnection structure 214 is copper.
In this embodiment, the planarization process is performed on the second conductive material layer by using a chemical mechanical polishing process.
Accordingly, in an embodiment of the present invention, a semiconductor structure is further provided, and continuing to refer to fig. 10, where the substrate 200 includes a substrate 200, a capacitor structure located on the capacitor region I, the capacitor structure includes a lower electrode plate layer 209, an insulating layer 208 located on the lower electrode plate layer 209, and an upper electrode plate layer 206 located on the insulating layer 208, a first dielectric layer 210 located on the substrate 200, where the first dielectric layer 210 covers the capacitor structure, a first electrical interconnection structure 211 located in the first dielectric layer 210, and the first electrical interconnection structure 211 is located on the non-capacitor region II, and a second dielectric layer 212 located on the first dielectric layer 210.
The first electrical interconnection structure 211 and the capacitor structure are simultaneously located in the first dielectric layer 210, so that the density and the height of the device structure between the capacitor region I and the non-capacitor region II in the first dielectric layer 210 tend to be consistent, and therefore, when the second dielectric layer 212 is formed subsequently, the top surface of the second dielectric layer 212 can be ensured to have better flatness, and when the second electrical interconnection structure 214 is formed subsequently, the metal material residue on the top surface of the second dielectric layer 212 can be reduced, and further, the problem of short circuit and leakage of the second electrical interconnection structure 214 can be effectively reduced, and the performance of the semiconductor structure is improved. In addition, by forming the first electrical interconnection structure 211 and the capacitor structure in the same process layer, the number of stacked layers of the semiconductor structure can be reduced, so as to reduce parasitic capacitance generated in the semiconductor structure, reduce RC delay, and improve performance of the semiconductor structure.
In this embodiment, the semiconductor device further includes a second electrical interconnection structure 214 located in the first dielectric layer 210 and the second dielectric layer 212, and the second electrical interconnection structure 214 is electrically connected to the first electrical interconnection structure 211 and the capacitor structure, respectively.
In this embodiment, the lower pole plate layer 209 is a composite laminate.
In this embodiment, the bottom plate layer 209 includes a first sub-plate layer 2091, a second sub-plate layer 2092 on the first sub-plate layer 2091, and a third sub-plate layer 2093 on the second sub-plate layer 2092.
In this embodiment, the second sub-plate layer 2092 is made of aluminum, and the first sub-plate layer 2091 and the third sub-plate layer 2093 are made of titanium nitride.
In this embodiment, the material of the upper plate layer 206 is titanium nitride.
In this embodiment, the first electrical interconnect structure 211 includes a first conductive plug 2111 and a first conductive layer 2112 on the first conductive plug 2111 and electrically connected to the first conductive plug 2111.
In this embodiment, the second electrical interconnect structure 214 includes a second conductive plug 2141 located in the second dielectric layer 212, the second conductive plug 2141 being electrically connected to the first conductive layer 2112, a third conductive plug 2142 located in the first dielectric layer 210 and the second dielectric layer 212, the third conductive plug 2142 being electrically connected to the bottom plate layer 209, and a fourth conductive plug 2143 located in the first dielectric layer 210 and the second dielectric layer 212, the fourth conductive plug 2143 being electrically connected to the top plate layer 206.
In this embodiment, the material of the first electrical interconnection structure 211 is copper.
In this embodiment, the material of the second electrical interconnection structure 214 is copper.
In this embodiment, the material of the first dielectric layer 210 is silicon oxide.
In this embodiment, the second dielectric layer 212 is made of silicon oxide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (22)
1. A semiconductor structure, comprising:
A substrate comprising a capacitive region and a non-capacitive region;
A capacitive structure located on the capacitive region, the capacitive structure comprising a lower pole plate layer, an insulating layer located on the lower pole plate layer, and an upper pole plate layer located on the insulating layer;
the first dielectric layer is positioned on the substrate and covers the capacitor structure;
a first electrical interconnect structure within the first dielectric layer and on the non-capacitive region.
2. The semiconductor structure of claim 1, further comprising a second dielectric layer overlying the first dielectric layer, and a second electrical interconnect structure within the first dielectric layer and the second dielectric layer, the second electrical interconnect structure electrically connected to the first electrical interconnect structure and the capacitive structure, respectively.
3. The semiconductor structure of claim 1, wherein the lower pole plate layer is a composite stack.
4. The semiconductor structure of claim 3 wherein said bottom plate layer comprises a first sub-plate layer, a second sub-plate layer on said first sub-plate layer, and a third sub-plate layer on said second sub-plate layer.
5. The semiconductor structure of claim 4, wherein the material of the second sub-plate layer comprises aluminum and the material of the first and third sub-plate layers comprises titanium nitride.
6. The semiconductor structure of claim 1, wherein the material of the upper plate layer comprises titanium nitride.
7. The semiconductor structure of claim 2, wherein the first electrical interconnect structure comprises a first conductive plug and a first conductive layer on and electrically connected to the first conductive plug.
8. The semiconductor structure of claim 7, wherein the second electrical interconnect structure comprises a second conductive plug in the second dielectric layer, the second conductive plug electrically connected to the first conductive layer, a third conductive plug in the first dielectric layer and the second dielectric layer, the third conductive plug electrically connected to the lower plate layer, and a fourth conductive plug in the first dielectric layer and the second dielectric layer, the fourth conductive plug electrically connected to the upper plate layer.
9. The semiconductor structure of claim 1, wherein the material of the first electrical interconnect structure comprises copper.
10. The semiconductor structure of claim 2, wherein the material of the second electrical interconnect structure comprises copper.
11. The semiconductor structure of claim 1, wherein the material of the first dielectric layer comprises silicon oxide.
12. The semiconductor structure of claim 2, wherein the material of the second dielectric layer comprises silicon oxide.
13. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a capacitance region and a non-capacitance region;
Forming a capacitor structure on the capacitor region, wherein the capacitor structure comprises a lower electrode plate layer, an insulating layer positioned on the lower electrode plate layer and an upper electrode plate layer positioned on the insulating layer;
the first dielectric layer is formed on the substrate and covers the capacitor structure;
A first electrical interconnect structure is formed within the first dielectric layer and is located over the non-capacitive region.
14. The method of forming a semiconductor structure of claim 13, further comprising forming a second dielectric layer over the first dielectric layer after forming the first electrical interconnect structure, and forming a second electrical interconnect structure within the first dielectric layer and the second dielectric layer, the second electrical interconnect structure electrically connected to the first electrical interconnect structure and the capacitor structure, respectively.
15. The method of forming a semiconductor structure as claimed in claim 13, wherein the method of forming a capacitor structure comprises forming a lower plate material layer on the substrate, forming an insulating material layer on the lower plate material layer, forming an upper plate material layer on the insulating material layer, and performing a patterned etching process on the upper plate material layer, the insulating material layer and the lower plate material layer to form the upper plate layer, the insulating layer and the lower plate layer, wherein the capacitor structure is formed by the upper plate layer, the insulating layer and the lower plate layer.
16. The method of claim 15, wherein the patterning the upper plate material layer, the insulating material layer, and the lower plate material layer comprises etching the upper plate material layer and a portion of the insulating material layer using a first etching process to form the upper plate layer, depositing a first anti-reflective layer that covers the exposed surface of the upper plate layer and the exposed surface of the insulating material layer, and etching the first anti-reflective layer, the remaining portion of the insulating material layer, and the lower plate material layer using a second etching process to form the insulating layer and the lower plate layer.
17. The method of forming a semiconductor structure of claim 13, wherein the lower pole plate layer is a composite stack.
18. The method of forming a semiconductor structure of claim 17 wherein said bottom plate layer comprises a first sub-plate layer, a second sub-plate layer on said first sub-plate layer, and a third sub-plate layer on said second sub-plate layer.
19. The method of forming a semiconductor structure as recited in claim 14 wherein said first electrical interconnect structure comprises a first conductive plug and a first conductive layer on said first conductive plug and electrically connected to said first conductive plug.
20. The method of forming a semiconductor structure of claim 19, wherein said first electrical interconnect structure is formed by forming a first conductive via and said first conductive trench in said first dielectric layer using a damascene process, said first conductive trench exposing said first conductive via, forming a first conductive material layer in said first conductive via, in said first conductive trench and on said first dielectric layer, planarizing said first conductive material layer until a top surface of said first dielectric layer is exposed, forming said first conductive plug in said first conductive via, and forming said first conductive layer in said first conductive trench.
21. The method of forming a semiconductor structure of claim 19, wherein said second electrical interconnect structure comprises a second conductive plug in said second dielectric layer, said second conductive plug electrically connected to said first conductive layer, a third conductive plug in said first dielectric layer and said second dielectric layer, said third conductive plug electrically connected to said lower plate layer, and a fourth conductive plug in said first dielectric layer and said second dielectric layer, said fourth conductive plug electrically connected to said upper plate layer.
22. The method of forming a semiconductor structure of claim 21, wherein the forming of the second electrical interconnect structure comprises forming a second conductive via in the second dielectric layer exposing a surface of the first conductive layer, forming a third conductive via in the first dielectric layer and the second dielectric layer exposing a surface of the lower plate layer, forming a fourth conductive via in the first dielectric layer and the second dielectric layer exposing a surface of the upper plate layer, forming a second conductive material layer in the second conductive via, in the third conductive via, in the fourth conductive via, and on the second dielectric layer, planarizing the second conductive material layer until a top surface of the second dielectric layer is exposed, forming the second conductive plug in the second conductive via, forming the third conductive plug in the third conductive via, and forming the fourth conductive plug in the fourth conductive via.
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