CN121604792A - Method for detecting open circuit of through hole in back-end process of semiconductor device - Google Patents

Abstract

This invention provides a method for detecting open vias in the back-end manufacturing process of semiconductor devices. The method includes: providing a semiconductor wafer subjected to a first chemical mechanical polishing (CMP) process, on which an interconnect structure including vias and overlay trenches is formed; performing a second CMP process on the semiconductor wafer to remove conductive material from the trenches until the top surface of the vias is exposed; and finally, using an electron beam to inspect the processed semiconductor wafer and determining whether an open-circuit defect exists in the vias based on the voltage contrast signal. This invention solves the technical problem that existing electron beam detection cannot detect individual open-circuit defects in redundant multi-via structures by adding a single CMP process to expose and physically separate each via, significantly improving detection efficiency and data volume, and shortening the analysis cycle for process problems.

Description

Method for detecting open circuit of through hole in back-end process of semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for detecting open circuit of a through hole in a back-end process of a semiconductor device.

Background

In semiconductor device fabrication technology, as process nodes continue to shrink, the reliability of metal interconnect structures in back-end-of-line (BEOL) plays a decisive role in chip performance and yield. Among them, open defects of vias (Via) for connecting different metal layers are a common failure mode, which seriously affects the electrical performance of the circuit.

Currently, electron beam inspection (E-beam) is a common technique used for wafer defect inspection. The principle is to scan the wafer surface with a focused electron beam and identify defects by detecting differences in secondary or backscattered electron signals. An electrical defect such as an open circuit or a short circuit causes a change in local surface potential, resulting in a significant Voltage Contrast (VC) of the electronic signal. For example, when the upper metal layer is connected to the lower structure through a single via, if the via is open, the electron beam detection can effectively identify the via by a Dark Voltage Contrast (DVC) signal (as shown in fig. 1), so that the electron beam detection technology can efficiently find such defects, and has the advantages of no damage, fast scanning speed, wide coverage area, and the like.

However, the existing electron beam detection method has significant limitations when applied to open-circuit detection of a through hole in a back-end-of-line process. Specifically, in the advanced process, in order to improve the reliability and electrical performance of the circuit, a redundant structure is generally designed in which a plurality of through holes (Multi-via) are connected under a single metal strip. With this structure, if only a part of the through holes are open, the remaining intact through holes can still provide a conductive path for the upper metal strip, so that the potential of the entire metal strip remains normal. Therefore, the conventional electron beam detection method cannot generate an effective voltage contrast signal on the surface of the upper metal strip, so that the hidden defect of the partial through hole open circuit cannot be detected.

To solve the above problems, it is currently common practice in the industry to rely on means of Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA). For example, after a chip with abnormal performance is found through an electrical test (such as WAT), a specific failure point needs to be positioned with high precision, and a destructive means such as a Transmission Electron Microscope (TEM) is used for point-by-point slicing and physical characterization to confirm the root cause of the open circuit of the through hole. Specific physical morphologies that lead to open vias can be observed by TEM analysis, and these morphologies may include voids between the Via bottom and the underlying Metal (e.g., "under Via voids" as shown in fig. 2, i.e., voidunder Via), complete absence of part of the Via structure during fabrication (e.g., "under Via voids" as shown in fig. 3, i.e., VIA MISSING), voids formed when the Via is filled with conductive material (e.g., "Via voids" as shown in fig. 4, i.e., via void), while affecting the vast voids of the Via and the overlying Metal (e.g., "Metal and Via voids" as shown in fig. 5, i.e., metal & Via void), or the presence of residues at the Via bottom due to incomplete etching that block electrical connection (e.g., "Via bottom etch residue" as shown in fig. 6, i.e., via void ET), and the like.

The method has the obvious defects that the analysis period is extremely long, the complete analysis of one point location generally takes more than one week, the method belongs to destructive analysis, the subsequent treatment of the wafer cannot be carried out, only a single point location can be analyzed at a time, the acquired data quantity is extremely small, the statistical significance is lacking, and the process stability of the whole wafer or batch is difficult to evaluate rapidly and comprehensively.

Therefore, there is a need to develop a new method capable of rapidly and nondestructively detecting single or partial open defects of a multi-via structure in a back-end-of-line process of an advanced process in a large area, so as to improve defect monitoring efficiency in development and production processes and accelerate the solution of process problems.

Disclosure of Invention

The invention aims to solve the technical problem of providing a method capable of rapidly and widely detecting single or partial open defects of a through hole under a multi-through hole structure in the back-end process of a semiconductor so as to overcome the defects that electron beam detection cannot detect the defects in the prior art, and the defects of long time consumption and small data quantity are dependent on physical failure analysis.

In order to achieve the above purpose, the present invention provides the following technical solutions:

A method for detecting open circuit of through hole in back-end process of semiconductor device includes the following steps:

Providing a semiconductor wafer subjected to a first chemical mechanical polishing process, wherein an interconnection structure is formed on the semiconductor wafer, and comprises a through hole filled with a conductive material and a groove positioned above the through hole;

Performing a second chemical mechanical polishing process on the semiconductor wafer to remove the conductive material in the trench until the top surface of the via hole is exposed, and

And thirdly, detecting the semiconductor wafer subjected to the second chemical mechanical polishing process by adopting an electron beam so as to determine whether the through hole has an open circuit defect according to the voltage contrast signal.

Preferably, the interconnect structure includes a plurality of the vias connected to the same trench.

Preferably, before the first step, the semiconductor wafer is subjected to a four-quadrant process experiment or an energy matrix experiment.

Preferably, the interconnection structure is a back-end-of-line interconnection layer other than the first metal interconnection layer.

Preferably, in the second step, the polishing selection ratio is controlled by adjusting the process parameters of the second chemical mechanical polishing process to prevent the conductive material from remaining or being excessively polished.

Preferably, the process parameters include adjusting a pattern loading effect.

Preferably, in the third step, the electron beam detection preferentially selects a region with a high density of through holes for scanning.

Preferably, step three further comprises analyzing the voltage contrast signal to exclude spurious defect signals generated by the suspended metal structure.

Preferably, the conductive material is copper or copper alloy.

As described above, the method for detecting the open circuit of the through hole in the back-end process of the semiconductor device has the following advantages:

The invention successfully solves the technical problem that the existing electron beam detection method can not effectively detect the single open defect under the multi-through hole redundant structure by adding a chemical mechanical polishing process to expose and physically separate each through hole. Meanwhile, the defect analysis time is shortened from about one week required by physical analysis of a single point in the prior art to complete large-area wafer scanning within tens of hours, so that the detection efficiency is greatly improved and the solving speed of the process problem is increased. In addition, the invention can realize large-area and nondestructive rapid scanning, can obtain a large amount of defect data covering a plurality of areas of the wafer, and provides statistically significant information for process monitoring, yield analysis and process optimization, which is incomparable with the traditional single-point destructive analysis.

Drawings

FIG. 1 is a schematic diagram of electron beam detection of open defects of a via according to the prior art;

FIG. 2 is a graph showing hole defect morphology under a through hole observed by a transmission electron microscope according to the prior art;

FIG. 3 shows a pattern of via hole deficiency defects observed by a transmission electron microscope according to the prior art;

FIG. 4 is a graph showing the morphology of hole defects observed by a transmission electron microscope according to the prior art;

FIG. 5 is a graph showing the morphology of metal and via hole defects observed by a transmission electron microscope according to the prior art;

FIG. 6 is a graph showing the morphology of residual defects of via bottom etching observed by a transmission electron microscope according to the prior art;

FIG. 7 is a flow chart of a method according to an embodiment of the invention;

FIG. 8 is a schematic cross-sectional view of an interconnect structure to be inspected according to an embodiment of the invention;

FIG. 9 is a schematic diagram of a four-quadrant process according to one embodiment of the present invention;

FIG. 10 is a schematic diagram of an energy matrix experiment according to an embodiment of the present invention;

FIG. 11 is a schematic cross-sectional view of an interconnect structure after a second chemical mechanical polishing process, in accordance with an embodiment of the present invention;

FIG. 12 is a graph showing voltage contrast defect signals found by electron beam inspection according to one embodiment of the present invention;

FIG. 13 is a diagram of layered defects obtained according to an embodiment of the present invention;

FIG. 14 is a schematic diagram showing a defect generation mechanism according to an embodiment of the present invention;

FIG. 15 is a wafer map of the total number of defects obtained in accordance with one embodiment of the present invention;

FIG. 16 is a graph showing a distribution of real voltage contrast defects on a wafer, as detected in accordance with one embodiment of the present invention.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

The invention provides a method for detecting open circuit of a through hole in the back-end process of a semiconductor device, the whole flow of which is shown in figure 7. The method comprises the following steps:

Step one, a semiconductor wafer subjected to a first chemical mechanical polishing process is provided, and an interconnection structure is formed on the semiconductor wafer, wherein the interconnection structure comprises a through hole filled with conductive material and a groove positioned above the through hole.

Fig. 8 schematically illustrates a cross-sectional view of the interconnect structure provided by this step, in which it is seen that the first layer of via V1 connects to the lower layer of metal (not shown) and supports the second layer of metal M2, which in turn connects to the upper layer of third layer of metal M3 through the second layer of via V2. M3 here corresponds to a "trench" filled with a conductive material as described in the claims, and V2 is a "via" to be detected.

In a specific process implementation, the interconnect structure is typically formed using a dual damascene process. Taking the dual damascene process as an example, the formation process typically includes the steps of first depositing an etch stop layer on the underlying metal interconnect layer or substrate, the etch stop layer material being silicon nitride (SiN), silicon carbide nitride (SiCN) or silicon oxynitride (SiON) to precisely control the etch depth in the subsequent etch step. One or more layers of an interlayer dielectric (ILD) material, typically a low-k or ultra-low-k material, are then deposited over the etch stop layer. Subsequently, a pattern of vias and a pattern of trenches are formed in the interlayer dielectric material sequentially or simultaneously by photolithography and etching processes. After etching, a barrier layer and/or a liner layer are deposited on the surface of the patterned dielectric layer and the inner walls of the through holes and the grooves by adopting Physical Vapor Deposition (PVD) or Atomic Layer Deposition (ALD) and other methods. The barrier layer material is typically tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), or a multilayer stack thereof. Finally, conductive material is filled into the through holes and the trenches by electrochemical deposition (ECP) or physical vapor deposition, etc., and a first chemical mechanical polishing process is performed for planarization.

In some embodiments, the interconnect structure includes a plurality of vias connected to the same trench. Such redundant designs of multiple via connections to a single metal strip are very common in advanced process nodes to improve the reliability of the circuit. However, it is this design that makes conventional e-beam inspection methods unable to detect open defects in a single via, because other intact vias still provide a conductive path for the overlying metal strip, thereby masking the defect signal. The method of the invention solves the technical problem exactly.

In some embodiments, prior to step one, the semiconductor wafer is subjected to a four-quadrant process experiment or an Energy Matrix (EM) experiment. As shown in fig. 9, which is a schematic diagram of a four-quadrant process experiment, by applying different process parameters (e.g., shift in exposure DOSE wise) to different quadrant regions of the wafer, the process window can be systematically studied and potential edge defects actively induced. Similarly, fig. 10 shows a schematic diagram of an energy matrix experiment that intentionally varies the critical dimensions of vias over different areas of a wafer by systematically adjusting the process energy (e.g., photolithographic exposure energy or etching energy) used to form the vias. Through the process treatments, specific process parameter deviation can be applied to the wafer, and the deviation can effectively induce or amplify potential weak open-circuit defects of the through holes in the process, so that the capturing rate of the defects in the subsequent detection step is improved.

In some embodiments, the interconnect structure is a back-end-of-line interconnect layer other than the first metal interconnect layer. Generally, the method is applied to a second level metal interconnect layer (M2) and to global or semi-global interconnect layers above. This is because the first metal interconnect layer (M1) is typically directly connected to front-end devices such as transistors, and the structure and design rules are different from the upper level metals, while the multi-via redundancy structure is more common in the M2 and above levels.

In some embodiments, the conductive material is copper or a copper alloy. In other embodiments, the conductive material may be other advanced conductive metals suitable for back-end-of-line processing, such as cobalt (Co), ruthenium (Ru), molybdenum (Mo), or combinations thereof, to meet resistivity and reliability requirements at smaller process nodes.

And step two, performing a second chemical mechanical polishing process on the semiconductor wafer to remove the conductive material in the groove until the top surface of the through hole is exposed. By performing an additional cmp, the upper metal strip (i.e., M3 in fig. 8) is completely removed such that the top ends of the plurality of vias (e.g., V2 in fig. 8) that were otherwise connected together by the metal strip are exposed and physically separated from each other. The cross section of the structure after the treatment is shown in fig. 11. In this way, each through hole becomes an independent electrical detection node, and a necessary condition is created for accurately identifying the open circuit state of the single through hole by using an electron beam.

In some embodiments, in step two, the polishing selectivity is controlled by adjusting process parameters of the second chemical mechanical polishing process to prevent conductive material residue or overpolish. The process parameters include adjusting the pattern loading effect. In order to achieve accurate removal of conductive material in the trench without damaging the exposed via top surface and surrounding dielectric material, the parameters of the chemical mechanical polishing need to be carefully controlled. Accurate process control can ensure that a flat surface is obtained, which is beneficial to the stability and accuracy of the subsequent electron beam detection signals.

And thirdly, detecting the semiconductor wafer subjected to the second chemical mechanical polishing process by adopting an electron beam so as to determine whether the through hole has an open circuit defect according to the voltage contrast signal. After the top surface of the via is exposed, the wafer surface is scanned with an electron beam. For connecting normal vias, they can form an effective discharge loop through the underlying metal structure, whose surface potential remains stable or near the substrate potential under electron beam irradiation. And for the through hole with open circuit defect, the through hole is electrically in a suspension state, and charge accumulation can occur under the irradiation of electron beams, so that the surface potential of the through hole is obviously different from that of a normal through hole, and a voltage contrast signal with sharp contrast is formed in a secondary electron image. As shown in fig. 12, the bright spot marked in the GVC (gray voltage contrast) image on the left side is a through hole of an open defect, and the reference (ref.) image on the right side shows a signal of a normal area. Fig. 13 further illustrates a delamination defect map obtained by the method of the invention. It can be seen that significant defect signals appear on VDEF (via defect) levels in the middle row, while M2 DEF (metal layer defect) and VDEF _sc (short defect) in the upper and lower rows have no signals, which clearly indicate that the defect type is via open, but not metal layer open or via short, validating the accuracy of the method. Fig. 14 intuitively explains the physical cause of defect generation, namely, the etching residue (Via under ET) at the bottom of the Via hole causes the electrical connection between the Via hole V2 and the metal layer M2 to be disconnected, thereby generating the DVC signal.

In some embodiments, in step three, electron beam detection preferentially selects areas of high via density for scanning. In chip layouts, areas with high via densities are often challenges for process control, and the probability of defects occurring is relatively high. Therefore, preferential scanning of these areas can more efficiently discover potential process problems, maximizing defect detection rate within a limited detection time.

In some embodiments, step three further includes analyzing the voltage contrast signal to exclude spurious defect signals generated by the floating metal structure. In the layout design, there may be some test structures or filled metal patterns which are in an electrical suspension state, and these structures also generate voltage contrast signals in electron beam detection. Therefore, the detected defect coordinates are compared with the design layout, or a specific algorithm is adopted to perform intelligent filtering so as to remove the pseudo defect signals generated by the known suspension structures, thereby ensuring that the finally reported defects are all real through hole open problems.

The method provided by the invention can overcome the bottleneck of the prior art and realize the rapid and large-area detection of single or partial open circuit of the through holes under the multi-through hole structure. Under the advanced process node, 61 die positions (die) are scanned by the method, as shown in fig. 15, which is a wafer map of the total number of defects, wherein the colors and values represent the defect densities of different areas, and only 36 hours are required to cover 1.28% of the wafer area, and 6 real voltage contrast defect points are successfully detected. As shown in fig. 16, the 6 real GVC defect points are clearly distributed on the wafer map. Compared with the traditional method of relying on a single point to perform physical failure analysis (EFA), which takes about one week for each point, the efficiency of the method is greatly improved. The method not only shortens the analysis period of the process problem obviously, but also can provide a large amount of data with statistical significance, and provides technical support for the research and development of the advanced semiconductor process, mass production and yield monitoring.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. A method for detecting open vias in the back-end process of a semiconductor device, characterized in that it includes at least: Step 1: Provide a semiconductor wafer that has undergone a first chemical mechanical polishing process, wherein an interconnect structure is formed on the semiconductor wafer, the interconnect structure including vias filled with conductive material and trenches located above the vias; Step 2: Perform a second chemical mechanical polishing process on the semiconductor wafer to remove the conductive material in the trench until the top surface of the via is exposed; Step 3: Use an electron beam to inspect the semiconductor wafer after the second chemical mechanical polishing process to determine whether the via has an open circuit defect based on the voltage contrast signal. 2. The method for detecting open vias in the back-end process of a semiconductor device according to claim 1, wherein the interconnect structure includes a plurality of vias connected to the same trench. 3. The method for detecting open vias in the back-end process of a semiconductor device according to claim 1 or 2, characterized in that: before step one, the semiconductor wafer undergoes a four-quadrant process experiment or an energy matrix experiment. 4. The method for detecting open vias in the back-end process of a semiconductor device according to claim 1, wherein the interconnect structure is a back-end process interconnect layer other than the first metal interconnect layer. 5. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: in step two, the polishing selectivity is controlled by adjusting the process parameters of the second chemical mechanical polishing process to prevent conductive material residue or over-polishing. 6. The method for detecting open vias in the back-end process of a semiconductor device according to claim 5, characterized in that: the process parameters include adjusting the pattern load effect. 7. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: in step three, the electron beam detection preferentially selects the region with high via density for scanning. 8. The method for detecting open vias in the back-end process of semiconductor devices according to claim 1, characterized in that: step three further includes: analyzing the voltage contrast signal to eliminate false defect signals generated by the suspended metal structure. 9. The method for detecting open vias in the back-end process of a semiconductor device according to claim 1, wherein the conductive material is copper or a copper alloy.