CN121620002A

CN121620002A - Solar cell and battery assembly

Info

Publication number: CN121620002A
Application number: CN202511784276.8A
Authority: CN
Inventors: 赵鑫; 朱海涛; 王永谦
Original assignee: Shandong Aixu Solar Energy Technology Co ltd; Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Current assignee: Shandong Aixu Solar Energy Technology Co ltd; Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Priority date: 2025-11-28
Filing date: 2025-11-28
Publication date: 2026-03-06

Abstract

The invention discloses a solar cell and a cell assembly, which comprise a substrate, a first auxiliary grid line and a second auxiliary grid line, wherein the first auxiliary grid line and the second auxiliary grid line are arranged on the substrate, the first auxiliary grid line and the second auxiliary grid line are arranged in an extending mode along a second direction and are alternately arranged in the first direction, the first main grid line is arranged in an extending mode along the first direction and is connected with the first auxiliary grid line and is spaced from the second auxiliary grid line, the second main grid line is arranged in an extending mode along the first direction and is connected with the second auxiliary grid line and is spaced from the first auxiliary grid line, the orthographic projection of the third auxiliary grid line on the substrate is located in the orthographic projection of the first main grid line on the substrate and is electrically connected with the first main grid line, and/or the orthographic projection of the fourth auxiliary grid line on the substrate is located in the orthographic projection of the second main grid line on the substrate and is electrically connected with the second main grid line, and the whole photoelectric conversion efficiency of the cell is improved.

Description

Solar cell and battery assembly

Technical Field

The embodiment of the invention relates to the technical field of photovoltaics, in particular to a solar cell and a cell assembly.

Background

In order to effectively conduct out the current generated by the solar cell, a large number of grid lines are provided on the solar cell panel. The grid lines are covered on the surface of the battery plate in a specific pattern to form a grid-like structure. When sunlight irradiates the panel, current generated by the photovoltaic effect is effectively collected and conducted out through the grid lines.

Currently, there is still a need for improvement in improving the conversion efficiency of solar cells by patterning the gate lines.

Disclosure of Invention

The invention provides a solar cell and a cell assembly, which realize that the overall photoelectric conversion efficiency of the cell is improved.

In a first aspect, an embodiment of the present invention provides a solar cell, including:

A substrate;

The first auxiliary grid line and the second auxiliary grid line are arranged on the substrate, extend along a second direction and are alternately arranged in a first direction, and the first direction intersects with the second direction;

the first main grid line is arranged along the first direction in an extending way, is connected with the first auxiliary grid line and is spaced from the second auxiliary grid line;

The second main grid line is arranged along the first direction in an extending way, is connected with the second auxiliary grid line and is spaced from the first auxiliary grid line;

And the orthographic projection of the third auxiliary grid line on the substrate is positioned in the orthographic projection of the first main grid line on the substrate and is electrically connected with the first main grid line, and/or the orthographic projection of the fourth auxiliary grid line on the substrate is positioned in the orthographic projection of the second main grid line on the substrate and is electrically connected with the second main grid line.

Optionally, the third auxiliary grid line comprises at least one first continuous grid line extending along the first direction, wherein the first continuous grid line is crossed with the first auxiliary grid line;

And/or the fourth sub-grid line comprises at least one second continuous grid line extending along the first direction, and the second continuous grid line is crossed with the second sub-grid line.

Optionally, along the first direction, the length of the first continuous gate line is less than or equal to the length of the first main gate line;

and/or the length of the second continuous grid line is smaller than or equal to the length of the second main grid line.

Optionally, the third auxiliary grid line comprises a plurality of first auxiliary grid line segments which are arranged at intervals along the first direction, wherein the first auxiliary grid line segments do not cross with the first auxiliary grid line or at least part of the first auxiliary grid line segments cross with the first auxiliary grid line;

And/or the fourth auxiliary grid line comprises a plurality of second auxiliary grid line segments which are arranged at intervals along the first direction, wherein the second auxiliary grid line segments do not cross the second auxiliary grid line or at least part of the second auxiliary grid line segments cross the second auxiliary grid line.

Optionally, the third auxiliary grid line comprises a plurality of first conductive points which are arranged at intervals along the first direction, wherein the first conductive points do not overlap with the first auxiliary grid line or at least part of the first conductive points overlap with the first auxiliary grid line;

And/or the fourth sub-grid line comprises a plurality of second conductive points which are arranged at intervals along the first direction, wherein the second conductive points do not overlap with the second sub-grid line or at least part of the second conductive points overlap with the second sub-grid line.

Optionally, the third sub-gate line includes a plurality of third sub-gate line segments extending along the second direction, and the third sub-gate line segments are arranged at intervals in the first direction;

And/or the fourth sub-grid line comprises a plurality of fourth sub-grid line segments extending along the second direction, and the fourth sub-grid line segments are arranged at intervals in the first direction.

Optionally, the third auxiliary gate line is located at a side of the first main gate line, which is close to the substrate or far from the substrate;

and/or the fourth auxiliary grid line is positioned at one side of the second main grid line, which is close to the substrate or far from the substrate.

Optionally, the first sub-gate line, the second sub-gate line, the third sub-gate line and the fourth sub-gate line are arranged in the same layer.

Optionally, the substrate includes a first doped layer and a second doped layer, the first doped layer includes a first doped sub-region, the first doped sub-region extends along the second direction, the second doped layer includes a second doped sub-region, the second doped sub-region extends along the second direction, and the first doped sub-region and the second doped sub-region are alternately arranged along the first direction;

the first doped subregion extends continuously at the first main grid line, the second doped subregion is interrupted at the first main grid line, the second doped subregion extends continuously at the second main grid line, and the first doped subregion is interrupted at the second main grid line;

The orthographic projection of the first auxiliary grid line on the substrate is located in orthographic projection of the first doping subarea on the substrate, the first auxiliary grid line is electrically connected with the first doping subarea, orthographic projection of the second auxiliary grid line on the substrate is located in orthographic projection of the second doping subarea on the substrate, the second auxiliary grid line is electrically connected with the second doping subarea, and the conductivity types of the first doping layer and the second doping layer are different.

The first doping layer comprises a third doping subarea, the width of the third doping subarea is larger than that of the first main grid line along the second direction, the orthographic projection of the third auxiliary grid line on the substrate is located in the orthographic projection of the third doping subarea on the substrate, the third auxiliary grid line is electrically connected with the third doping subarea, or the second doping layer comprises a fourth doping subarea, the width of the fourth doping subarea is larger than that of the second main grid line along the second direction, the orthographic projection of the fourth auxiliary grid line on the substrate is located in the orthographic projection of the fourth doping subarea on the substrate, and the fourth auxiliary grid line is electrically connected with the fourth doping subarea.

In a second aspect, an embodiment of the present invention provides a battery assembly including the solar cell according to any of the embodiments of the present invention.

The solar cell provided by the embodiment of the invention comprises the first auxiliary grid lines and the second auxiliary grid lines which are arranged in an extending manner along the second direction Y and are alternately arranged in the first direction X, wherein the first main grid line is intersected with the first auxiliary grid lines and is electrically connected, the second auxiliary grid is interrupted at the position intersected with the first main grid line, the second main grid line is intersected with the second auxiliary grid line and is electrically connected, the first auxiliary grid line is interrupted at the position intersected with the second main grid line, and the third auxiliary grid line is introduced into the orthographic projection area of the first main grid line, and/or the fourth auxiliary grid line is introduced into the orthographic projection area of the second main grid line, and the photon-generated carriers in the area below the main grid are directly collected by utilizing the third auxiliary grid line and/or the fourth auxiliary grid line, so that the carrier diffusion path is reduced, the composite loss is facilitated, the collecting blind area in the traditional structure is effectively eliminated, and the whole photoelectric conversion efficiency of the cell is further improved.

Drawings

Fig. 1 is a schematic diagram of a partial structure of a solar cell according to an embodiment of the present invention;

fig. 2-3 are schematic partial structures of a solar cell according to another embodiment of the present invention;

Fig. 4 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention;

fig. 5 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention;

Fig. 6 to 7 are schematic partial structures of a solar cell according to another embodiment of the present invention;

fig. 8 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention;

fig. 9 is a schematic view of a partial structure of a solar cell according to another embodiment of the present invention;

Fig. 10 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention.

Reference numerals:

110. The first auxiliary grid line, 120, second auxiliary grid line, 130, third auxiliary grid line, 131, first continuous grid line, 132, first auxiliary grid line, 133, first conductive point, 134, third auxiliary grid line, 140, first main grid line, 150, first doping layer, 151, first doping subarea, 152, third doping subarea, 160, second doping layer, 161, second doping subarea, 162, fourth doping subarea, 170, second main grid line, 180, fourth auxiliary grid line, 181, second continuous grid line, 182, second auxiliary grid line, 183, second conductive point, 184, fourth auxiliary grid line;

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In a solar cell comprising a substrate on which functional layers are provided, the current is finally collected by a grid line, which usually consists of a number of main grid lines and a number of sub-grid lines. The main grid line is used for collecting photo-generated carriers collected by the auxiliary grid line and transmitting the photo-generated carriers to an external circuit, and the width of the photo-generated carriers is large and is usually 5% -15% of the whole area of the battery piece. In order to reduce contact recombination or to be compatible with passivation contact structures, the main gate region is often printed with non-burn-through conductive paste, which does not penetrate the surface passivation layer during sintering, and thus cannot form ohmic contact with the silicon substrate. This results in the photo-generated carriers in the region directly below the main gate not being able to be collected directly by the main gate, but rather having to rely on the sub-gate lines running through the main gate region for lateral transport. However, due to the large main gate coverage area, carriers need to pass through a long lateral diffusion path to reach an effective collection point, and the carriers are easily lost due to recombination during the period, so that the short-circuit current and the filling factor are remarkably reduced. Particularly in the high-efficiency cell structure, the region becomes a dead zone for collecting carriers, which restricts the further improvement of the overall photoelectric conversion efficiency of the cell.

In view of the above, fig. 1 is a schematic diagram of a partial structure of a solar cell according to an embodiment of the invention, referring to fig. 1, including a substrate 1, a first sub-gate line 110, a second sub-gate line 120, a third sub-gate line 130, a first main gate line 140 and a second main gate line 170, wherein the substrate 1 may be an N-type or P-type doped semiconductor substrate. The substrate 1 includes opposite first and second surfaces, and the first, second, third, and second sub-grids 110, 120, 130, 140, and 170 may be disposed on the first, second, or both surfaces, depending on the type of structure of the solar cell (e.g., IBC, TOPCon, HJT, etc.). In the embodiment of the invention, taking the full back electrode contact battery (INTERDIGITATED BACK CONTACT, IBC) as an example, the first auxiliary grid line 110, the second auxiliary grid line 120, the third auxiliary grid line 130, the first main grid line 140 and the second main grid line 170 are arranged on the first surface, namely, the back surface of the substrate, so that no grid line shielding on the front surface can be realized, and the light absorption capacity can be maximized.

As shown in fig. 1, the first and second sub-gate lines 110 and 120 extend in a second direction Y, and the first and second sub-gate lines 110 and 120 are alternately arranged in a first direction X, which intersects the second direction Y, and is exemplary, perpendicular to the first direction X and the second direction Y. The first and second sub-gate lines 110 and 120 extend to regions where electron-hole pairs are generated within the substrate for efficiently collecting photo-generated carriers dispersed throughout the substrate. Wherein the first sub-gate line 110 is used for collecting carriers of a first conductivity type, and the second sub-gate line 120 is used for collecting carriers of an opposite conductivity type. It should be noted that the carriers of the first conductivity type may be electrons, and the carriers of the opposite conductivity type may be holes. Alternatively, the carriers of the first conductivity type may be holes and the carriers of the opposite conductivity type may be electrons.

The first main gate line 140 extends along the first direction X, the first sub gate line 110 intersects with the first main gate line 140 and is electrically connected, and the second sub gate line 120 is disconnected at a position where the first main gate line 140 intersects to form a space, so that short circuit caused by gate line contact with different polarities is avoided. The first main gate line 140 is electrically connected with the first auxiliary gate line 110, the first main gate line 140 can provide a low-resistance path, the average distance of current transmission is shortened, and the first main gate line 140 can efficiently collect the current of the first auxiliary gate line 110, so that the series resistance of the whole battery is remarkably reduced, and the filling factor and conversion efficiency of the battery are improved. The second main gate lines 170 extend along the first direction X and are alternately arranged with the first main gate lines 140 in the second direction Y, the second main gate lines 170 intersect with and are electrically connected to the second sub-gate lines 120, the second main gate lines 170 may provide a low resistance path, an average distance of current transmission is shortened, and the second main gate lines 170 may efficiently collect currents of the second sub-gate lines 120. Accordingly, the first sub-gate line 110 and the second main gate line 170 are separated from each other at the crossing position to form a space, thereby avoiding a short circuit between the electrodes of different polarities.

Because the first main grid line 140 is usually printed by adopting non-burning-through conductive paste, ohmic contact cannot be directly formed with the silicon substrate, and the area below the first main grid line is easy to become a dead zone for collecting current carriers, in the embodiment of the invention, the solar cell is further provided with the third auxiliary grid line 130, the orthographic projection of the third auxiliary grid line 130 on the substrate 1 is positioned in the orthographic projection of the first main grid line 140 on the substrate 1, the third auxiliary grid line 130 extends along the first direction X and is electrically connected with the first main grid line 140, and the third auxiliary grid line 130 is utilized to directly collect the photo-generated current carriers in the area below the main grid, so that the current carrier diffusion path is reduced, the composite loss is facilitated to be reduced, the collecting dead zone in the traditional structure is effectively eliminated, and the overall photoelectric conversion efficiency of the cell is further improved.

The solar cell provided by the embodiment of the invention comprises the first auxiliary grid lines 110 and the second auxiliary grid lines 120 which are arranged along the second direction Y in an extending manner and are alternately arranged in the first direction X, the first main grid line 140 is intersected with the first auxiliary grid line 110 and is electrically connected, the second auxiliary grid line is interrupted at the position intersected with the first main grid line 140, the second main grid line 170 is intersected with the second auxiliary grid line 120 and is electrically connected, the first auxiliary grid line 110 is interrupted at the position intersected with the second main grid line 170, and the third auxiliary grid line 130 is introduced into the orthographic projection area of the first main grid line 140, so that the photo-generated carriers in the area below the main grid are directly collected by utilizing the third auxiliary grid line 130, thereby reducing the carrier diffusion path, being beneficial to reducing the recombination loss, effectively eliminating the collecting blind area in the traditional structure and further improving the whole photoelectric conversion efficiency of the cell.

Referring to fig. 1, in the embodiment of the invention, a fourth auxiliary grid line 180 is further provided, the orthographic projection of the fourth auxiliary grid line 180 on the substrate 1 is located in the orthographic projection of the second main grid line 170 on the substrate 1, the fourth auxiliary grid line 180 extends along the first direction X and is electrically connected with the second main grid line 170, and the fourth auxiliary grid line 180 is utilized to directly collect photo-generated carriers in the area below the second main grid line 170, so that the carrier diffusion path is reduced, the composite loss is reduced, the collecting blind area in the traditional structure is effectively eliminated, and the overall photoelectric conversion efficiency of the battery is further improved. It should be noted that, in some embodiments, only the third sub-gate line 130 or only the fourth sub-gate line 180 may be provided, or the third sub-gate line 130 and the fourth sub-gate line 180 may be provided at the same time, depending on the design of the solar cell, the material cost, and the like.

Optionally, referring to fig. 1, the third sub-gate line 130 may intersect the first sub-gate line 110, and exemplary, the third sub-gate line 130 may include at least one first continuous gate line 131 extending along the first direction X, where the first continuous gate line 131 intersects the first sub-gate line 110, that is, the first continuous gate line 131 is a continuous line, and the length of the first continuous gate line 131 is less than or equal to the length of the first main gate line 140 along the first direction X, that is, the length of the first continuous gate line 131 may be adapted to the length of the first main gate line 140, so that the area under the entire first main gate line 140 may be collected. In the embodiment of the present invention, it is exemplarily shown that the first main gate line 140 is provided with one first continuous gate line 131 at a corresponding position, and in other embodiments, according to the width of the first main gate line 140 in the second direction Y, a plurality of first continuous gate lines 131 may be arranged in parallel in the second direction Y, so as to form a third auxiliary gate line 130 array arranged in parallel, so as to further improve the carrier collection density and uniformity of the coverage area of the first main gate line 140.

Fig. 2-3 are schematic partial structures of a solar cell according to another embodiment of the present invention, and referring to fig. 2 and 3, the difference between the embodiment of the present invention and the above embodiment is that the third sub-gate line 130 may include a plurality of first sub-gate line segments 132 arranged at intervals along the first direction X, and the spatial relationship between the first sub-gate line segments 132 and the first sub-gate line 110 may be flexibly configured to achieve both carrier collection efficiency and material cost.

In fig. 2, the first sub-gate line segment 132 does not intersect the first sub-gate line 110, that is, the first sub-gate line segment 132 is located between the adjacent first sub-gate lines 110 in the first direction X. At least a portion of the first sub-gate line segment 132 in fig. 3 intersects the first sub-gate line 110, and the intersecting structure may form a low-resistance current path, which is conducive to quickly collecting carriers collected by the third sub-gate line segment 134 into the first sub-gate line 110, thereby reducing a local bus resistance and improving current collection efficiency.

In the embodiment of the present invention, by adopting the first auxiliary gate line segments 132 arranged in multiple segments at intervals, the usage amount of the conductive paste, such as silver paste, can be significantly reduced and the manufacturing cost can be reduced on the premise of ensuring the uniformity of collecting carriers in the orthographic projection area of the first main gate line 140. Meanwhile, the length, width and spacing of the line segments can be optimally designed according to the geometric dimension, doping distribution and carrier diffusion length of the main grid line, so that the optimal balance of performance and cost is realized. In the embodiment of the present invention, the first auxiliary gate line segments 132 arranged in a row are exemplarily shown in the corresponding position of the first main gate line 140, and in other embodiments, according to the width of the first main gate line 140 in the second direction Y, a plurality of first auxiliary gate line segments 132 may be arranged in parallel in the second direction Y to form a third auxiliary gate line 130 array arranged in parallel, so as to further improve the carrier collection density and uniformity of the coverage area of the first main gate line 140.

Fig. 4 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention, and referring to fig. 4, the embodiment of the present invention is different from the above embodiment in that the third sub-grid line 130 includes a plurality of first conductive points 133 arranged at intervals along the first direction X, and the first conductive points 133 do not overlap with the first sub-grid line 110 or at least part of the first conductive points 133 overlap with the first sub-grid line 110. In the embodiment of the invention, by adopting a plurality of first conductive points 133, the collecting points can be flexibly set in the orthographic projection area of the first main grid line 140, and the use amount of conductive paste is further reduced while the carrier collecting uniformity is improved, so that the manufacturing cost is reduced. In addition, the first conductive points 133 with multiple points can also provide stress relief for the first main grid line 140, so as to avoid the problem of hidden cracking caused by the difference of thermal expansion coefficients and enhance the mechanical stability of the battery. In other embodiments of the present invention, according to the width of the first main gate line 140 in the second direction Y, a plurality of columns of the first conductive dots 133 may be disposed in parallel in the second direction Y to form a third array of sub gate lines 130 arranged in parallel. For example, when the first main gate line 140 is wider, two or more columns of the first conductive dots 133 may be disposed to further improve the carrier collection density and uniformity of the coverage area of the first main gate line 140. In addition, the specific shape and size of the first conductive point 133 may be adjusted according to actual requirements. Common shapes include circular, square, triangular, or other geometric shapes, without limitation.

Fig. 5 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention, referring to fig. 5, the embodiment of the present invention is different from the above embodiment in that a third auxiliary grid line 130 extends along a second direction Y and is electrically connected to a first main grid line 140, and in combination with fig. 2, the third auxiliary grid line 130 can be regarded as a plurality of third auxiliary grid line segments 134 extending along the second direction Y, and the third auxiliary grid line segments 134 are arranged at intervals in the first direction X, so as to form a collection structure with a wide area in the orthographic projection area of the first main grid line 140. With this layout, each third sub-gate line segment 134 can cover a different width region of the first main gate line 140 in the second direction Y, effectively expanding the carrier collection range. The number, length, and spacing of the third sub-gate segments 134 in the first direction X may be flexibly adjusted according to the actual width of the first main gate line 140, the paste printing accuracy, and the carrier lateral diffusion length.

Optionally, in conjunction with fig. 1, the fourth sub-gate line 180 may intersect the second sub-gate line 120, and as an example, the fourth sub-gate line 180 may include at least one second continuous gate line 181 extending along the first direction X, where the second continuous gate line 181 intersects the second sub-gate line 120, that is, where the second continuous gate line 181 is a continuous line, and where the length of the second continuous gate line 181 is less than or equal to the length of the second main gate line 180 in the first direction X, that is, the length dimension of the second continuous gate line 181 may be adapted to the length dimension of the second main gate line 170, so that the area below the entire second main gate line 170 may be collected. In the embodiment of the present invention, a second continuous gate line 181 is exemplarily shown in a position corresponding to the second main gate line 170, and in other embodiments, a plurality of second continuous gate lines 181 may be disposed in parallel in the second direction Y according to the width of the second main gate line 170 in the second direction Y, so as to form a fourth array of auxiliary gate lines 180 arranged in parallel, so as to further improve the carrier collection density and uniformity of the coverage area of the second main gate line 170.

Fig. 6-7 are schematic partial structures of a solar cell according to another embodiment of the present invention, and referring to fig. 6 and 7, the difference between the embodiment of the present invention and the above embodiment is that the fourth sub-gate line 180 may include a plurality of second sub-gate line segments 182 arranged at intervals along the first direction X, and the spatial relationship between the second sub-gate line segments 182 and the second sub-gate line 120 may be flexibly configured to achieve both carrier collection efficiency and material cost.

As shown in fig. 6, the second sub-gate line segment 182 may not intersect the second sub-gate line 120, that is, the second sub-gate line segment 182 is located between the adjacent second sub-gate lines 120 in the first direction X. As shown in fig. 7, at least a portion of the second sub-gate line segment 182 may intersect the second sub-gate line 120, and the intersecting structure may form a low-resistance current path, so as to facilitate rapid collection of the carriers collected by the second sub-gate line segment 182 into the second sub-gate line 120, thereby reducing the local bus resistance and improving the current collection efficiency.

In the embodiment of the present invention, by adopting the second sub-gate segments 182 arranged in multiple segments at intervals, the usage amount of the conductive paste, such as silver paste, can be significantly reduced and the manufacturing cost can be reduced on the premise of ensuring the uniformity of collecting the carriers in the orthographic projection area of the second main gate line 170. Meanwhile, the length, width and spacing of the line segments can be optimally designed according to the geometric dimension, doping distribution and carrier diffusion length of the main grid line, so that the optimal balance of performance and cost is realized. In the embodiment of the present invention, a row of second sub-gate segments 182 are exemplarily shown to be disposed at positions corresponding to the second main gate line 170, and in other embodiments, a plurality of second sub-gate segments 182 may be disposed in parallel in the second direction Y according to the width of the second main gate line 170 in the second direction Y, so as to form a fourth array of sub-gate lines 180 disposed in parallel, so as to further improve the carrier collection density and uniformity of the coverage area of the second main gate line 170.

Fig. 8 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention, referring to fig. 8, the fourth sub-grid line 180 may further include a plurality of second conductive points 183 arranged at intervals along the first direction X, where the second conductive points 183 do not overlap the second sub-grid line 120 or at least part of the second conductive points 183 overlap the second sub-grid line 120. In the embodiment of the invention, by adopting the plurality of second conductive points 183, the collecting points can be flexibly set in the orthographic projection area of the second main grid line 170, and the use amount of conductive paste is further reduced while the carrier collecting uniformity is improved, so that the manufacturing cost is reduced. In addition, the second conductive points 183 with multiple points can provide stress relief for the second main grid line 170, so as to avoid the problem of hidden cracking caused by the difference of thermal expansion coefficients and enhance the mechanical stability of the battery. In other embodiments of the present invention, a plurality of columns of second conductive dots 183 may be disposed in parallel in the second direction Y according to the width of the second main gate line 170 in the second direction Y, to form a fourth array of sub-gate lines 180 arranged in parallel. For example, when the second main gate line 170 is wider, two or more columns of the second conductive dots 183 may be disposed to further improve the carrier collection density and uniformity of the coverage area of the second main gate line 170. In addition, the specific shape and size of the second conductive dots 183 may be adjusted according to actual needs. Common shapes include circular, square, triangular, or other geometric shapes, without limitation.

Fig. 9 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention, which is different from the above embodiment in that the fourth sub-grid line 180 may further extend along the second direction Y and be electrically connected to the second main grid line 170, the fourth sub-grid line 180 includes a plurality of fourth sub-grid line segments 184 extending along the second direction Y, and the fourth sub-grid line segments 184 are arranged at intervals in the first direction X, so as to form a collection structure with a width region in the orthographic projection region of the second main grid line 170. With this layout, each fourth sub-gate line segment 184 can cover a different width region of the second main gate line 170 in the second direction Y, effectively expanding the carrier collection range. The number, length, and spacing of the fourth sub-gate segments 184 in the first direction X can be flexibly adjusted according to the actual width of the second main gate line 170, the paste printing accuracy, and the carrier lateral diffusion length.

Fig. 10 is a schematic view of a partial structure of another solar cell according to an embodiment of the present invention, in which a first doped layer 150 and a second doped layer 160 are disposed on a substrate 1. First doped layer 150 and second doped layer 160 have different conductivity types, and illustratively, in one embodiment of the present invention, first doped layer 150 may be N-type doped and second doped layer 160 may be P-type doped. The first doped layer 150 includes a first doped sub-region 151 extending in the second direction Y, and the second doped layer 160 includes a second doped sub-region 161 extending in the second direction Y. The first doped subregions 151 and the second doped subregions 161 are alternately arranged in the first direction X, the first doped subregions 151 continuously extend below the first main gate line 140, and the second doped subregions 161 are interrupted at the position of the first main gate line 140, so that only one conductive type continuous doped region exists below the first main gate line 140, the recombination loss of carriers with different polarities in the same region is avoided, and the current collection efficiency is improved.

Further, a passivation layer is typically further disposed on the substrate 1, and may cover the entire back surface of the substrate, as well as the first doped layer 150 and the second doped layer 160, to reduce the carrier recombination rate at the semiconductor surface. The orthographic projection of the first auxiliary grid line 110 on the substrate 1 is completely located in the orthographic projection of the first doped subarea 151, and the first auxiliary grid line 110 penetrates through the passivation layer and forms ohmic contact connection with the first doped area, so as to collect electrons generated by the N-type area and ensure efficient electron collection. Similarly, the orthographic projection of the second sub-gate line 120 on the substrate is completely located in the orthographic projection of the second doped sub-region 161, and the second sub-gate line 120 penetrates through the passivation layer and forms ohmic contact connection with the second doped region, so as to collect holes generated in the P-type region and ensure efficient hole collection.

Optionally, the first doped layer 150 includes a third doped sub-region 152, where the width of the third doped sub-region is greater than the width of the first main gate line along the second direction Y, the orthographic projection of the third auxiliary gate line 130 on the substrate 1 is located in the orthographic projection of the third doped sub-region 152 on the substrate 1, and the third auxiliary gate line 130 penetrates through the passivation layer and forms ohmic contact connection with the third doped region, so as to collect electrons generated in the N-type region and ensure efficient electron collection. That is, the third sub-gate line 130 is also aligned with the third doped region to achieve efficient extraction of photogenerated carriers within the coverage area of the first main gate line 140. For example, when the third sub-gate line 130 is a continuous sub-gate line extending along the first direction X, the orthographic projection thereof is completely included in the orthographic projection region of the first main gate line 140 and forms an ohmic contact with the third doped sub-region 152, so as to further reduce the carrier diffusion path and improve the overall conversion efficiency.

Optionally, the second doped layer 160 includes a fourth doped sub-region 162, and along the second direction Y, the width of the fourth doped sub-region 162 is greater than the width of the second main gate line 170, the orthographic projection of the fourth sub-gate line 180 on the substrate 1 is located in the orthographic projection of the fourth doped sub-region 162 on the substrate 1, and the fourth sub-gate line 180 penetrates through the passivation layer and forms ohmic contact connection with the fourth doped region, so as to collect holes generated in the P-type region, and ensure efficient hole collection. That is, the fourth sub-gate line 180 is also aligned with the fourth doped region to achieve efficient extraction of photogenerated carriers within the coverage area of the second main gate line 170. For example, when the fourth sub-gate line 180 is a continuous sub-gate line extending along the first direction X, the orthographic projection thereof is completely included in the orthographic projection region of the second main gate line 170 and forms an ohmic contact with the fourth doped sub-region 162, so as to further reduce the carrier diffusion path and improve the overall conversion efficiency.

Optionally, the third sub-gate line 130 is located at a side of the first main gate line 140 close to the substrate 1 or distant from the substrate 1, and/or,

The fourth sub-gate line 180 is located at a side of the second main gate line 170 close to the substrate 1 or remote from the substrate 1.

Specifically, in the manufacturing process, the interlayer positional relationship between the third sub-gate line 130 and the first main gate line 140 and the interlayer positional relationship between the fourth sub-gate line 180 and the second main gate line 170 may be flexibly controlled according to the printing order. For example, in the manufacturing process, the third sub-gate line 130 may be printed first and then the first main gate line 140 may be printed, so that the third sub-gate line 130 is structurally located at a side of the first main gate line 140 near the substrate 1. It is also possible to print the first main gate line 140 first and then print the third sub gate line 130, so that the third sub gate line 130 is structurally located at a side of the first main gate line 140 away from the substrate 1. The third thin gate line is electrically connected to the first main gate line 140, and forms an ohmic contact connection with the third doped region by co-sintering the third thin gate line to form a conductive path.

Accordingly, the fourth sub-gate line 180 may be printed first and then the second main gate line 170 may be printed, so that the fourth sub-gate line 180 is structurally located at a side of the second main gate line 170 near the substrate 1. The second main gate line 170 may be printed first and then the fourth sub gate line 180 may be printed, so that the fourth sub gate line 180 is structurally located at a side of the second main gate line 170 away from the substrate 1. The fourth thin gate line is electrically connected to the second main gate line 170, and forms an ohmic contact connection with the fourth doped region by co-sintering the fourth thin gate line to form a conductive path.

Further, the first sub-gate line 110, the second sub-gate line 120, the third sub-gate line 130 and the fourth sub-gate line 180 are arranged in the same layer, so that the third sub-gate line 130 and the fourth sub-gate line 180 can be prepared simultaneously with the first sub-gate line 110 and the second sub-gate line 120 by adopting the same screen printing process, no additional printing machine, mask or process step is required, and therefore, the manufacturing cost is not increased significantly. The design not only improves the process compatibility, but also ensures good alignment precision between the auxiliary grid lines.

The embodiment of the invention also provides a battery assembly, which comprises the solar battery of any embodiment of the invention. In the embodiment of the invention, a plurality of solar cells in the battery assembly can be connected in series to form a plurality of cell strings, each cell string can be connected in series, in parallel or after being combined in series and parallel to realize the current converging output, for example, the connection between each cell sheet can be realized by welding a welding strip, and the connection between each cell string can be realized by a bus bar. In some embodiments, the individual strings of cells may be assembled into an array of cells, which are then packaged together by a front plate, a front adhesive film, a rear adhesive film, and a back plate to form a battery assembly.

It should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to the above-mentioned embodiments, it should be understood by those skilled in the art that the technical solution described in the above-mentioned embodiments may be modified or some technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solution of the embodiments of the present invention.

Claims

1. A solar cell, characterized in that it comprises:

substrate;

A first sub-gate line and a second sub-gate line are disposed on the substrate, wherein the first sub-gate line and the second sub-gate line extend along a second direction and are alternately arranged in a first direction; the first direction intersects the second direction;

The first main grid line extends along the first direction, connects to the first sub-grid line, and is spaced apart from the second sub-grid line;

The second main grid line extends along the first direction, connects to the second sub-grid line, and is spaced apart from the first sub-grid line;

A third sub-gate line, the orthographic projection of the third sub-gate line on the substrate is located within the orthographic projection of the first main gate line on the substrate, and is electrically connected to the first main gate line; and/or, a fourth sub-gate line, the orthographic projection of the fourth sub-gate line on the substrate is located within the orthographic projection of the second main gate line on the substrate, and is electrically connected to the second main gate line.

2. The solar cell according to claim 1, wherein the third sub-grid line includes at least one first continuous grid line extending along the first direction; the first continuous grid line intersects with the first sub-grid line;

And/or, the fourth sub-gate line includes at least one second continuous gate line extending along the first direction; the second continuous gate line intersects with the second sub-gate line.

3. The solar cell according to claim 2, wherein, along the first direction, the length of the first continuous grid line is less than or equal to the length of the first main grid line;

And/or, the length of the second continuous gate line is less than or equal to the length of the second main gate line.

4. The solar cell according to claim 2, wherein the third sub-grid line comprises a plurality of first sub-grid line segments arranged at intervals along the first direction; the first sub-grid line segments do not intersect with the first sub-grid line or at least some of the first sub-grid line segments intersect with the first sub-grid line;

And/or, the fourth sub-gate line includes a plurality of second sub-gate line segments spaced apart along the first direction; the second sub-gate line segments do not intersect with the second sub-gate line or at least some of the second sub-gate line segments intersect with the second sub-gate line.

5. The solar cell according to claim 2, wherein the third sub-grid line comprises a plurality of first conductive points arranged at intervals along the first direction; the first conductive points do not overlap with the first sub-grid line or at least some of the first conductive points overlap with the first sub-grid line;

And/or, the fourth sub-gate line includes a plurality of second conductive points spaced apart along the first direction; the second conductive points do not overlap with the second sub-gate line or at least some of the second conductive points overlap with the second sub-gate line.

6. The solar cell according to claim 2, wherein the third sub-grid line comprises a plurality of third sub-grid line segments extending along the second direction, the third sub-grid line segments being spaced apart in the first direction;

And/or, the fourth sub-gate line includes a plurality of fourth sub-gate line segments extending along the second direction, the fourth sub-gate line segments being spaced apart in the first direction.

7. The solar cell according to any one of claims 1-6, wherein the third sub-grid line is located on the side of the first main grid line that is close to or far from the substrate;

And/or, the fourth sub-gate line is located on the side of the second main gate line that is close to or away from the substrate.

8. The solar cell according to claim 2, wherein the first sub-grid line, the second sub-grid line, the third sub-grid line and the fourth sub-grid line are arranged in the same layer.

9. The solar cell according to claim 1, wherein the substrate comprises a first doped layer and a second doped layer, the first doped layer comprises a first doped sub-region extending along a second direction, the second doped layer comprises a second doped sub-region extending along a second direction, and the first doped sub-region and the second doped sub-region are alternately arranged along the first direction;

The first doped sub-region extends continuously at the first main gate line, and the second doped sub-region is interrupted at the first main gate line; the second doped sub-region extends continuously at the second main gate line, and the first doped sub-region is interrupted at the second main gate line.

The orthographic projection of the first sub-gate line on the substrate lies within the orthographic projection of the first doped sub-region on the substrate, and the first sub-gate line is electrically connected to the first doped sub-region; the orthographic projection of the second sub-gate line on the substrate lies within the orthographic projection of the second doped sub-region on the substrate, and the second sub-gate line is electrically connected to the second doped sub-region; the first doped layer and the second doped layer have different conductivity types;

The first doped layer includes a third doped sub-region, the width of which is greater than the width of the first main gate line along the second direction; the orthographic projection of the third sub-gate line on the substrate lies within the orthographic projection of the third doped sub-region on the substrate; the third sub-gate line is electrically connected to the third doped sub-region; and or, the second doped layer includes a fourth doped sub-region, the width of which is greater than the width of the second main gate line along the second direction; the orthographic projection of the fourth sub-gate line on the substrate lies within the orthographic projection of the fourth doped sub-region on the substrate; the fourth sub-gate line is electrically connected to the fourth doped sub-region.

10. A battery assembly, characterized in that it comprises the solar cell according to any one of claims 1-9.