CN1265509B - 存储器中的可编程延迟控制 - Google Patents

存储器中的可编程延迟控制 Download PDF

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Publication number
CN1265509B
CN1265509B CN99123118XA CN99123118A CN1265509B CN 1265509 B CN1265509 B CN 1265509B CN 99123118X A CN99123118X A CN 99123118XA CN 99123118 A CN99123118 A CN 99123118A CN 1265509 B CN1265509 B CN 1265509B
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CN
China
Prior art keywords
circuit
delay
output terminal
data line
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN99123118XA
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English (en)
Chinese (zh)
Other versions
CN1265509A (zh
Inventor
雷·张
威廉·R·威尔
理查德·Y·王
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Vlsi Technology Co ltd
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Freescale Semiconductor Inc
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Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1265509A publication Critical patent/CN1265509A/zh
Application granted granted Critical
Publication of CN1265509B publication Critical patent/CN1265509B/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
CN99123118XA 1999-03-01 1999-10-21 存储器中的可编程延迟控制 Expired - Lifetime CN1265509B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/259,454 1999-03-01
US09/259,454 US6111796A (en) 1999-03-01 1999-03-01 Programmable delay control for sense amplifiers in a memory

Publications (2)

Publication Number Publication Date
CN1265509A CN1265509A (zh) 2000-09-06
CN1265509B true CN1265509B (zh) 2010-10-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN99123118XA Expired - Lifetime CN1265509B (zh) 1999-03-01 1999-10-21 存储器中的可编程延迟控制

Country Status (8)

Country Link
US (2) US6111796A (fr)
EP (3) EP1770710B1 (fr)
JP (2) JP4445074B2 (fr)
KR (1) KR100665484B1 (fr)
CN (1) CN1265509B (fr)
DE (1) DE69942354D1 (fr)
SG (2) SG100732A1 (fr)
TW (1) TW440869B (fr)

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US6947608B2 (en) * 2002-01-25 2005-09-20 Kabushiki Kaisha Toshiba Equalizing circuit and method, and image processing circuit and method
US6762961B2 (en) * 2002-04-16 2004-07-13 Sun Microsystems, Inc. Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier
US7080275B2 (en) * 2002-08-12 2006-07-18 Micron Technology, Inc. Method and apparatus using parasitic capacitance for synchronizing signals a device
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US7020035B1 (en) 2003-10-10 2006-03-28 Sun Microsystems, Inc. Measuring and correcting sense amplifier and memory mismatches using NBTI
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US7164612B1 (en) 2003-10-10 2007-01-16 Sun Microsystems, Inc. Test circuit for measuring sense amplifier and memory mismatches
US6914467B2 (en) * 2003-12-04 2005-07-05 International Business Machines Corporation Dual edge programmable delay unit
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WO2005106667A2 (fr) * 2004-04-29 2005-11-10 Koninklijke Philips Electronics N.V. Correction d'erreur dans un circuit electronique
US6958943B1 (en) 2004-05-12 2005-10-25 International Business Machines Corporation Programmable sense amplifier timing generator
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US7157952B2 (en) * 2004-08-20 2007-01-02 L-3 Integrated Systems Company Systems and methods for implementing delay line circuitry
EP1630815B1 (fr) * 2004-08-24 2011-10-05 Infineon Technologies AG Dispositif de memoire a la flexibilite en relation a la tension d'alimentation et avec un rendement adapte a la tension d'alimentation
KR100613073B1 (ko) 2004-09-21 2006-08-16 주식회사 하이닉스반도체 센스 앰프 오버드라이브 회로
KR100609621B1 (ko) 2005-07-19 2006-08-08 삼성전자주식회사 메모리 블락별로 레이턴시 제어가 가능한 동기식 반도체메모리 장치
US7215585B2 (en) * 2005-09-01 2007-05-08 Micron Technology, Inc. Method and apparatus for synchronizing data from memory arrays
US7158432B1 (en) * 2005-09-01 2007-01-02 Freescale Semiconductor, Inc. Memory with robust data sensing and method for sensing data
US8077533B2 (en) 2006-01-23 2011-12-13 Freescale Semiconductor, Inc. Memory and method for sensing data in a memory using complementary sensing scheme
US7339842B1 (en) * 2006-08-16 2008-03-04 Arm Limited Timing control for sense amplifiers in a memory circuit
KR100761381B1 (ko) * 2006-09-06 2007-09-27 주식회사 하이닉스반도체 비트라인 센스앰프 미스매치판단이 가능한 메모리장치.
KR100824779B1 (ko) * 2007-01-11 2008-04-24 삼성전자주식회사 반도체 메모리 장치의 데이터 출력 경로 및 데이터 출력방법
KR100889311B1 (ko) * 2007-02-23 2009-03-18 주식회사 하이닉스반도체 비트라인 감지증폭기를 포함하는 반도체메모리소자
JP5102800B2 (ja) 2009-04-15 2012-12-19 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体記憶装置
KR20110025487A (ko) * 2009-09-04 2011-03-10 삼성전자주식회사 반도체 메모리 장치
JP5471761B2 (ja) * 2010-04-15 2014-04-16 富士通株式会社 受信回路
US9201096B2 (en) 2010-09-08 2015-12-01 Dcg Systems, Inc. Laser-assisted device alteration using synchronized laser pulses
JP5579580B2 (ja) * 2010-11-12 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
US8400852B2 (en) * 2011-03-04 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit with remote amplifier
US8467254B2 (en) * 2011-09-25 2013-06-18 Nanya Technology Corporation Memory apparatus
US8879303B2 (en) * 2013-01-03 2014-11-04 Lsi Corporation Pre-charge tracking of global read lines in high speed SRAM
US11209985B2 (en) * 2019-04-23 2021-12-28 Macronix International Co., Ltd. Input/output delay optimization method, electronic system and memory device using the same
CN112069768B (zh) * 2020-09-08 2024-07-16 飞腾信息技术有限公司 一种针对双端口sram输入输出延时优化的方法
KR102692866B1 (ko) * 2021-04-26 2024-08-08 한국전자통신연구원 컴퓨팅 자원 분할 운용 방법 및 장치
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Also Published As

Publication number Publication date
SG100732A1 (en) 2003-12-26
KR100665484B1 (ko) 2007-01-10
US6111796A (en) 2000-08-29
EP1033721A2 (fr) 2000-09-06
JP4903847B2 (ja) 2012-03-28
EP1033721B1 (fr) 2017-03-15
TW440869B (en) 2001-06-16
EP1770710A2 (fr) 2007-04-04
US6385101B1 (en) 2002-05-07
KR20000062133A (ko) 2000-10-25
EP1770710A3 (fr) 2007-07-04
EP1770710B1 (fr) 2010-05-05
JP2000251472A (ja) 2000-09-14
SG103248A1 (en) 2004-04-29
EP1770708A2 (fr) 2007-04-04
EP1770708A3 (fr) 2007-07-04
EP1770708B1 (fr) 2012-11-14
DE69942354D1 (de) 2010-06-17
CN1265509A (zh) 2000-09-06
JP2010003406A (ja) 2010-01-07
EP1033721A3 (fr) 2000-10-25
JP4445074B2 (ja) 2010-04-07

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