CN1268770A - 形成半导体器件的工艺过程 - Google Patents

形成半导体器件的工艺过程 Download PDF

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Publication number
CN1268770A
CN1268770A CN00104671A CN00104671A CN1268770A CN 1268770 A CN1268770 A CN 1268770A CN 00104671 A CN00104671 A CN 00104671A CN 00104671 A CN00104671 A CN 00104671A CN 1268770 A CN1268770 A CN 1268770A
Authority
CN
China
Prior art keywords
etching
layer
stack
forming
height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN00104671A
Other languages
English (en)
Chinese (zh)
Inventor
张海雷
李勇杰·汤姆
菲乌米·恩古延
穆萨米·布特
吴伟·艾德温
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of CN1268770A publication Critical patent/CN1268770A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Landscapes

  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN00104671A 1999-03-25 2000-03-24 形成半导体器件的工艺过程 Pending CN1268770A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27626999A 1999-03-25 1999-03-25
US09/276,269 1999-03-25

Publications (1)

Publication Number Publication Date
CN1268770A true CN1268770A (zh) 2000-10-04

Family

ID=23055947

Family Applications (1)

Application Number Title Priority Date Filing Date
CN00104671A Pending CN1268770A (zh) 1999-03-25 2000-03-24 形成半导体器件的工艺过程

Country Status (4)

Country Link
JP (1) JP2000294546A (ja)
KR (1) KR20010006864A (ja)
CN (1) CN1268770A (ja)
TW (1) TW449864B (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7339230B2 (en) * 2006-01-09 2008-03-04 International Business Machines Corporation Structure and method for making high density mosfet circuits with different height contact lines

Also Published As

Publication number Publication date
KR20010006864A (ko) 2001-01-26
TW449864B (en) 2001-08-11
JP2000294546A (ja) 2000-10-20

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Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication