CN1468396A - 并行计数器和用于执行乘法的逻辑电路 - Google Patents

并行计数器和用于执行乘法的逻辑电路 Download PDF

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Publication number
CN1468396A
CN1468396A CNA018169287A CN01816928A CN1468396A CN 1468396 A CN1468396 A CN 1468396A CN A018169287 A CNA018169287 A CN A018169287A CN 01816928 A CN01816928 A CN 01816928A CN 1468396 A CN1468396 A CN 1468396A
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CN
China
Prior art keywords
scale
output
logical
logic
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA018169287A
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English (en)
Chinese (zh)
Inventor
德文特里・鲁梅宁
德文特里·鲁梅宁
・塔瓦尔
苏尼尔·塔瓦尔
默历曼斯
彼得·默历曼斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Automatic Parallel Designs Ltd
Original Assignee
Automatic Parallel Designs Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0019287A external-priority patent/GB2365636B/en
Application filed by Automatic Parallel Designs Ltd filed Critical Automatic Parallel Designs Ltd
Publication of CN1468396A publication Critical patent/CN1468396A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
CNA018169287A 2000-08-04 2001-07-27 并行计数器和用于执行乘法的逻辑电路 Pending CN1468396A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0019287A GB2365636B (en) 2000-08-04 2000-08-04 A parallel counter and a multiplication logic circuit
GB0019287.2 2000-08-04
GB0101961.1 2001-01-25
GB0101961A GB2365637B (en) 2000-08-04 2001-01-25 A parallel counter and a multiplication logic circuit

Publications (1)

Publication Number Publication Date
CN1468396A true CN1468396A (zh) 2004-01-14

Family

ID=26244799

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA018169287A Pending CN1468396A (zh) 2000-08-04 2001-07-27 并行计数器和用于执行乘法的逻辑电路

Country Status (5)

Country Link
EP (1) EP1307812A2 (fr)
JP (1) JP2004506260A (fr)
CN (1) CN1468396A (fr)
AU (1) AU2002229155A1 (fr)
WO (1) WO2002012995A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101091157B (zh) * 2004-07-12 2010-09-01 哈利尔·基利克 用于处理数字数据的数字处理器和方法
CN112068802A (zh) * 2020-08-14 2020-12-11 清华大学 计数器的设计方法、装置及计数器

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7136888B2 (en) 2000-08-04 2006-11-14 Arithmatica Limited Parallel counter and a logic circuit for performing multiplication
WO2003034200A1 (fr) * 2000-08-11 2003-04-24 Arithmatica Limited Compteur parallele et circuit logique executant une multiplication
GB2365636B (en) 2000-08-04 2005-01-05 Automatic Parallel Designs Ltd A parallel counter and a multiplication logic circuit
US6883011B2 (en) 2000-08-04 2005-04-19 Arithmatica Limited Parallel counter and a multiplication logic circuit
GB2373602B (en) 2001-03-22 2004-11-17 Automatic Parallel Designs Ltd A multiplication logic circuit
US7260595B2 (en) 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
US6909767B2 (en) 2003-01-14 2005-06-21 Arithmatica Limited Logic circuit
US7042246B2 (en) 2003-02-11 2006-05-09 Arithmatica Limited Logic circuits for performing threshold functions
US7308471B2 (en) 2003-03-28 2007-12-11 Arithmatica Limited Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
US7170317B2 (en) 2003-05-23 2007-01-30 Arithmatica Limited Sum bit generation circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3634658A (en) * 1970-03-19 1972-01-11 Sperry Rand Corp Parallel bit counter
US3757098A (en) * 1972-05-12 1973-09-04 Rca Corp Carry generation means for multiple character adder
US4703435A (en) * 1984-07-16 1987-10-27 International Business Machines Corporation Logic Synthesizer
JP2506991B2 (ja) * 1987-09-25 1996-06-12 松下電器産業株式会社 回路変換システムと回路変換方法と反転論理生成方法および論理設計システム
US5175862A (en) * 1989-12-29 1992-12-29 Supercomputer Systems Limited Partnership Method and apparatus for a special purpose arithmetic boolean unit
US5524082A (en) * 1991-06-28 1996-06-04 International Business Machines Corporation Redundancy removal using quasi-algebraic methods
US6023566A (en) * 1997-04-14 2000-02-08 Cadence Design Systems Cluster matching for circuit implementation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101091157B (zh) * 2004-07-12 2010-09-01 哈利尔·基利克 用于处理数字数据的数字处理器和方法
CN112068802A (zh) * 2020-08-14 2020-12-11 清华大学 计数器的设计方法、装置及计数器
CN112068802B (zh) * 2020-08-14 2022-11-11 清华大学 计数器的设计方法、装置及计数器

Also Published As

Publication number Publication date
WO2002012995A2 (fr) 2002-02-14
JP2004506260A (ja) 2004-02-26
WO2002012995A3 (fr) 2003-03-13
AU2002229155A1 (en) 2002-02-18
EP1307812A2 (fr) 2003-05-07

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