CN1521950A - Phase error compensation apparatus for synchronous phase lock loop jitter apparatus and its using method - Google Patents
Phase error compensation apparatus for synchronous phase lock loop jitter apparatus and its using method Download PDFInfo
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Abstract
The invention relates to phase error compensation arrangement for shake phase synchronization phase-locked loop and method for using, wherein when the dither signal for converting analog to digital A/D checks wave phase error on the crossing point of positive, negative and zero PZCP, the shake phase synchronization phase-locked loop uses the separate phase error compensator on the crossing point for separate parallel moment phase error compensation. The function of the shake phase synchronization phase-locked loop is to change the duty ratio of the dither signal, thus preventing the gradual failure of the shake phase synchronization phase-locked loop.
Description
(1) technical field
The invention relates to and be recordable CD, the data record of optical recording medias such as DVD or the method for reproduction are especially instigated the recording frequency of synchronous phase-locked loop generation output or are reproduced Frequency Synchronization in the phase error compensation device and the using method of a kind of synchronous phase-locked loop jittering device of the dither signal of reading from optical recording media.
(2) background technology
At first, Fig. 1 is the formation schematic diagram of the existing shake Phase synchronization phase-locked loop of diagram, and above-mentioned shake Phase synchronization phase-locked loop 100 comprises phase detector 12, loop filter 13 and numerically-controlled oscillator (DCO) 14.
In addition, the dither signal of reading from recordable optical recording medias such as DVD-RW is as push-pull signal, filtered by pass filter (BPF) 10, and after eliminating High-frequency Interference, dc offset undesirable constituentss such as (offset), be converted into digital signal by A/D converter (ADC) 11 simulations.
In addition, in the phase detector 12 of above-mentioned shake Phase synchronization phase-locked loop 100, after the dither signal of above-mentioned A/D conversion cut by the preset standard level, generate also output as the illustrated rectangular-shaped dither signal of Fig. 2.In addition, after the phase-locked loop PLL impulse wave of output is compared with the phase error of simulating the dither signal that is converted into numeral and calculated from above-mentioned numerically-controlled oscillator 14, output to above-mentioned loop filter 13.
In addition, above-mentioned loop filter 13 generates the phase compensation value to above-mentioned numerically-controlled oscillator 14 phase-locked loop PLL impulse waves based on the phase error of above-mentioned phase detector 12 outputs.Above-mentioned loop filter is carried out the effect of a kind of low territory by filter LPF, makes from the PLL impulse wave of above-mentioned numerically-controlled oscillator 14 outputs to be synchronized with above-mentioned dither signal.
In addition, above-mentioned digital oscillating controller compensates the frequency of oscillation of present PLL impulse wave according to the phase compensation value that generates and export in the above-mentioned loop filter 13, thereby generates and export the PLL impulse wave that is synchronized with dither signal.
In addition, generate the PLL impulse wave of exporting according to the shake Phase synchronization phase-locked loop 100 that constitutes as mentioned above and move and be input to the additional bit wave detector 15 that has above-mentioned simulation to be converted into the dither signal of numeral.And above-mentioned bit wave detector 15 to utilize the PLL impulse wave that simulation is converted into the dither signal detection of numeral and is converted into value be 0 or 1 bit stream (BIT STREAM).
In addition, be carried in synchronous detector 16 generations and the output and the corresponding synchronizing signal of its synchronous images of the synchronous images (pattern) of dither signal from above-mentioned bit stream detection.In addition, from the bit stream of above-mentioned bit wave detector 15, the address decoder 17 of decoding optical recording media actual address is to decode in the basis with the synchronizing signal of above-mentioned synchronous detector, and the actual address of optical recording media is outputed to main locking phase phase-locked loop 300.
In addition, the phase detector 12 of aforesaid shake Phase synchronization phase-locked loop is described the same as Fig. 3, and the dither signal of changing at A/D is (NZCP) detection phase error during from just (positive) to negative (negative) zero crossings.Determine the time counting value of above-mentioned numerically-controlled oscillator 14 vibration frequencies, for example freely reduce (free down) time counting value, can be recompensed all the time by the phase error of above-mentioned NZCP initial point detection.
At this moment, the PLL impulse wave phase place that generates in above-mentioned numerically-controlled oscillator 14 is than when analog-converted shifts to an earlier date for the dither signal ripple of numeral, in the detection and just generate (positive) phase error and output to loop filter 13 as shown in Figure 3 of above-mentioned phase detector 12.In the above-mentioned loop filter according to the count value of a spot of compensation of above-mentioned just (positive) phase error decision numerically-controlled oscillator 14 frequencies.
In addition, when the phase place of the PLL impulse wave that generates in above-mentioned numerically-controlled oscillator 14 be the dither signal phase lag of numeral than analog-converted, the detection and generate and bear (negative) phase error and output to above-mentioned loop filter 13 as shown in Figure 3 of above-mentioned phase detector 12; In above-mentioned loop filter, the time counting value of decision numerically-controlled oscillator 14 frequencies is carried out the compensation of big amount according to above-mentioned negative phase error value.
Then, above-mentioned shake Phase synchronization phase-locked loop 100 is at above-mentioned NZCP initial point detection phase error, and the time counting value of the above-mentioned numerically-controlled oscillator frequency of compensation decision makes to continuing to make the PLL impulse wave be synchronized with the action of dither signal phase error compensation.
But analog-converted can change according to the duty ratio of the dither signal of above-mentioned section from the initial point that just intersecting to negative zero point to some extent for the dither signal of numeral as mentioned above.Change because the duty ratio of dither signal can be according to the characteristic of BPF, cut shape flat, dither signal, so with the NZCP initial point is standard when shaking the action of Phase synchronization phase-locked loop, because the characteristic of BPF, cut the problem that the timing jitter degradation failure of shake Phase synchronization phase-locked loop appears in reasons such as shape flat, dither signal.
In addition, forming the correct required times of phase error compensation at above-mentioned shake Phase synchronization phase-locked loop 100 is because of the loop filter characteristic changes, and the problem that phase error compensation work can not instantaneous time be finished therefore can occur.
Also have, above-mentioned dither signal is when discontinuous reading, for example dither signal is not read out within a certain period of time, when reading dither signal suddenly under interrupt jitter Phase synchronization phase-locked loop operating state, the problem of Phase synchronization phase-locked loop work can appear can't shaking rapidly for dither signal.
(3) summary of the invention
The present invention creates in order to address the above problem.To shake Phase synchronization phase-locked loop, for the dither signal that changes at A/D from just to the initial point detection phase error of negative zero point intersection, carry out the phase error compensation device and the using method of a kind of synchronous phase-locked loop jittering device of phase error compensation in its PZCP initial point moment.
The object of the present invention is achieved like this:
A kind of phase error compensation device of synchronous phase-locked loop jittering device, comprise: the dither signal of reading from the recordable optical recording media of DVD-RW, after the pass filter filtration, be converted into digital signal by the A/D converter simulation, via phase detector, the shake Phase synchronization phase-locked loop that loop filter and numerically-controlled oscillator are formed carries out phase error compensation and exports the PLL impulse wave, again through the bit stream wave detector, synchronous detector, the address decoder of decoding optical recording media actual address, the actual address of optical recording media is outputed to main locking phase phase-locked loop 300
Wherein said shake Phase synchronization phase-locked loop also comprises:
The output frequency PLL impulse wave Phase synchronization that takes place from described numerically-controlled oscillator in the phase error compensation device of described dither signal, according to the phase error between described PLL impulse wave and dither signal, the time counting value changes over the particular value of in advance setting in the frequency generating apparatus that described numerically-controlled oscillator produces.
A kind of using method of phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 1 comprises:
The 1st step: according to described numerically-controlled oscillator PLL impulse wave frequency plot is changed output, the frequency of above-mentioned output and analog-converted are compared for the phase error between the dither signal of numeral;
The 2nd step: generate the phase error that detection goes out according to described phase detector, the respective phase offset is synchronized with above-mentioned dither signal to the frequency plot PLL impulse wave of above-mentioned output and the phase error compensation method of the shake Phase synchronization phase-locked loop that forms;
According to the phase error between said frequencies and dither signal, other comprises the step that the time counting value of described decision said frequencies is provided with by the particular value conversion of setting in advance.
Effect of the present invention:
Phase error compensation device and using method with above-mentioned shake Phase synchronization phase-locked loop that constitutes and move, it mainly is on the PZCP initial point detection phase error and utilizes phase compensator independent parallel operation phase error instantaneous phase compensate function, so can prevent because of being subjected to the BPF characteristic, cut flatly, the duty ratio that the influence of dither signal shape changes dither signal prevents to shake the Phase synchronization phase-locked loop and regularly trembles progressively extinction tests.And can generate and read the PLL impulse wave that instantaneous time is synchronized with dither signal, in addition, dither signal can not be read within a certain period of time and be read suddenly under the state of interrupt jitter Phase synchronization phase-locked loop action
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Fig. 1 is the formation schematic diagram of the existing shake Phase synchronization phase-locked loop of diagram;
Fig. 2 is diagram is carried out the PLL impulse wave of phase error compensation according to existing shake Phase synchronization phase-locked loop an oscillogram schematic diagram;
Fig. 3 is the phase error of the existing shake Phase synchronization phase-locked loop of diagram, and the PLL pulse involves the time control data value schematic diagram of numerically-controlled oscillator;
Fig. 4 and Fig. 5 are the phase error compensation device of the relevant shake Phase synchronization phase-locked loop of the present invention of diagram and the formation and the schematic flow sheet of using method;
Fig. 6 and 7 is phase errors of the relevant shake Phase synchronization phase-locked loop of the present invention of diagram, and the PLL pulse involves the schematic diagram of the time control data value of numerically-controlled oscillator;
To be diagrams involve waveform schematic diagram to jittering characteristic according to the PLL pulse of relevant shake Phase synchronization phase-locked loop of the present invention institute phase compensation to Fig. 8 to 10.
Symbol description in the main accompanying drawing:
10: pass filter (BPF)
11: analog/digital converter (ADC)
12,22: phase detector (PHASE DETECTOR)
13,23: loop filter (LOOP FILTER)
14,24: numerically-controlled oscillator (DCO)
15: bit wave detector (BIT DETECTOR)
16: synchronous detector (SYNC DETECTOR)
17: address decoder (ADDRESS DECODER)
20: phase error compensation device (PHASE ERROR COMPENSATOR)
100,200: shake Phase synchronization phase-locked loop shake Phase synchronization phase-locked loop
300: main locking phase phase-locked loop (MAIN PLL)
(5) embodiment
Fig. 4 and Fig. 5 are diagrams according to the formation of the phase compensator of shake Phase synchronization phase-locked loop of the present invention and method and carry out the diagrammatic sketch of flow process that above-mentioned shake Phase synchronization phase-locked loop 200 comprises with reference to the described phase detector 22 of Fig. 1, loop filter 23, numerically-controlled oscillator 24 etc.Other is included as the phase error compensation device 20 of the phase error compensation of instantaneous time.
In addition, above-mentioned phase detector 22 is as illustrated in Fig. 6 and Fig. 7, analog-converted be the dither signal detection of numeral from negative (negative) to the zero crossings initial point of (positive) just, and the phase error of detection on its PZCP initial point.Determine the time counting value of the frequency of above-mentioned numerically-controlled oscillator 24, for example freely reduce (FREE DOWN) time counting value, according to the phase error of detection in above-mentioned PZCP initial point and the conversion compensation.
At this moment, when the PLL impulse wave phase-lead that generates in the numerically-controlled oscillator 24 be the phase place of digital dither signal in analog-converted, above-mentioned phase detector 22 the insides such as Fig. 6 illustrate detection and just generate that (positive) phase error outputs to loop filter 230, in the above-mentioned loop filter the time counting value of numerically-controlled oscillator 14, a spot of according to above-mentioned plus phase error value toward post-compensation, excute phase error compensation action on common shake Phase synchronization phase-locked loop, otherwise, among Fig. 7, when the situation of negative phase error, then, toward post-compensation.
The compensation operation rule of phase error compensation device:
S10 step: detect PZCD,, enter following S17 step if do not examine PZCD;
The S11 step: then tested in the above-mentioned phase error compensation device 20 as above-mentioned PZCP initial point, the acknowledging time count value CV in above-mentioned numerically-controlled oscillator DCO24 that phase error compensation work is relatively independent;
The S12 step: differentiate above-mentioned CV and whether surpass the maximum critical field of in advance setting;
S13 step: when above-mentioned CV surpasses maximum critical field, count value transformed mappings (Mapping) at present and be defaulted as set point Vset in advance, enter following S17 step in the numerically-controlled oscillator 24;
The S14 step: when the CV value of differentiating in the above-mentioned S12 step did not surpass the maximum critical field of in advance setting, whether the time counting value CV in the discriminating digit control generator 24 was included in maximum/minimum sandards scope of in advance setting;
The S15 step: above-mentioned CV value is in maximum/minimum sandards scope of in advance setting the time, time counting value among the numerically-controlled oscillator DCO24 change mapping (Mapping) and be defaulted as set point Vset in advance 1/2 promptly, carry out toward post-compensation (Backward Gap Compensator), enter following S17 step;
In addition, when the PLL impulse wave phase place that generates in the above-mentioned numerically-controlled oscillator 24 is the dither signal hysteresis of numeral than analog-converted, above-mentioned phase detector 22 detection generation negative phase error as shown in Figure 7 outputs to loop filter, and the time counting value of the numerically-controlled oscillator 24 in the above-mentioned loop filter is the regular event that excute phase error on the common property shake Phase synchronization phase-locked loop is guaranteed in big amount compensation according to the negative phase error value.
S16 step: in addition, above-mentioned phase error compensation device 20 is when detecting above-mentioned PZCP initial point, relatively independent with above-mentioned phase error compensation action, confirm the time counting value CV in the numerically-controlled oscillator, when exceeding predefined maximum/minimum sandards scope, for example, when not reaching the minimum sandards scope, above-mentioned numerically-controlled oscillator 24 is mapped as null value to present count value CV change, makes it can change over default value VSET at once;
S17 step: shake the PLL operation normally.
In addition, when the time counting value of above-mentioned numerically-controlled oscillator 24 is included in the minimum/maximum magnitude of prior setting the mapping of the time counting value transform of numerically-controlled oscillator 24 and be reduced into 1/2 of default value, that is, carry out the action of past precompensation (FORWARD GAP COMPENSATOR).
Shake Phase synchronization phase-locked loop 200 be not subjected to the BPF characteristic, cut flat, on the PZCP initial point of influence such as dither signal shape, detect phase error, illustrate as Fig. 8, the rectangle dither signal surpasses or during less than 50%, and the phase error detection cycle can be by the some cycles detection by corresponding to 50% duty ratio dither signal.So can prevent to shake the phenomenon that the timing jitter of Phase synchronization phase-locked loop progressively disappears.
In addition, according to shake Phase synchronization phase-locked loop 200 of the present invention, when being the normal phase bit error compensating movement on basis, carry out the instantaneous phase compensate function on the independent operating phase compensator 20 according to above-mentioned loop filter 23.Shown in Fig. 9 and 10, therefore better jittering characteristic and generation and output and the instantaneous synchronous PLL impulse wave of dither signal are arranged than existing shake Phase synchronization phase-locked loop 100 (shown in Figure 1).
In addition, shake Phase synchronization phase-locked loop 200 according to the present invention is in order to ensure the instantaneous phase error compensate function, during the discontinuous output of dither signal, also can form rapidly and operation shake Phase synchronization phase-locked loop function dither signal.
Those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (10)
1. the phase error compensation device of a synchronous phase-locked loop jittering device, comprise: the dither signal of reading from the recordable optical recording media of DVD-RW, after the pass filter filtration, be converted into digital signal by the A/D converter simulation, via phase detector, the shake Phase synchronization phase-locked loop that loop filter and numerically-controlled oscillator are formed carries out phase error compensation and exports the PLL impulse wave, again through the bit stream wave detector, synchronous detector, the address decoder of decoding optical recording media actual address, the actual address of optical recording media is outputed to main locking phase phase-locked loop 300
It is characterized in that described shake Phase synchronization phase-locked loop also comprises:
The output frequency PLL impulse wave Phase synchronization that takes place from described numerically-controlled oscillator in the phase error compensation device of described dither signal, according to the phase error between described PLL impulse wave and dither signal, the time counting value changes over the particular value of in advance setting in the frequency generating apparatus that described numerically-controlled oscillator produces.
2. the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 1, it is characterized in that described phase error compensation device is is relatively independent described numerically-controlled oscillator to be carried out the time counting value changes over the particular value of in advance setting in the frequency generating apparatus with described phase detector and loop filter, and carry out the phase compensation action with instantaneous time.
3. the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 1, it is characterized in that described phase error compensation device is the initial point of dither signal from just intersecting to negative zero point with described A/D conversion, when the time counting value that described numerically-controlled oscillator frequency takes place surpasses the maximum critical field that in advance configures, existing time counting value mapping change.
4. the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 1, it is characterized in that described phase error compensation device be with the dither signal of described A/D conversion from just to initial point that negative zero point intersects the time, when the time counting value that described numerically-controlled oscillator frequency takes place is included in the maximum that in advance configures/minimum sandards reference range, existing time counting value is shone upon change into 1/2 of default value.
5. the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 1, it is characterized in that described phase error compensation device be with the dither signal of described A/D conversion from just to initial point that negative zero point intersects the time, when the time counting value that described numerically-controlled oscillator frequency takes place does not reach the minimum sandards scope that in advance configures, existing time counting value mapping is changed into zero.
6. the using method of the phase error compensation device of a synchronous phase-locked loop jittering device as claimed in claim 1 is characterized in that comprising:
The 1st step: according to described numerically-controlled oscillator PLL impulse wave frequency plot is changed output, the frequency of above-mentioned output and analog-converted are compared for the phase error between the dither signal of numeral;
The 2nd step: generate the phase error that detection goes out according to described phase detector, the respective phase offset is synchronized with above-mentioned dither signal to the frequency plot PLL impulse wave of above-mentioned output and the phase error compensation method of the shake Phase synchronization phase-locked loop that forms;
According to the phase error between said frequencies and dither signal, other comprises the step that the time counting value of described decision said frequencies is provided with by the particular value conversion of setting in advance.
7. the using method of the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 6, the step that it is characterized in that described change and setting-up time count value is relatively independent with the 1st and the 2nd step, determine frequency time counting value, and it is changed over the phase compensation action that is set at particular value in advance and carries out phase place with instantaneous time.
8. the using method of the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 6, the step that it is characterized in that described change and setting-up time count value be with the dither signal of described A/D conversion from just to initial point that negative zero point intersects the time, when above-mentioned time counting value surpasses the maximum critical field in advance configure, existing time counting value shone upon change into default value.
9. the using method of the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 6, the step that it is characterized in that described change and setting-up time count value be with the dither signal of described A/D conversion from just to initial point that negative zero point intersects the time, when above-mentioned time counting value is included in the maximum that in advance configures/minimum sandards scope, 1/2 of default value is changed in existing time counting value mapping.
10. the using method of the phase error compensation device of synchronous phase-locked loop jittering device as claimed in claim 6, the step that it is characterized in that described change and setting-up time count value be with the dither signal of described A/D conversion from just to initial point that negative zero point intersects the time, when above-mentioned time counting value does not reach the minimum sandards scope that in advance configures, existing time counting value mapping is changed over zero.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA031151671A CN1521950A (en) | 2003-01-27 | 2003-01-27 | Phase error compensation apparatus for synchronous phase lock loop jitter apparatus and its using method |
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| CNA031151671A CN1521950A (en) | 2003-01-27 | 2003-01-27 | Phase error compensation apparatus for synchronous phase lock loop jitter apparatus and its using method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101051836B (en) * | 2007-03-30 | 2012-01-11 | 北京中星微电子有限公司 | Device and method for timed synchronous transmission stream decoding and coding |
| CN101414823B (en) * | 2007-10-16 | 2012-08-08 | 联发科技股份有限公司 | Error Compensation Method, Digital Phase Error Elimination Module and Full Digital Phase Locked Loop |
| CN109557602A (en) * | 2018-12-29 | 2019-04-02 | 河南鑫安利安全科技股份有限公司 | Portable meteorological measuring set control system |
| CN110687520A (en) * | 2018-07-06 | 2020-01-14 | 英飞凌科技股份有限公司 | Detection and Compensation of Asymmetry and Periodic Jitter of MEMS Oscillating Structures |
-
2003
- 2003-01-27 CN CNA031151671A patent/CN1521950A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101051836B (en) * | 2007-03-30 | 2012-01-11 | 北京中星微电子有限公司 | Device and method for timed synchronous transmission stream decoding and coding |
| CN101414823B (en) * | 2007-10-16 | 2012-08-08 | 联发科技股份有限公司 | Error Compensation Method, Digital Phase Error Elimination Module and Full Digital Phase Locked Loop |
| CN110687520A (en) * | 2018-07-06 | 2020-01-14 | 英飞凌科技股份有限公司 | Detection and Compensation of Asymmetry and Periodic Jitter of MEMS Oscillating Structures |
| CN110687520B (en) * | 2018-07-06 | 2023-08-25 | 英飞凌科技股份有限公司 | Detection and compensation of asymmetric and periodic jitter of MEMS oscillating structure |
| CN109557602A (en) * | 2018-12-29 | 2019-04-02 | 河南鑫安利安全科技股份有限公司 | Portable meteorological measuring set control system |
| CN109557602B (en) * | 2018-12-29 | 2020-12-15 | 周意 | Portable meteorological measuring instrument control system |
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