CN1552011A - 对数字信号改进定时和使外部影响最小化 - Google Patents

对数字信号改进定时和使外部影响最小化 Download PDF

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CN1552011A
CN1552011A CNA028174283A CN02817428A CN1552011A CN 1552011 A CN1552011 A CN 1552011A CN A028174283 A CNA028174283 A CN A028174283A CN 02817428 A CN02817428 A CN 02817428A CN 1552011 A CN1552011 A CN 1552011A
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clock pulse
clock
signal
time
pulse signal
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F・赫内尔
F·赫内尔
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Siemens Corp
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Abstract

数字系统的性能很大程度取决于频率。但是为了使数字信号安全地从一个驱动器经过一个印制导线到达接收机，频率越高留存的时间就越小。必须将时钟脉冲和信号的运行时间最佳化到使得即使在极端的环境情况时也不会给定时造成任何损害。本发明通过将输出信号结合到一个内部PLL－时钟脉冲上，改善了定时并使外部影响降低到最小。

Description

对数字信号改进定时和使外部影响最小化
1.通过本发明要解决哪个技术问题？
2.迄今这个问题是如何解决的？
3.以何种方式解决本发明所说明的技术问题？
4.本发明的实施例。
关于第1点  通过本发明要解决哪个技术问题？
数字系统性能在很大程度上取决于频率。但是：为了使数字信号安全地从一个驱动器经过一个印制导线到达接收机，频率越高留存的时间就越小。限制因素是时钟-至-输出时间、板上运行时间、接收机的设定/保持-时间、输出和输入扭斜(skew)(发送器和接收机的扭斜)以及时钟扭斜或抖动(tskew)。
图1示出的是一个数字信号在一个发送器的驱动器输出端和在接收机输入端的短时状态，这里表示出了所列因素在时间上的影响。
设定时间-要求说明，一个要提供时钟脉冲的信号在时钟脉冲边沿之前必须稳定多少纳秒。保持时间-要求说明，信号在一个时钟脉冲边沿之后还必须保持稳定多长时间。如果改变时钟脉冲和信号相互时间点的状态，这对一个要求有正面影响，但对另一个要求则有负面作用。
在极其有利的环境条件(温度低，电源电压高，驱动器功率强，接收机的寄生电容小)下，信号很快。但时钟脉冲有时并不特别快。此时存在保持时间-问题。
在极其不利的环境条件(温度高，电源电压低，驱动器功率弱，接收机的寄生电容大)下，信号很慢。但时钟脉冲有时并不特别慢。此时存在设定时间-问题。
必须将时钟和信号的运行时间优化到使得即使在极其不利的环境情况下也不会给定时造成任何损害。折衷方案决定最大可能的频率和系统性能，或迫使在结构上进行限制。
关于第2点  迄今这个问题是如何解决的？
通常制订一个表，该表为每个信号列出所有要注意的定时-参数，对快速和缓慢的情况都计算出一个预算和一个损害。所述参数能(受限制地)通过选择元器件、板布局和(如果发送器或接收机位于一个ASIC中)通过ASIC的设计受影响。该限制是由于选出的元器件(驱动器的强度、数据表的设定/保持时间)、元器件在板上的距离、网络的结构(单向/双向信号、参与的驱动器/接收机数量)和频率或时钟脉冲周期造成的。然后进行优化。然而如果针对缓慢情况进行优化，那么就对快速情况有害，反之亦然。
信号姓名 tskew芯片 tco，min  tco，max  trun，min  trun，max  T设定 t保持 保持空白 设定空白
表1：设定和保持时间空白计算
保持空白＝tco，min+trun，min-tskew-thold
设定空白＝7.5纳秒-tco，max-trun，max-tsetup-tskew
有时候问题也根本没有解决，而是回避了。例如在PC中的SDRAM地址-信号：其中地址-信号是由驱动器发出，而用再下一个时钟脉冲才在接收机上提供时钟脉冲(eingetaktet)。这对SDRAM-控制器的设计和整个系统的性能有影响。此外，为了避开定时-问题，将具有SDRAM总线频率133MHz的PC母板只装备最多3个SDRAM模块(DIMM)装备。然而，这就限制了最大可能的存储器扩展。
为了使发送器与接收机之间的时钟脉冲-扭斜最小化，一个已经部分流行的可能性是，在一个发送器-标准组件(例如ASIC)中应用一个PLL，参见图2。此时，用于SDRAM的时钟脉冲和信号来自相同的芯片。一个附加的时钟脉冲输出又饶回到发送器的PLL，而且是与接收机-时钟有相同的物理长度。PLL较早地发出这个与板-运行时间t_run符合的反馈-时钟脉冲，从而反馈-时钟脉冲就以与参考-时钟脉冲相位相同的方式进入到ASIC的PLL-输入端。由于接收机-时钟的相同运行时间，它在其接收机上在时间点T0也自动使相位相同。这样，发送器与接收机之间的时钟-扭斜总是等于零。
关于第3点  以何种方式解决本发明所说明的技术问题？
本发明为快速和缓慢情况指向一个接近恒定的时钟-至-输出时间。通过板布局-措施，此外考虑到时钟和信号在板上的边沿距离得到保持，并在接收机处不改变。从可以以少量的限制条件提高最大频率或总线频率的驱动。在定时设计-风险明显降低(在图3中以箭头表明，相同地实施信号和时钟脉冲的所有范围。决定时钟-至-输出-时间的线路长度和缓冲器也是如此。因此，时钟-至-输出-时间与环境影响无关，并且也与ASIC的制造工艺无关。同样相同地设定板上信号运行时间，从而与环境影响无关)。
本发明的一个主要特征在于，这个总线的输出-FF不是用正常系统-时钟脉冲为ASIC的核芯提供时钟脉冲，而是用一个由PLL输出端时钟脉冲推导出的时钟脉冲(参见图3)。这个时钟脉冲由PLL在缓慢情况时相应地较早发出，以便在PLL-输入端与参考-时钟脉冲相位相同。在缓慢情况，信号的输出也较弱并在板上需要较长的时间。因此，也将信号较早地发出是合理的。这通过用输出端时钟脉冲的脱离计时(Abtaktung)自动完成。在快速情况时，将时钟和信号发出的相应较迟。实施缓冲器类型和时钟-和信号-输出缓冲器的放置。在两种极端情况下，时钟-至-输出距离tco总是相同。通过输出-时钟-路径中的延迟-元件能使时钟-至-输出-时间最小化。
在板布局中，将信号的运行时间与时钟和反馈-时钟的运行时间也调整到一致。总线的所有信号要微调到相同长度。因此，从驱动器标准组件到接收机的时钟-至-信号-距离保持一样，与环境条件无关。这样，在定时-表中同时有多个参数被降低：时钟-至-输出，输出扭斜和运行时间扭斜。除此之外，照顾到了在快速或缓慢情况参数的一致性。
关于第4点  本发明的实施例。
用一个ASIC，4×512MB SDRAM DIMM和一个133MHz的时钟-乘法器的SDRAM-存储控制，举例实现了所介绍的原则，参见图4。
PLL考虑到，在时间点T0上，上升的时钟脉冲边沿既在ASIC也在DIMM的相位相同而没有扭斜。相对于用tco的时钟-输出用同样的时钟脉冲也将信号发出，与联系起来。如果在布局中将时钟脉冲和信号调整到一致，则时钟脉冲与信号之间的距离总是准确为Tco。这与环境因素和ASIC-过程因素是否为加速或减速作用无关。由于运行时间的差别、输出-扭斜、板-扭斜、DIMM-扭斜以及DIMM-时钟-扭斜和通常方式考虑的因素造成不准确性。
在这个实施例中，还附带识别出一个PLL时钟驱动器和三个延迟线。此外输入端信号是分开处理的。这些延迟线用于说明双向数字信号往返方向定时的独立可调性。
尽管尤其在PC-领域还没有要求(3cm的较低板-结构高度用倾斜插座的4个DIMM-插接位置，地址-信号只关心一个时钟脉冲)，但是通过采用本发明，有可能在安全定时而不给系统造成性能损害的情况下实现一个133MHz的总线时钟脉冲。
最后有一个关于在发送器和接收机时时钟与信号之间必要距离的举例说明：
a)假设：发送器和接收机从外面得到相位相同的时钟。发送器有一个一定的时钟-至-输出-时间tco。接收机要求一个一定的保持-时间thd(在时钟脉冲边沿之后还必须将信号保持一定时间thd稳定，这样肯定将逻辑层次识别出)。
b)如果tco＞thd，最简单的解决办法：即使在板上根本没有运行时间，保持时间还是得到满足。
c)如果tco＜thd：板-运行时间考虑到信号的一个延迟，使保持时间仍然得到满足。
d)板-运行时间很长(大距离)和时钟脉冲周期很短(高频率)：板-运行时间使信号边沿延迟，使得接收机的设定时间tsu不能被遵守。那么，信号或许还要用过去的逻辑层次脱离计时！这种情况在133MHz和10cm的距离及大的容性负载时，对于多个接收机是正常的。因此，将信号用tco结合到时钟脉冲上并将两者一起发出。由于在板上长度相同，将距离tco一直保持到接收机并在那里像在b)那样满足保持时间。SPLL考虑到将正好所需要的那么多提前脱离计时。
e)在实现时甚至表明tco＜thd。这能用板-PLL和延迟1(参见图4)适当推移。
               应用的缩写
DIMM           Dual Inline Memory Module
DRAM           Dynamic Random Access Memory
SDRAM          Synchronous Dynamic Random Access Memory
PLL            Phase Locked Loop
SPLL           PLL for SDRAM
扭斜           (逐字翻译)倾斜位置，失真
时钟脉冲-扭斜  通过不同长的运行时间和/或通过不同驱动器强或接
               收机负荷产生的时间差。由时钟脉冲-扭斜造成，将
               一些接收机-寄存器比其它的早一些/迟一些接通。
输出-扭斜      在属于同类的信号(总线)时tco时间的发散宽度，
输入扭斜       在芯片中从外面管脚到接收机的输入-运行时间的
               发散宽度

Claims (3)

1.数字系统，具有
-用于处理数据的处理装置(核芯)，该处理装置经过第一个时钟脉冲信号被提供时钟脉冲，
-经过信号线向另一个数字系统发送数据的数据输出-寄存器，
-PLL-装置，它从所述第一个时钟脉冲信号产生第二个时钟脉冲信号，将第二个时钟脉冲信号经过一个时钟脉冲线路作为时钟脉冲信号传给所述另一个数字系统，此时PLL-装置的反馈环与所述信号线路具有相同的运行时间，
其特征在于：
-第二个时钟脉冲信号作为时钟脉冲信号被传送给数据输出-寄存器，
-所述时钟脉冲线路与所述信号线具有相同的运行时间。
2.如权利要求1的数字系统，
其特征在于：
数字系统内的运行时间和时钟脉冲信号的缓冲器类型和数据信号保持一致。
3.如权利要求1或2的数字系统，
其特征在于：
所述运行时间的一致性，是通过确定各自线路物理长度一个相应的尺度和/或通过采用至少一个延迟装置来实现。
CNA028174283A 2001-09-06 2002-08-30 对数字信号改进定时和使外部影响最小化 Pending CN1552011A (zh)

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CN101079617B (zh) * 2006-05-26 2012-07-04 半导体元件工业有限责任公司 精确的定时信号发生器及其方法

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