CN202425205U - Printed circuit board (PCB) with built-in resistors - Google Patents
Printed circuit board (PCB) with built-in resistors Download PDFInfo
- Publication number
- CN202425205U CN202425205U CN2012200012344U CN201220001234U CN202425205U CN 202425205 U CN202425205 U CN 202425205U CN 2012200012344 U CN2012200012344 U CN 2012200012344U CN 201220001234 U CN201220001234 U CN 201220001234U CN 202425205 U CN202425205 U CN 202425205U
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- resistor
- substrate layer
- circuit board
- layer
- pcb
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Abstract
本实用新型公开了一种内埋置电阻器的印刷电路板，包括电阻器、多个电路层、以及多个分别设置在各电路层之间的绝缘层，所述的绝缘层包括第一基板层和第二基板层，电阻器设置在第二基板层中且位于第一基板层的上表面处，其特征在于：电阻器上表面的两端分别设有铜箔电极，电极的上表面设有穿过第二基板层的微通孔，微通孔的连接端设置在第二基板层上与电路层连接；所述的电阻器为蛇形。该印刷电路板可减少电子封装体积、节省材料，提高产品集成度；提高电子封装方面电气性能，蛇形电阻占用PCB的面积更小，集成度更高，电气互联的线路更短，提高了电气性能；增加内埋置电阻的阻值，满足特殊电路对埋置电阻高阻值的需求。
The utility model discloses a printed circuit board embedded with a resistor, which comprises a resistor, a plurality of circuit layers, and a plurality of insulating layers respectively arranged between each circuit layer, and the insulating layer includes a first substrate layer and the second substrate layer, the resistor is arranged in the second substrate layer and is located on the upper surface of the first substrate layer, and it is characterized in that: the two ends of the upper surface of the resistor are respectively provided with copper foil electrodes, and the upper surface of the electrode is provided with There are micro through-holes passing through the second substrate layer, and the connecting ends of the micro-through holes are arranged on the second substrate layer to connect with the circuit layer; the resistor is serpentine. The printed circuit board can reduce the volume of electronic packaging, save materials, and improve the integration of products; improve the electrical performance of electronic packaging, the area occupied by the snake resistor is smaller, the integration is higher, the electrical interconnection is shorter, and the electrical performance is improved. Performance; increase the resistance value of the embedded resistor to meet the needs of special circuits for high resistance value of the embedded resistor.
Description
Technical field
The utility model relates to printed circuit board (PCB) (PCB), especially a kind of printed circuit board (PCB) of embedded set resistor.
Background technology
Development along with electronic product; Present surface installation technique (SMT) is widely used in microelectronics assembling and encapsulation; Generally speaking; In the typical SMT technology, passive component occupies whole approximately PCB substrate 40% and above area, has restricted the development of electronic product to miniaturization, multi-functional, low-cost, high-performance direction.According to international semiconductor route map (ITRS), substrate embedded set passive device technology (EPT) is as a kind of advanced form of system in package (SIP), has clear superiority than the surface installation technique (SMT) of passive device.
The embedded set passive device is as a kind of advanced form of microelectronics surface-assembled (SMT); Because the development of technology and of the requirement of some circuit design to embedding passive device; Require embed-type PCB thinner under littler embedding volume and the specific condition, higher electrical property; Also require simultaneously the resistor of embedded set passive device need down to require higher resistance value at some special circuits.
Summary of the invention
The purpose of the utility model is the deficiency to prior art; Cater to miniaturization of electronic products, multi-functional, low-cost, high performance mainstream development direction, for the special circuit that satisfies some embed-type PCB provides a kind of printed circuit board (PCB) with snakelike resistance device of embedded set of high resistance to the demand of the high resistance of embedded resistors.
The purpose of the utility model is to realize through following technical scheme:
A kind of printed circuit board (PCB) of embedded set resistor; Comprise resistor, a plurality of circuit layer and a plurality of insulating barrier that is arranged between each circuit layer; Described insulating barrier comprises first substrate layer and second substrate layer; Resistor is arranged in second substrate layer and is positioned at the upper surface place of first substrate layer; Different with prior art is: the two ends of resistor upper surface are respectively equipped with copper foil electrode, and the upper surface of copper foil electrode is provided with the micro through hole that passes second substrate layer, the link of micro through hole be arranged on second substrate layer with insulating barrier between circuit diagram be connected.
Described resistor is snakelike.
Said first substrate layer is a FR-4 epoxy resin.
Said second substrate layer is FR-4 epoxy resin or polyimides.
The utlity model has following advantage:
1. reduce encapsulation volume, apparent surface's packaging technology and common embedding resistance can reduce the Electronic Packaging volume, save material, make the electronic product integrated level higher;
2. raising electric property can improve Electronic Packaging aspect electric property, and it is littler mainly to be that snakelike resistance takies the area of PCB relatively, and integrated level is higher, and the circuit of electrical interconnection is shorter, thereby has improved electric property;
3. increase the resistance of embedded set resistance, satisfy the demand of special circuit embedding resistance high value.
Description of drawings
Fig. 1 is the cross-sectional view of embodiment insulating barrier;
Fig. 2 is an A-A line of vision structural representation among Fig. 1.
Among the figure, 1. first substrate layer, 2. resistors, 3. electrodes, 4. second substrate layers, 5. micro through holes.
Embodiment
Below in conjunction with embodiment and accompanying drawing the utility model content is done further to specify, but be not qualification the utility model.
Embodiment:
With reference to Fig. 1 Fig. 2; A kind of printed circuit board (PCB) of embedded set resistor; Comprise resistor, a plurality of circuit layer and a plurality of insulating barrier that is arranged between each circuit layer; Insulating barrier comprises first substrate layer 1 and second substrate layer 4, and resistor 2 is arranged in second substrate layer 4 and is positioned at the upper surface place of first substrate layer 1, and the two ends of resistor 2 upper surfaces are respectively equipped with copper foil electrode 3; The upper surface of electrode 3 is provided with the micro through hole 5 that passes second substrate layer 4, and the link of micro through hole 5 is arranged on second substrate layer 4 and is connected with circuit diagram.
After insulating barrier completes; Make circuitous pattern at insulating barrier laminated Copper Foil; Promptly make circuit layer, the embedded set resistor in the insulating barrier is interconnected through micro through hole 5 and circuit layer, repeats above step; Layer with layer between interconnectedly be connected through via, finally produce the printed circuit board (PCB) of embedded set resistor.
Claims (4)
1. the printed circuit board (PCB) of an embedded set resistor; Comprise resistor, a plurality of circuit layer and a plurality of insulating barrier that is separately positioned between each circuit layer; Described insulating barrier comprises first substrate layer and second substrate layer; Resistor is arranged in second substrate layer and is positioned at the upper surface place of first substrate layer; It is characterized in that: the two ends of resistor upper surface are respectively equipped with copper foil electrode, and the upper surface of electrode is provided with the micro through hole that passes second substrate layer, and the link of micro through hole is arranged on second substrate layer and is connected with circuit layer.
2. printed circuit board (PCB) according to claim 1 is characterized in that: described resistor is snakelike.
3. printed circuit board (PCB) according to claim 1 is characterized in that: said first substrate layer is a FR-4 epoxy resin.
4. printed circuit board (PCB) according to claim 1 is characterized in that: said second substrate layer is FR-4 epoxy resin or polyimides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200012344U CN202425205U (en) | 2012-01-04 | 2012-01-04 | Printed circuit board (PCB) with built-in resistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200012344U CN202425205U (en) | 2012-01-04 | 2012-01-04 | Printed circuit board (PCB) with built-in resistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202425205U true CN202425205U (en) | 2012-09-05 |
Family
ID=46749924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012200012344U Expired - Fee Related CN202425205U (en) | 2012-01-04 | 2012-01-04 | Printed circuit board (PCB) with built-in resistors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202425205U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573292A (en) * | 2012-01-04 | 2012-07-11 | 桂林电子科技大学 | Printed circuit board and manufacturing method of embedded resistor |
-
2012
- 2012-01-04 CN CN2012200012344U patent/CN202425205U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102573292A (en) * | 2012-01-04 | 2012-07-11 | 桂林电子科技大学 | Printed circuit board and manufacturing method of embedded resistor |
| CN102573292B (en) * | 2012-01-04 | 2014-07-23 | 桂林电子科技大学 | Printed circuit board and manufacturing method of embedded resistor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120905 Termination date: 20140104 |