CN205004354U - III - V compound semiconductor hall element of clan - Google Patents

Abstract

The utility model discloses a III - V compound semiconductor hall element of clan, its structure includes hall element functional layer film, assembles on the insulating radiation base through the mode of flip chip bonding, the electrode figure has been prepared in advance to the insulating radiation base. A mode, with hall element functional layer membrane separator, dear single crystal lining ground warp thread crosses simple processing back, can repeatedly be used for epitaxial growth, and the number of repetition is more than 20 times, but greatly reduced manufacturing cost for growing the single -crystal underlay of hall element functional layer film is peeled off through the substrate.

Description

A III-V Compound Semiconductor Hall Element

technical field

The utility model relates to the technical field of semiconductors, in particular to a III-V group compound semiconductor Hall element.

Background technique

The 21st century is the era of electronic information, and sensor technology is an important technical basis for the information society. Hall element is a magnetic sensor based on the Hall effect. They have a firm structure, small size, light weight, long life, easy installation, low power consumption, high frequency, vibration resistance, and are not afraid of dust, oil, water vapor and smoke. Such pollution or corrosion, so it is more and more widely used in modern society. Hall element is a key component in brushless DC motors, widely used in mobile phones, automotive ABS, electronic ignition and driving speed measurement, and can also be used in Hall ammeters, electronic compasses, current and voltage sensors, etc., becoming a national defense, industrial, civil It is an indispensable key device in many industrial sectors, and it is also the core technology for the development of military equipment, which plays a leading role in the construction of the national defense industry.

At present, Hall elements are mainly prepared by ion implantation method and epitaxial growth method. Both methods require a single crystal substrate material with a thickness of several hundred microns. The prepared Hall element contains a functional layer of several microns and several The substrate layer of 100 microns, the single crystal substrate material is expensive, and does not play the role of the functional layer in the Hall element. It can be reused, but in the current preparation process, it can only be used once, and there is a huge waste. On the other hand, in the traditional process, the single crystal substrate material used in the production of Hall elements must be an insulating or semi-insulating single crystal substrate material, and its price is more expensive than that of a certain doped single crystal substrate material a lot of.

Contents of the invention

For this reason, what the utility model is to solve is that the production cost of the existing III-V compound semiconductor Hall element is relatively high, and the single crystal substrate can only be used once, and there is a serious waste problem, thereby providing a low-cost III - Group V compound semiconductor Hall element. Among them, in the preparation process of the Hall element, the functional layer of the Hall element can be effectively separated from the single crystal substrate material. After the single crystal substrate is processed, it can be reused for epitaxial growth. On the other hand, more Inexpensive doped single crystal substrate material instead of expensive semi-insulating single crystal substrate.

For solving the problems of the technologies described above, the technical scheme of the utility model is as follows:

a) Provide a III-V group compound semiconductor single crystal substrate, preferably, a gallium arsenide substrate or an indium phosphide substrate;

b) growing a sacrificial layer on the III-V compound semiconductor single crystal substrate;

c) growing the functional layer material of the Hall element on the sacrificial layer;

d) Adhering a layer of flexible and chemically inert material on the surface of the epitaxial functional layer, this layer of material can assist the substrate to be peeled off, improving efficiency and yield;

e) Etching the sacrificial layer with a selective etching solution to realize the peeling of the epitaxial functional layer of the Hall element from the III-V compound semiconductor single crystal substrate; after the stripped III-V compound semiconductor single crystal substrate, after simple treatment, reusable;

f) Adhere one side of the flexible material of the epitaxial functional layer after peeling to another rigid substrate. Preferably, a silicon substrate, a glass substrate, a ceramic substrate or a rigid plastic substrate is selected as the rigid substrate;

g) On the functional layer of the Hall element, prepare ohmic contact metal, and complete mesa corrosion, passivation and other processes;

h) The Hall elements prepared with ohmic contact metal are assembled on the pre-patterned insulating and heat-dissipating substrate through flip-chip welding and other processes, and then the adhesive used in the previous process is dissolved by using a highly selective solution. The Hall element is separated from the supporting flexible material and the rigid substrate, and the Hall element with a thickness of only a few microns can be prepared. At the same time, the chip size of the Hall element can be effectively reduced by wire bonding on the insulating heat dissipation substrate instead of directly bonding on the metal electrode of the Hall element (the wire bonding package requires a larger area of the metal block).

A III-V compound semiconductor Hall element according to an embodiment of the present invention, wherein the III-V compound semiconductor single crystal substrate is gallium arsenide (GaAs), and the sacrificial layer is arsenic Aluminum (AlAs), the selective etching solution is hydrofluoric acid (HF) solution.

To sum up, the utility model utilizes the epitaxial stripping technology to prepare a very cost-effective Hall element. For III-V compound semiconductor single crystal substrates, each treatment consumes no more than 10 microns in thickness, and a substrate with a thickness of 500 microns can be reused at least 20 times. At the same time, the Hall element prepared by the traditional process requires the III-V compound semiconductor single crystal substrate to be semi-insulating, and its price is much more expensive than the doped single crystal substrate. The conductivity of the single crystal substrate is not required, and a doped single crystal substrate can be used to further reduce the cost.

Description of drawings

Hereinafter, embodiments of the present utility model will be described in detail in conjunction with the accompanying drawings. In the drawings: 001 is a III-V compound semiconductor single crystal substrate; 002 is a sacrificial layer; 003 is a Hall element functional layer; 004 is a flexible material; 005 is a rigid support substrate; 006 is an ohmic contact electrode; Patterned metal; 008 is an insulating heat dissipation base.

Fig. 1 Growth of a Hall element epitaxial functional layer on a III-V compound semiconductor single crystal substrate, including a III-V compound semiconductor single crystal substrate 001, a sacrificial layer 002, and a Hall element functional layer 003;

Fig. 2 Adhesive flexible material 004 on epitaxial functional layer 003, including III-V group compound semiconductor single crystal substrate 001, sacrificial layer 002, Hall element functional layer 003, flexible material 004;

Fig. 3 shows that after the sacrificial layer 002 is etched away, the III-V group compound semiconductor single crystal substrate 001 is separated from the Hall element functional layer 003 and the flexible material 004;

Fig. 4 shows that the Hall element functional layer 003, the flexible material 004 and the rigid support substrate 005 are adhered together after peeling off;

Figure 5 uses semiconductor planar technology to prepare the Hall element ohmic contact electrode 006, as well as mesa corrosion, passivation and other processes;

Figure 6 uses the reverse soldering process to assemble the ohmic contact electrode 006 of the Hall element with the pre-metallized insulating heat dissipation base 008, and the metallization pattern of the insulating heat dissipation base is 007;

FIG. 7 separates the flexible material 004, the rigid support substrate 005 from other parts of the Hall element on the basis of FIG. 6 .

detailed description

Example 1:

First take a gallium arsenide single crystal substrate, grow a sacrificial layer of aluminum arsenide (AlAs) on the substrate by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), and a Hall element functional layer . After the growth is completed, take the epitaxial wafer and spin-coat a layer of adhesive A on the surface. This adhesive is compatible with the subsequent semiconductor planar process and will not change during the process. Then take a flexible material B and stick it on it. The material is also compatible with the semiconductor planar process and will not change. The treated epitaxial wafer is immersed in a solution containing hydrofluoric acid, and the reaction selectivity ratio of hydrofluoric acid to aluminum arsenide (AlAs) and gallium arsenide (GaAs) exceeds 10,000. Utilizing the high corrosivity of hydrofluoric acid to the aluminum arsenide (AlAs) sacrificial layer, the sacrificial layer is completely corroded, and the Hall element functional layer is peeled off from the gallium arsenide single crystal substrate.

In addition, take a silicon wafer with the same size as the gallium arsenide single crystal substrate, spin-coat a layer of adhesive A on the surface of the silicon wafer, and adhere the stripped flexible material B and the functional layer of the Hall element to the silicon wafer. On the top, one side of the flexible material B is bonded to the silicon chip. According to the process of the standard Hall element, conventional photolithography method is adopted, the photoresist is spin-coated, exposed and developed, and the electrode pattern of the Hall element is obtained. Then use electron beam evaporation (E-beam) to vapor-deposit gold-germanium (Au-Ge) alloy. After dissolving the photoresist in the glue remover, the metal attached to the photoresist falls off, and the remaining metal is Hall The ohmic contact of the element to the metal. Rapid annealing in a nitrogen atmosphere makes the metal and semiconductor material form a good ohmic contact. Then adopt the method of photolithography overlay, continue to spin-coat photoresist on the surface of the epitaxial layer, expose, develop, and obtain the pattern of Hall element mesa etching. Chemical wet etching or dry etching is used to remove the semiconductor material in the area without photoresist protection to obtain a four-leaf clover-shaped pattern of the Hall element. Remove the photoresist for isolation protection, and then use plasma enhanced chemical vapor deposition (PECVD) to coat a layer of silicon nitride (SiNx) passivation layer material on the surface of the Hall element to protect the Hall element. The photolithography overlay method is used again to prepare and etch the pattern of the passivation layer material covering the ohmic contact metal of the Hall element, and then use dry etching to remove the silicon nitride (SiNx) on the ohmic contact metal, and finally use Stripping solution to remove photoresist.

Take an insulating and heat-dissipating substrate, arrange the metal patterns on the substrate according to the Hall elements, prepare symmetrical metal patterns, and then use the reverse welding process to weld the metal of the Hall elements and the metal of the insulating and heat-dissipating base. Finally, using a solution that can remove the adhesive A, the adhesive A is dissolved, and the flexible material B and the silicon chip are separated from the Hall element. So far, the whole technological process is all completed.

Claims (5)

1. A Ⅲ-Ⅴ group compound semiconductor Hall element, its structure includes an insulating heat dissipation base, an ohmic contact electrode, and a Hall element functional layer film arranged from bottom to top, and it is characterized in that: the Hall element structure does not contain III - Group V compound semiconductor single crystal substrate, supported by an insulating heat dissipation base. 2 . The III-V compound semiconductor Hall element according to claim 1 , wherein the Hall element functional layer thin film is prepared by epitaxial growth. 3 . 3 . The Hall element of III-V compound semiconductor according to claim 1 , wherein the thin film of the functional layer of the Hall element is separated from the III-V compound semiconductor single crystal substrate by means of epitaxial lift-off. 4 . 4 . The III-V compound semiconductor Hall element according to claim 1 , wherein the insulating heat dissipation base is pre-prepared with electrode patterns. 5 . The III-V compound semiconductor Hall element according to claim 1 , wherein the insulating and heat-dissipating base is a heat-dissipating ceramic sheet.