CN205864458U - A kind of counter modulation phaselocked loop carrier synchronization circuitry - Google Patents

Abstract

The utility model discloses a kind of counter modulation phaselocked loop carrier synchronization circuitry, comprising: phase-locked loop circuit, demodulator circuit, phase-shift circuit and counter modulation unit, wherein, input signal is divided into two-way, one tunnel is input to phase-locked loop circuit, and another road is input to demodulator circuit；One tunnel input signal is divided into two-way the first output signal through phase-locked loop circuit, one tunnel is input to demodulator circuit, exporting the second output signal after one tunnel input signal and road the first output signal demodulated circuit demodulation, another road first output signal exports the 3rd output signal after phase-shift circuit；Second output signal and the 3rd output signal export the 4th output signal after counter modulation unit counter modulation；4th output signal is input in phase-locked loop circuit.Counter modulation phaselocked loop carrier synchronization circuitry of the present utility model, circuit design the most easily realizes, and is affected less by peripheral components, distributed capacitor etc., and it is short that carrier synchronization sets up the time, synchronizes maintenance ability strong.

Description

An Inverse Modulation PLL Carrier Synchronization Circuit

technical field

The utility model relates to the field of aerospace technology, in particular to an anti-modulation phase-locked loop carrier synchronization circuit.

Background technique

The digitally modulated carrier or subcarrier signal is mostly in the form of a phase-shift keying signal with strong anti-interference. According to the signal detection theory, the phase-locked loop can be used to form the best coherent demodulator of phase-shift keying signal with the minimum average bit error rate. Compared to amplitude keying (ASK). Frequency shift keying (FSK), has the characteristics of strong anti-interference ability. Therefore, at present, phase-shift keying signals are mostly used for communication between spacecraft and ground measurement and control stations.

The spacecraft has relatively high requirements on the phase-shift keying signal carrier synchronization establishment time and maintenance ability. For example, it is generally required that the synchronization establishment time is not greater than 128bit, and the maintenance ability is not less than 32bit.

Utility model content

The utility model aims at the problems existing in the above-mentioned prior art, and proposes an anti-modulation phase-locked loop carrier synchronization circuit, the circuit design is simple and easy to implement, and its tracking band and capture band performance parameters are less affected by peripheral devices, distributed capacitors, etc. Small, the carrier synchronization establishment time is short, and the synchronization maintenance ability is strong.

In order to solve the problems of the technologies described above, the utility model is achieved through the following technical solutions:

The utility model provides an anti-modulation phase-locked loop carrier synchronization circuit, which includes: a phase-locked loop circuit, a demodulation circuit, a phase shift circuit and an anti-modulation unit, wherein,

The input signal is divided into two paths, the input signal of one path is input to the phase-locked loop circuit, and the input signal of the other path is input to the demodulation circuit;

One path of the input signal is divided into two paths of first output signals through the phase-locked loop circuit, one path of the first output signal is input to the demodulation circuit, one path of the input signal and one path of the first output signal pass through The demodulation circuit outputs a second output signal after demodulation, and the other first output signal outputs a third output signal after passing through the phase shift circuit;

The second output signal and the third output signal are demodulated by the demodulation unit to output a fourth output signal;

The fourth output signal is input into the phase-locked loop circuit.

Preferably, the phase-locked loop circuit includes: a phase detector, a loop filter, and a voltage-controlled oscillator connected in sequence, the phase detector is the input end of the phase-locked loop circuit, and the voltage-controlled oscillator The device is the output terminal of the phase-locked loop circuit.

Preferably, the phase-locked loop circuit is a phase-locked loop integrated circuit CD4046.

Preferably, the input signal is a binary phase-shift keying signal (BPSK), and BPSK coherent demodulation technology has strong anti-interference ability.

Preferably, the phase shift circuit is phase shift circuit.

Compared with the prior art, the utility model has the following advantages:

(1) The anti-modulation phase-locked loop carrier synchronization circuit provided by the utility model is simple and easy to implement, the performance parameters of the tracking band and the capture band are less affected by peripheral devices, distributed capacitors, etc., and the phase-shift keying signal carrier synchronization establishment time is short , Long synchronization maintenance ability, synchronization establishment time is less than 4bit, synchronization maintenance ability can reach more than 640bit;

(2) In the anti-modulation phase-locked loop carrier synchronous circuit of the present utility model, increase between the phase-locked loop circuit and the anti-modulation unit phase shifting circuit for eliminating the PLL circuit's own Phase difference, carrier synchronization performance is better.

Of course, any product implementing the present utility model does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

Below in conjunction with accompanying drawing, the embodiment of the present utility model is further described:

Fig. 1 is the schematic diagram of the anti-modulation phase-locked loop carrier synchronization circuit of the present utility model;

Fig. 2 is the schematic diagram of the anti-modulation phase-locked loop carrier synchronization circuit of the present utility model;

Fig. 3 is the embodiment of the utility model Schematic diagram of the phase shift circuit;

Fig. 4 is the embodiment of the utility model The timing diagram of the phase shift circuit;

Fig. 5 is the schematic diagram of the demodulation circuit of the embodiment of the present utility model;

FIG. 6 is a timing diagram of the demodulation circuit of the embodiment of the present invention.

Explanation of symbols: 1 - phase-locked loop circuit, 2 - phase shift circuit, 3 - demodulation circuit, 4 - anti-modulation unit; 11 - phase detector, 12 - loop filter, 13 - voltage controlled oscillator.

detailed description

The following is a detailed description of the embodiments of the present utility model. This embodiment is implemented on the premise of the technical solution of the present utility model, and detailed implementation methods and specific operating procedures are provided, but the protection scope of the present utility model is not limited to the following the described embodiment.

In conjunction with Fig. 1-Fig. 5, the anti-modulation PLL carrier synchronization circuit of the present utility model is described in detail, as shown in Fig. 1, it is a schematic diagram, which includes: PLL circuit 1, phase shift circuit 2, demodulation circuit 3 And the anti-modulation unit 4, the input signal U1(t) is divided into two paths, one path is input to the phase-locked loop circuit 1, and the path input signal and the path first output signal are demodulated by the demodulation circuit 3 to output the second output signal U3 (t), the other one is input to the demodulation circuit 3, the phase-locked loop circuit 1 outputs the first output signal U2(t), the first output signal U2(t) is divided into two routes, and one is input to the demodulation circuit 3 , the other input to Phase shift circuit 2, another road input to demodulation circuit 3, phase shift circuit 2 is used for eliminating the phase difference of phase-locked loop circuit 1 self, outputs the 3rd output signal U4 (t); The second output signal U3 (t) and The third output signal U4(t) is input to the anti-modulation unit 4 for anti-modulation to output the fourth output signal U5(t), and then input to the phase-locked loop circuit 1 .

In this embodiment, the phase-locked loop circuit 1 includes a phase detector 11, a loop filter 12, and a voltage-controlled oscillator (VCO) 13 connected in sequence, and the phase detector 11 is an input terminal of an input signal and a fourth output signal, The voltage controlled oscillator 13 is the output terminal of the first output signal.

As shown in Figure 2, it is the schematic diagram of the carrier synchronization circuit of this embodiment. In this embodiment, the phase-locked loop circuit 1 adopts the phase-locked loop integrated circuit CD4046, and the anti-modulation unit 4 is an exclusive OR gate. As shown in the figure, the input The signal is a BPSK signal, and after the output signal of the voltage-controlled oscillator 13 of the phase-locked loop circuit 1 is XORed with the output signal of the demodulation circuit 3, it is sent to the comparison terminal COMP IN of the phase-locked loop circuit 1 for feedback comparison, thereby realizing For the anti-modulation of the phase-locked loop circuit 1, the parameters of the tracking band can be obtained by debugging R1* and R2*, and the parameters of the capture band can be obtained by debugging R3* and R4*. The schematic diagram of the phase shift circuit 2 of the present embodiment is as shown in Figure 3, and the phase shift circuit of the present embodiment is phase-shift circuit for eliminating phase-locked loop Phase difference, the signal with a frequency of 2CP is divided by two by the D flip-flop to obtain the signal CP, and the signal CP and 2CP are XORed to obtain the signal CPX, then CPX is the phase shift of the signal CP The signal, its phase shift sequence is shown in Figure 4. The schematic diagram of the demodulation circuit 3 of this embodiment is shown in Figure 5, CP is the extracted coherent carrier, which has the same frequency and phase as the modulation signal BPSK, and the analog switch selects the low-level signal and BPSK signal respectively under the control of CP , so as to generate signal A, when the CP is high level, the low level is selected, and when the CP is low level, the BPSK signal is selected. Signal A and signal B are calculated to obtain signal C, C=2A-B, after the C signal is low-passed, the double frequency component of the subcarrier is filtered out, and then a shaped code rate square wave signal is generated by the limiting circuit D, the PCM code stream demodulated by the machine; the waveforms of the signals at each point are shown in Figure 6. The carrier synchronization performance of the phase-locked loop carrier synchronization circuit of this embodiment has been tested and the carrier synchronization establishment time is less than 4 bits, and the carrier synchronization maintenance capability can reach more than 640 bits.

The principle is described below in conjunction with specific formulas, and the input signal BPSK signal is:

U1(t)＝m(t)sin(ω ₀ t+θ ₁ );

Among them, m(t) is the modulation function, take ±1, ω ₀ is the carrier frequency, θ ₁ is the initial phase of the carrier;

U2(t) is the extracted coherent carrier, then:

U2(t)=sin(ω ₀ t+θ ₂ );

but:

U3(t)=U1(t)U2(t)=K _d m(t)cos(θ ₁ -θ ₂ )=±K _d cos(θ ₁ -θ ₂ );

Ignoring the second harmonic item, K _d is the gain of the demodulator. After limiting, (θ ₁ -θ ₂ ) is positive in quadrants 1 and 4, and negative in quadrants 2 and 3.

U2(t) phase shift but:

U4(t)=cos(ω ₀ t+θ ₂ );

U5(t)＝U3(t)U4(t)＝±K _d m(t)cos(ω ₀ t+θ ₂ );

U6(t)=U1(t)U5(t)=±K _d m ² (t) sin(θ ₁ -θ ₂ )=±K _d sin(θ ₁ -θ ₂ );

Neglecting the second harmonic term, (θ ₁ -θ ₂ ) is positive in quadrants 1 and 4, and negative in quadrants 2 and 3.

From the above analysis, it can be seen that the loop error control voltage U6(t) has nothing to do with the polarity change of the signal modulation function m(t), it only controls the VCO frequency according to the change of the phase difference (θ ₁ -θ ₂ ). The coherent carrier wave extracted by the U2(t) bit, U3(t) is the demodulated modulated signal m(t), so according to this principle, the phase-locked loop can be used to design the carrier synchronization circuit. However, in the BPSK signal, the carrier component has been suppressed, and the reference phase carrier cannot be directly extracted from the phase-modulated signal by using a phase-locked loop or a narrow-band filter. Therefore, in this embodiment, while designing the PLL, a corresponding PLL auxiliary circuit is designed, and the phase modulation signal is non-linearly processed through the demodulation circuit 3 and the anti-modulation unit 4, and the phase modulation information is eliminated. To restore the parameters containing reference phase information, and then purify it to generate the reference phase carrier U5(t) necessary for coherent detection, so as to realize carrier synchronization; at the same time, design phase shift circuit 2 to eliminate the PLL itself Phase difference.

In the anti-modulation phase-locked loop carrier synchronization circuit of this embodiment, the demodulated signal is anti-modulated to the input signal, which not only cancels the modulation in the received signal, but also reduces the modulation degree of the signal, restores a part of the carrier component, and is controlled by the lock The phase loop circuit extracts the carrier component, and the extracted coherent carrier is not only used for output, but also provided for coherent demodulation; since the error control voltage of the phase locked loop circuit 1 has nothing to do with the polarity change of the signal demodulation function, It only controls the frequency of the voltage-controlled oscillator according to the change of the phase difference (θ ₁ -θ ₂ ), thereby realizing carrier synchronization, and the carrier synchronization performance is superior.

What is disclosed here is only the preferred embodiment of the utility model. This specification selects and describes these embodiments in detail to better explain the principle and practical application of the utility model, not to limit the utility model. Any modifications and changes made by those skilled in the art within the scope of the description shall fall within the protection scope of the present utility model.

Claims (5)

1. a counter modulation phaselocked loop carrier synchronization circuitry, it is characterised in that including: phase-locked loop circuit, demodulator circuit, phase shift electricity Road and counter modulation unit, wherein,

Input signal is divided into two-way, and input signal described in a road is input to described phase-locked loop circuit, another road input signal input To described demodulator circuit；

Input signal described in one tunnel is divided into two-way the first output signal through described phase-locked loop circuit, the first output letter described in a road Number being input to described demodulator circuit, described in input signal described in a road and a road, the first output signal is through described demodulator circuit Exporting the second output signal after demodulation, the first output signal described in another road exports the 3rd output letter after described phase-shift circuit Number；

It is defeated that described second output signal and described 3rd output signal export the 4th after described counter modulation unit counter modulation Go out signal；

Described 4th output signal is input in described phase-locked loop circuit.

Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described phase-locked loop circuit bag Including: phase discriminator, loop filter and the voltage controlled oscillator being sequentially connected with, described phase discriminator is the input of described phase-locked loop circuit End, described voltage controlled oscillator is the outfan of described phase-locked loop circuit.

Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described phase-locked loop circuit is Phase-locked loop intergrated circuit CD4046.

Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described input signal is two System phase-shift keyed signal.

Counter modulation phaselocked loop carrier synchronization circuitry the most according to claim 1, it is characterised in that described phase-shift circuit is Phase-shift circuit.