CN207217536U - Array substrate and mobile terminal - Google Patents

Abstract

The disclosure is directed to a kind of array base palte and mobile terminal.The array base palte includes：Substrate；Fluting；Multiple pixel cells, are laid on substrate and form viewing area；The pixel cell at the first sub- edge forms the first viewing area, and the pixel cell at the second sub- edge forms the second viewing area；Pixel cell positioned at same a line of the first viewing area shares first grid line；Pixel cell positioned at same a line of the second viewing area shares second grid line；First grid drive circuit positioned at the first side of fluting, for the pixel cell by the driving of the first grid line positioned at the first viewing area；Second grid drive circuit positioned at the second side of fluting, for the pixel cell by the driving of the second grid line positioned at the second viewing area；A plurality of clock cable, first grid drive circuit and second grid drive circuit are by different clock signal line traffic controls.The depth of fluting can be reduced in the embodiment of the present disclosure, reach the purpose of mobile terminal narrow frame design.

Description

Array substrate and mobile terminal

technical field

The present disclosure relates to the technical field of terminals, and in particular, to an array substrate and a mobile terminal.

Background technique

With the popularity of mobile terminals such as smart phones, more and more users prefer mobile terminals with large screens and narrow borders. Due to some accessories of the mobile terminal, for example, the front camera will occupy the position of the display screen, so that some areas of the display screen cannot be displayed. In order to achieve a narrow frame, in the related art, the array substrate is slotted (Notch), and the front camera is placed in the slot, so that content is displayed on both sides of the camera, thereby increasing the area ratio of the display screen and realizing a narrow frame.

However, in the process of implementing the technical solution of the present invention, the inventors found that the grid lines of the pixel units on both sides of the slot need to avoid the slot, occupying part of the display area around the camera, and affecting the visual appearance.

Utility model content

The present disclosure provides an array substrate and a mobile terminal to solve or partially solve the deficiencies in the related technologies.

According to a first aspect of an embodiment of the present disclosure, an array substrate is provided, and the array substrate includes:

base;

a slot disposed on an edge of the base;

A plurality of pixel units are arranged on the substrate to form a display area; wherein the pixel units of the first sub-edge constitute the first display area, and the pixel units of the second sub-edge constitute the second display area, wherein the first sub-edge an edge is an area of the edge on a first side of the slot, and the second sub-edge is an area of the edge on a second side of the slot;

The pixel units located in the same row of the first display area share a first gate line;

The pixel units located in the same row of the second display area share a second gate line;

a first gate drive circuit located on the first side of the slot, electrically connected to a plurality of the first gate lines, and used to drive the pixel units located in the first display area;

a second gate drive circuit located on the second side of the slot, electrically connected to a plurality of the second gate lines, and used to drive the pixel units located in the second display area;

A plurality of clock signal lines, the first gate drive circuit and the second gate drive circuit are controlled by different clock signal lines.

Optionally, a third display area is provided on the array substrate, and the third display area is composed of pixel units below the bottom of the groove; and the pixel units in the same row in the third display area share a first Three bars.

Optionally, the first gate drive circuit includes a first drive unit and a second drive unit;

The first driving unit is electrically connected to a plurality of the first gate lines for driving pixel units located in the first display area;

The second driving unit is electrically connected to a plurality of the third gate lines for driving pixel units located in the third display area.

Optionally, the size of the driving tube in the first driving unit is smaller than the size of the driving tube in the second driving unit.

Optionally, the size of the driving transistor in the second gate driving circuit is smaller than the size of the driving transistor in the second driving unit.

Optionally, the second drive unit is disposed on the first side of the slot.

Optionally, a first non-display area is provided on the array substrate, and a first drive unit is provided in the first non-display area;

The first non-display area is an area between the slot and the first display area.

Optionally, a second non-display area is provided on the array substrate, and the second gate drive circuit is provided in the second non-display area;

The second non-display area is an area between the slot and the second display area.

Optionally, the plurality of clock signal lines are disposed between the display area and the substrate, and extend to the first non-display area or the second non-display area.

Optionally, a third non-display area is disposed on the array substrate, and a first drive unit is disposed in the third non-display area;

The third non-display area is an area between the first display area and the first sub-edge.

Optionally, a fourth non-display area is disposed on the array substrate, and the second gate drive circuit is disposed in the fourth non-display area;

The fourth non-display area is an area between the second display area and the second sub-edge.

Optionally, the plurality of clock signal lines are arranged between the display area and the substrate, and extend to the third non-display area or the fourth non-display area.

According to a second aspect of an embodiment of the present disclosure, a mobile terminal is provided, including the array substrate described in the first aspect and a preset component, where the preset component is disposed in a slot.

Optionally, the preset component includes at least one of a camera, a receiver, a speaker and a light sensor.

The technical solutions provided by the embodiments of the present disclosure may include the following beneficial effects:

It can be seen from the above embodiments that the present disclosure forms a display area by arranging a plurality of pixel units on a substrate provided with slots, the same row of pixel units located on the first side of the slots share a first gate line, and the pixel units located on the second side of the slots share a first gate line. The same row of pixel units on both sides share a second gate line. The first gate drive circuit drives the pixel units in the first display area through a plurality of first gate lines, and the second gate drive circuit drives the pixel units in the second display area through a plurality of second gate lines. The pixel units on both sides are driven by different gate drive circuits, so the pixel units in the same row on both sides of the slot do not need to share the gate line, that is, the gate line in the embodiment of the present disclosure does not need to use avoidance slots, which can reduce the cost of slotting. Depth, to achieve the purpose of mobile terminal narrow frame design. In addition, the first gate driving circuit and the second gate driving circuit are controlled by different clock signal lines, which can independently control the first display area and the second display area, realize regional control, and provide conditions for displaying different contents.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure.

FIG. 1 is a schematic structural diagram of an array substrate shown in the related art;

Fig. 2 is a schematic structural diagram of an array substrate according to an exemplary embodiment;

Fig. 3 is a schematic structural diagram of an array substrate according to another exemplary embodiment;

Fig. 4 is a schematic structural diagram of an array substrate according to yet another exemplary embodiment;

Fig. 5 is a schematic structural diagram of an array substrate according to yet another exemplary embodiment;

Fig. 6 is a schematic structural diagram of an array substrate according to yet another exemplary embodiment;

Fig. 7 is a schematic structural diagram of a mobile terminal according to an exemplary embodiment.

Detailed ways

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with aspects of the present disclosure as recited in the appended claims.

FIG. 1 is a schematic structural diagram of an array substrate shown in the related art. As shown in FIG. 1 , the array substrate 100 includes a base 101 . An edge of the base 101 is provided with a slot 102 , and some predetermined components can be placed in the slot 102 , such as at least one of a camera, a receiver, a speaker and a light sensor. A plurality of pixel units (not shown in the figure) are arranged on the substrate 101 . The above-mentioned plurality of pixel units form a display area 103 , and the shape of the display area 103 may vary with the shapes of the substrate 101 and the groove 102 .

In order to ensure the display of the pixel units on both sides of the slot 102, as shown in FIG. Extending through the hub region 104 to the second side of the slot 102 (the right side of the slot 102 in FIG. 1 ). In this way, the gate driver circuit (Gate Driver On Array, GOA) 105 can drive the gate lines 106 on both sides of the slot 102 through the gate lines 106 (in FIG. pixel unit. If the depth of the groove 102 (the width corresponding to the vertical direction of FIG. 1 ) is deep, there will be many rows of pixel units on both sides of the groove 102, and the number of corresponding gate lines 106 is also large. Larger size causes the display area below the bottom of the slot 102 to be narrowed. In other words, the area between the opening of the slot 102 and the edge 107 of the wire-collecting area 104 away from the opening is not used for display, which affects the visual appearance.

In order to solve the above problems, an embodiment of the present disclosure provides an array substrate, as shown in FIG. 2 , the array substrate 200 includes:

Base 201;

a groove 202 disposed on an edge 210 of the base 201;

A plurality of pixel units (not shown in the figure) are arranged on the substrate 201 to form a display area 203; the pixel units of the first sub-edge 211 form the first display area, and the pixel units of the second sub-edge 212 form the second display area Area, wherein, the first sub-edge 211 is the area where the edge 210 is located on the first side of the slot 202 (the left side of the slot in FIG. 2 ), and the second sub-edge 212 is the area where the edge 210 is located on the second side of the slot 202 ;

The pixel units located in the same row of the first display area share a first gate line 204 (in FIG. 2, labels G1, ..., Gk, ..., Gn are also used to highlight each gate line);

Pixel units located in the same row of the second display area share a second gate line 205;

The first gate drive circuit 207 located on the first side of the slot 202 is electrically connected to a plurality of first gate lines for driving the pixel units located in the first display area;

The second gate drive circuit 208 located on the second side of the slot 202 is electrically connected to a plurality of second gate lines for driving the pixel units located in the second display area;

A plurality of clock signal lines (represented by symbols STV1 , STV2 and STV3 in FIG. 2 ), the first gate driving circuit 207 and the second gate driving circuit 208 are controlled by different clock signal lines.

It can be understood that the edge 210 is an area corresponding to a part of the base on the base 201 . Since there is a groove in the edge 210 , for ease of understanding, it is assumed that the depth of the groove is the same as the width of the edge 210 , that is, the groove 202 will divide the edge 210 into two parts. The portion of the edge 210 located on the first side of the slot 202 is the first sub-edge 211 , and the portion of the edge 210 located on the second side of the slot 202 is the second sub-edge 212 .

It should be noted that the aforementioned pixel units in the same row share one first gate line 204, which means that the pixel units in the same row are controlled by driving signals from the same first gate line 204, while the pixel units in multiple rows are controlled by driving signals from the same first gate line 204, respectively. The driving signals of the plurality of first gate lines 204 are controlled. For the arrangement of gate lines and pixel units, reference may be made to related technologies, which are not limited in the present disclosure.

The number of pixel units can be set according to actual needs. For the convenience of understanding, a plurality of pixel units in the embodiments of the present disclosure are arranged in this way: viewed from the row direction (the left and right directions of FIG. 2 ), the pixel units are located in one row; viewed from the column direction ( 2), the pixel units are arranged in a row. It can be understood that, when the layout of the pixel units is changed, the structure of the above-mentioned array substrate will also be adjusted accordingly, but the effectiveness of the solutions of the embodiments of the present disclosure will not be affected.

In the embodiment of the present disclosure, the pixel units on both sides of the slot 202 are driven by different gate driving circuits, so the pixel units in the same row on both sides of the slot 202 may not share the gate line, that is, the gate line does not need to be avoided in the embodiment of the present disclosure. Slot 202 scheme. As shown in FIG. 2 , the width of the line gathering area 104 in the related art is d1, and the width of this area becomes d2 after adopting the solution of the embodiment of the present disclosure, that is, the width of the line gathering area 104 is reduced by d3 (ie, d1-d2), The solution of the embodiment of the present disclosure can reduce the depth of the slot, and achieve the purpose of designing a narrow frame of the mobile terminal.

Moreover, in the embodiment of the present disclosure, the first gate driving circuit and the second gate driving circuit are provided with clock signals by different clock signal lines, so that the pixel units in the first display area and the second display area can be in different timings , that is, the display area of the array substrate can form two separate display areas, so that different contents can be displayed synchronously.

In an embodiment of the present disclosure, the array substrate 200 further includes: a third display area, the third display area is composed of pixel units below the bottom of the slot 202; and the pixel units in the same row in the third display area share a third gate line 206;

The first gate driving circuit 207 is electrically connected to a plurality of third gate lines 206 for driving pixel units in the third display area.

In order to make the first display area and the third display area have different timings, the first gate driving circuit 207 in an embodiment of the present disclosure further includes a first driving unit 2071 and a second driving unit 2072 . Wherein, the first driving unit 2071 is electrically connected to a plurality of first gate lines 204 for driving the pixel units located in the first display area. The second driving unit 2072 is electrically connected to the plurality of third gate lines 206 for driving the pixel units located in the third display area.

Since the pixel units in the same row in the first sub-edge 211 share a first gate line, the pixel units in the same row in the second sub-edge 212 share a second gate line, that is, there are two gate lines in the same row on both sides of the slot 202 , if a commonly used gate drive circuit is used to output the same power, energy consumption will increase. In an embodiment of the present disclosure, the size of the gate driving circuit is adjusted to reduce the power consumption of the gate driving circuit. Since the size of the driving transistor in the gate driving circuit determines the output power of the gate driving circuit, the size of the driving transistor is reduced in the embodiments of the present disclosure. For example, the size of the driving tube in the first driving unit 2071 is smaller than the size of the driving tube in the second driving unit 2072, or the size of the driving tube in the second gate driving circuit 208 is smaller than the size of the driving tube in the second driving unit 2072, so that Not only can the area of the substrate occupied by the first driving unit and/or the second gate driving circuit be reduced, but also the output power and the power consumption of the array substrate can be reduced, and at the same time, materials can be saved and production costs can be reduced.

In an embodiment of the present disclosure, as shown in FIG. 2 , the first driving unit 2071 is disposed in an area between the base 201 and the first display area, and this area does not occupy the display area. Usually, since the second driving unit 2072 is provided in this area, the width of the above-mentioned area will not be increased after the first driving unit 2071 is installed. In this embodiment, the first gate line 204 does not need to avoid the slot 202, so that the distance between the first side of the slot 202 and the first display area can be reduced by d4, so that the display area of the first side of the slot 202 can be increased. The first display area is increased, which is beneficial to designing a narrow frame and improving visual aesthetics.

In yet another embodiment of the present disclosure, as shown in FIG. 2 , the second gate driving circuit 208 is disposed in an area between the second side of the substrate 201 and the second display area, and this area does not occupy the display area. It can be understood that when the above-mentioned area is set on the edge of the mobile terminal, the width of the second gate driving circuit 208 (the left-right direction in FIG. 2 ) can be reduced to increase its length, and this design will not occupy the area of the display area. In this embodiment, the second gate line 205 does not need to avoid the slot 202, so that the distance between the second side of the slot 202 and the second display area can be reduced by d5, so that the display area of the second side of the slot 202 can be increased. The second display area is enlarged, which is beneficial to designing a narrow frame and improving visual aesthetics.

In a specific usage scenario, in an embodiment of the present disclosure, the first drive unit 2071 and the second gate drive circuit 208 can be set up according to the layout shown in FIG. , that is, the edge of the display area 203 is as close as possible to the edge of the slot 202 , and they can overlap theoretically. In practice, a bar-shaped area as shown in FIG. 2 can be preset to facilitate welding of preset components and other components.

In practical application, the first driving unit 2071 , the second gate driving circuit 208 and the second driving unit 2072 need a clock signal line to control timing. According to the usage scenario, at least three clock signal lines are provided in this embodiment, and they are provided on both sides of the display area 203 . Taking the array substrate shown in FIG. 2 as an example, assuming that the clock signal lines STV1/STV2 are arranged between the display area 203 and the substrate 201 and on the first side of the slot 202 (the left side of the slot 202 in FIG. 2 ), the clock signal The line STV1 / STV3 is disposed between the display area 203 and the substrate 201 and on the second side of the slot 202 (the right side of the slot 202 in FIG. 2 ).

At this time, the first driving unit 2071 and the second driving unit 2072 receive the clock signal from the clock signal line STV1/STV2, and the first driving unit 2071 and the second driving unit 2072 sequentially drive the pixel units of each row through the gate line according to the preset timing. , after the data line inputs the pixel data to the pixel unit, the pixel unit displays the corresponding pixel value. Dynamic display of images in the first display area and the third display area can be realized by adjusting the frequency of the clock signal. For the principle of image display, please refer to related technologies, which will not be described in detail here.

Similarly, the second gate drive circuit 208 receives the clock signal from the clock signal line STV1/STV3, drives the pixel unit through the second gate line, and after the data line inputs the pixel data to the pixel unit, the pixel unit displays the corresponding pixel value . By adjusting the frequency of the clock signal, images can be dynamically displayed in the second display area. For the principle of image display, please refer to related technologies, which will not be described in detail here.

The above only introduces the scheme that the first driving unit 2071 and the second driving unit 2072 share the clock signal line STV1/STV2, but the second gate driving circuit 208 uses a different clock signal line STV1/STV3. Certainly, the first driving unit 2071 may be provided with a clock signal by the clock signal line STV1/STV3, while the second gate driving circuit 208 and the second driving unit 2072 are provided with clock signals by the clock signal line STV1/STV2. Alternatively, the first driving unit 2071 and the second gate driving circuit 208 provide clock signals through clock signal lines STV1/STV3, while the second driving unit 2072 provides clock signals through clock signal lines STV1/STV2. Alternatively, the first driving unit 2071 , the second gate driving circuit 208 and the second driving unit 2072 respectively provide clock signals through different clock signal lines. It is understandable that the above clock signal lines can be set to 3, 4, or even more, and those skilled in the art can adjust the layout and number of clock signal lines according to specific scenarios.

In this embodiment, when the second gate drive circuit 208 is provided on the array substrate, the clock signal line required by the second gate drive circuit 208 is provided in the area where the second gate drive circuit 208 is located, that is, the second display area. and the area between the substrate 201.

It is understandable that the wide array substrate and the resistance of the clock signal line will cause a delay when the clock signal line is transmitted from the first side of the slot to the second side. Therefore, it is necessary to adjust the timing of the clock signal so that the same clock Signals appear simultaneously on both sides of the slot. The process of adjusting the clock signal may be adjusted at the clock source. For a specific adjustment method, reference may be made to related technologies, which are not limited in the embodiments of the present disclosure.

In an embodiment of the present disclosure, as shown in FIG. 3 , a first non-display area 301 is provided on the array substrate 300, and the first non-display area 301 is an area between the first side of the groove and the first display area. . Correspondingly, the clock signal lines that provide clock signals for the first driving unit and the second driving unit extend to the first non-display area 301 .

In an embodiment of the present disclosure, as shown in FIG. 4 , a second non-display area 402 is provided on the array substrate 400, and the second non-display area 402 is an area between the second side of the groove and the second display area. . Correspondingly, the clock signal line that provides the clock signal for the second gate driving circuit extends to the second non-display area 402 .

In an embodiment, the first non-display area and the second non-display area can be set at the same time, such as the first non-display area 401 and the second non-display area 402 shown in FIG. 4 . Correspondingly, the clock signal line that provides the clock signal for the second gate driving circuit extends to the first non-display area 401 and the second non-display area 402 .

As shown in FIG. 4, taking the clock signal line STV1/STV2 on the first side of the slot 202 as an example, when the first gate drive circuit 207 is arranged in the first non-display area 401, the clock signal line STV1/STV2 includes the first A line segment 403, a second line segment (not shown in the figure) and a first connecting segment 404;

The first line segment 403 is located on the first side of the display area, and is used to provide a clock signal to the gate drive circuit (such as the second drive unit 2072 in FIG. 2 ) connected to the pixel unit below the bottom of the groove 202; the first connection segment 404 is located on the first side of the slot 202 and is parallel to the gate line, and is used to connect the first line segment 403 and the second line segment; the second line segment is located in the first non-display area, and is used to provide clocks to the first gate drive circuit Signal.

When the second gate driving circuit 208 is disposed in the second non-display area 402 , the layout of the clock signal lines STV1 / STV3 can refer to the layout of the clock signal lines STV1 / STV2 in the previous embodiment, which will not be repeated here.

In an embodiment of the present disclosure, as shown in FIG. 5, when the clock signal line STV1/STV2/STV3 is arranged on the first side of the display area 203, the clock signal line STV1/STV2 includes a first line segment 503, a first connection segment 504 and a second line segment (not shown in the figure), the clock signal line STV1/STV3 includes a third line segment 506 and a second connection segment 505;

The first line segment 503 is located on the first side of the display area (the left side of the display area in FIG. 5 ), and is used to connect the gate drive circuit to the pixel unit below the bottom of the groove 202 (such as the second drive unit in FIG. 2 ). 2072) providing a clock signal;

The first connection segment is located on the first side of the slot 202 and parallel to the gate line, for connecting the first line segment 503 and the second line segment;

The second line segment is located in the first non-display area 501 and is used to provide a clock signal to the first gate driving circuit;

The second connecting segment 505 is located in the display area below the bottom of the slot and parallel to the gate lines, for connecting the first segment 503 and the third segment 506;

The third line segment 506 is located in the second non-display area 502 and is used to provide a clock signal to the second gate driving circuit.

It can be understood that the above-mentioned second line segment is used to connect the first connecting segment 504 and the first gate driving circuit located in the first non-display area 501, and according to the actual scene, the second line segment may be parallel to the first gate line, Or perpendicular to the grid lines.

It can be understood that when the third line segment 506 provides the clock signal to the second gate drive circuit 208, the third connection segment 507 and the fourth line segment can also be set according to the position of the second gate drive circuit. The setting of the fourth line segment Reference may be made to the above-mentioned setting manner of the second line segment, which will not be described in detail here.

In an embodiment of the present disclosure, as shown in FIG. 6 , a third non-display area 601 is disposed on the array substrate 600, and a first drive unit 2071 is disposed in the third non-display area 601. The circuit of the first drive unit 2071 passes through The first gate line 204 drives the pixel units within the first sub-edge 211 (left side in FIG. 6 ). The third non-display area 601 is an area between the first sub-edge 211 and the first display area. When the first drive unit 2071 is arranged in the third non-display area 601, the area occupied by the gate lines in FIG. First, the display area becomes larger, which is beneficial to design a narrow frame and increase the display area.

In yet another embodiment of the present disclosure, as shown in FIG. 6 , a fourth non-display area 602 is disposed on the array substrate 600 , and a second gate drive circuit 208 is disposed in the fourth non-display area 602 , and the second gate The driving circuit 208 drives the pixel units in the second sub-edge 212 (the right side of the slot 202 in FIG. 6 ) through the second gate line 205 . The fourth non-display area 601 is an area between the second display area and the second sub-edge 212 . When the second gate drive circuit 208 is arranged in the fourth non-display area 602, the area occupied by the gate lines in FIG. Second, the display area becomes larger, which is conducive to designing a narrow frame and increasing the display area.

In one embodiment, the array substrate is provided with the third non-display area 601 and the fourth non-display area 602 at the same time. In this way, the grid line does not need to avoid the groove, and the edge of the display area can be as close as possible to the edge of the groove, that is, the first display area and the second display area become larger at the same time, which is conducive to designing a narrow frame and increasing the display area, improving the display area. Visual aesthetics, to achieve the technical effect of the solution shown in Figure 2.

It can be understood that, in order to make the first gate driving circuit and the second gate driving circuit work normally, in an embodiment of the present disclosure, the position of the clock signal line is adjusted according to the positions of the first gate driving circuit and the second gate driving circuit. Arrange the position so that the clock signal line provides the clock signal for the first gate drive circuit and the second gate drive circuit through the shortest path. For the specific layout method, please refer to the layout method of the clock signal line in Figure 4 and Figure 5, which will not be repeated here. Detailed Description.

It should be noted that, in order to simplify the drawings and descriptions, no data lines are mentioned in the above embodiments. In order to realize the solutions of the embodiments of the present disclosure, when the first gate driving circuit, the second gate driving circuit and the second driving unit receive the clock signal, they output the gate driving signal to each pixel unit. Correspondingly, the data line inputs the pixel data, at this time, the pixel unit displays the corresponding pixel value, and a frame of image is displayed after the pixel units of all rows are displayed once according to the preset sequence. For the principle of image display, please refer to related technologies, which will not be described in detail here.

So far, in the array substrate provided by the embodiments of the present disclosure, the pixel units on both sides of the slot are driven by different gate drive circuits, so the pixel units in the same row on both sides of the slot do not need to share a gate line, that is, the gate line in the embodiment of the present disclosure Lines do not need to use avoidance slots. According to the arrangement of the gate drive circuit, the width of the collection area in the related art can be reduced, such as the area width between the bottom edge of the slot and the display area, the area width between the first side of the slot and the display area , and the width of the area between the second side of the slot and the display area, which facilitates the design of narrow borders. In addition, the first drive unit, the second gate drive circuit, and the third drive unit are controlled by different clock signal lines, which can independently control the first display area, the second display area, and the third display area to realize sub-area control , to provide conditions for displaying different content in different display areas.

An embodiment of the present disclosure further provides a mobile terminal, which includes the array substrate and preset components provided in the foregoing embodiments. The preset component is arranged in the slot, such as at least one of a camera, a receiver, a loudspeaker and a light sensor.

As shown in FIG. 7, the mobile terminal 700 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, and the like.

7, mobile terminal 700 may include one or more of the following components: processing component 702, memory 704, power supply component 706, multimedia component 708, audio component 710, input/output (I/O) interface 712, sensor component 714 , and the communication component 716.

The processing component 702 generally controls the overall operations of the mobile terminal 700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. Processing component 702 may include one or more processors 720 to execute instructions.

Additionally, processing component 702 may include one or more modules that facilitate interaction between processing component 702 and other components. For example, processing component 702 may include a multimedia module to facilitate interaction between multimedia component 708 and processing component 702 .

The memory 704 is configured to store various types of data to support operations at the mobile terminal 700 . Examples of such data include instructions for any application or method operating on the mobile terminal 700, contact data, phonebook data, messages, pictures, videos, and the like. The memory 704 can be realized by any type of volatile or non-volatile storage device or their combination, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable Programmable Read Only Memory (EPROM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Magnetic Memory, Flash Memory, Magnetic or Optical Disk.

The power supply component 706 provides power to various components of the mobile terminal 700 . Power components 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for mobile terminal 700 .

The multimedia component 708 includes a screen providing an output interface between the mobile terminal 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense a boundary of a touch or swipe action, but also detect duration and pressure associated with the touch or swipe action. In some embodiments, the multimedia component 708 includes a front camera and/or a rear camera. When the mobile terminal 700 is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capability.

The audio component 710 is configured to output and/or input audio signals. For example, the audio component 710 includes a microphone (MIC), which is configured to receive an external audio signal when the mobile terminal 700 is in operation modes, such as a call mode, a recording mode and a voice recognition mode. Received audio signals may be further stored in memory 704 or sent via communication component 716 . In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

The I/O interface 712 provides an interface between the processing component 702 and a peripheral interface module, which may be a keyboard, a click wheel, a button, and the like. These buttons may include, but are not limited to: a home button, volume buttons, start button, and lock button.

The sensor component 714 includes one or more sensors for providing various aspects of status assessment for the mobile terminal 700 . For example, the sensor component 714 can detect the open/closed state of the mobile terminal 700, the relative positioning of components, such as the display and the keypad of the mobile terminal 700, the sensor component 714 can also detect the mobile terminal 700 or a mobile terminal 700 Changes in the positions of components, presence or absence of user contact with the mobile terminal 700 , orientation or acceleration/deceleration of the mobile terminal 700 and temperature changes of the mobile terminal 700 . Sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. Sensor assembly 714 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 714 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor or a temperature sensor.

The communication component 716 is configured to facilitate wired or wireless communication between the mobile terminal 700 and other devices. The mobile terminal 700 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology and other technologies.

In an exemplary embodiment, the mobile terminal 700 may be powered by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Programmable gate array (FPGA), controller, microcontroller, microprocessor or other electronic implementation.

In an exemplary embodiment, there is also provided a non-transitory computer-readable storage medium including instructions, such as the memory 704 including instructions, which are executable by the processor 720 of the mobile terminal 700 . For example, the non-transitory computer readable storage medium may be ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like.

Other embodiments of the disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, and these modifications, uses or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure . The specification and examples are to be considered exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It should be understood that the present disclosure is not limited to the precise constructions which have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (16)

1. An array substrate, characterized in that the array substrate comprises: base; a slot disposed on an edge of the base; A plurality of pixel units are arranged on the substrate to form a display area; wherein the pixel units of the first sub-edge constitute the first display area, and the pixel units of the second sub-edge constitute the second display area, wherein the first sub-edge an edge is an area of the edge on a first side of the slot, and the second sub-edge is an area of the edge on a second side of the slot; The pixel units located in the same row of the first display area share a first gate line; The pixel units located in the same row of the second display area share a second gate line; a first gate drive circuit located on the first side of the slot, electrically connected to a plurality of the first gate lines, and used to drive the pixel units located in the first display area; a second gate drive circuit located on the second side of the slot, electrically connected to a plurality of the second gate lines, and used to drive the pixel units located in the second display area; A plurality of clock signal lines, the first gate drive circuit and the second gate drive circuit are controlled by different clock signal lines. 2. The array substrate according to claim 1, wherein a third display area is provided on the array substrate, and the third display area is composed of pixel units below the bottom of the slot; Pixel units in the same row in the three display areas share a third gate line; The first gate driving circuit is electrically connected to a plurality of the third gate lines for driving pixel units in the third display area. 3. The array substrate according to claim 2, wherein the first gate drive circuit comprises a first drive unit and a second drive unit; The first driving unit is electrically connected to a plurality of the first gate lines for driving pixel units located in the first display area; The second driving unit is electrically connected to a plurality of the third gate lines for driving pixel units located in the third display area. 4. The array substrate according to claim 3, wherein the size of the driving tube in the first driving unit is smaller than the size of the driving tube in the second driving unit. 5 . The array substrate according to claim 3 , wherein the size of the driving transistor in the second gate driving circuit is smaller than the size of the driving transistor in the second driving unit. 6. The array substrate according to claim 3, wherein the second driving unit is disposed on the first side of the slot. 7. The array substrate according to claim 1, wherein a first non-display area is disposed on the array substrate, and a first driving unit is disposed in the first non-display area; The first non-display area is an area between the slot and the first display area. 8. The array substrate according to claim 7, wherein the plurality of clock signal lines are arranged between the display area and the substrate, and extend to the first non-display area. 9. The array substrate according to claim 1, wherein a second non-display area is disposed on the array substrate, and the second gate driving circuit is disposed in the second non-display area; The second non-display area is an area between the slot and the second display area. 10. The array substrate according to claim 9, wherein the plurality of clock signal lines are arranged between the display area and the substrate, and extend to the second non-display area. 11. The array substrate according to claim 1, wherein a third non-display area is arranged on the array substrate, and a first driving unit is arranged in the third non-display area; The third non-display area is an area between the first display area and the first sub-edge. 12. The array substrate according to claim 11, wherein the plurality of clock signal lines are arranged between the display area and the substrate, and extend to the third non-display area. 13. The array substrate according to claim 1, wherein a fourth non-display area is arranged on the array substrate, and the second gate driving circuit is arranged in the fourth non-display area; The fourth non-display area is an area between the second display area and the second sub-edge. 14. The array substrate according to claim 13, wherein the plurality of clock signal lines are arranged between the display area and the substrate, and extend to the fourth non-display area. 15. A mobile terminal, comprising the array substrate according to any one of claims 1 to 14 and a preset component, wherein the preset component is arranged in a slot. 16. The mobile terminal according to claim 15, wherein the preset component comprises at least one of a camera, a receiver, a speaker and a light sensor.