CN210200744U

CN210200744U - Solar cell

Info

Publication number: CN210200744U
Application number: CN201920953937.9U
Authority: CN
Inventors: Jiyu Liu; 刘继宇; Hua Li; 李华
Original assignee: Taizhou Lerri Solar Technology Co Ltd
Current assignee: Taizhou Longi Solar Technology Co Ltd
Priority date: 2019-06-24
Filing date: 2019-06-24
Publication date: 2020-03-27
Anticipated expiration: 2029-06-24

Abstract

The application discloses a solar cell, which comprises a silicon substrate and a grid line electrode formed on the silicon substrate; the gate line electrode includes: a first metal layer formed directly on the silicon substrate, the first metal layer containing nickel atoms; a second metal layer stacked on the first metal layer; the second metal layer contains cobalt atoms; and a third metal layer laminated on the second metal layer; the third metal layer contains copper atoms. The application improves the diffusion barrier effect of the first metal layer.

Description

Solar cell

Technical Field

The utility model relates to a photovoltaic field, concretely relates to photovoltaic power generation field especially relates to a solar cell.

Background

The cost reduction of solar cells depends mainly on the improvement of cell efficiency and the reduction of the cost of cell manufacturing materials. In recent years, the demand for silver paste substitutes in the field of solar cells is increasing day by day, and the price of copper is only about one percent of that of silver, so that the material cost of the solar cell can be greatly reduced by replacing a silver electrode with a copper electrode.

Since copper is easily diffused into silicon, recombination centers are formed in a silicon substrate, and the photoelectric conversion efficiency and the service life of the crystalline silicon solar cell are reduced.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks or deficiencies in the prior art, it is desirable to provide a solar cell.

In a first aspect, the present invention provides a solar cell, including a silicon substrate and a gate line electrode formed on the silicon substrate;

the gate line electrode includes:

a first metal layer formed directly on the silicon substrate, the first metal layer containing nickel atoms;

a second metal layer stacked on the first metal layer; the second metal layer contains cobalt atoms;

and a third metal layer laminated on the second metal layer; the third metal layer contains copper atoms.

The solar cell is provided with the second metal layer and the first metal layer below the third metal layer; the second metal layer is cobalt or alloy thereof, which can effectively prevent copper atoms from entering the silicon substrate, thereby avoiding forming a recombination center; the first metal layer is nickel or an alloy thereof, and can further prevent copper atoms from entering the silicon substrate to form a second barrier; and after the nickel atoms enter the silicon substrate, nickel silicide is formed between the nickel atoms and the silicon substrate, so that good ohmic contact can be realized, the resistance between the grid line electrode and the silicon substrate is further reduced, and the battery performance is favorably improved.

Optionally, the third metal layer further contains at least one of silver, tin, zinc, nickel, and tungsten.

Optionally, the second metal layer is a cobalt-phosphorus alloy, and the second metal layer contains at least 10 atomic% of phosphorus.

Optionally, the second metal layer is a cobalt-tungsten alloy, and the second metal layer contains at least 2 atomic% of tungsten.

Optionally, the second metal layer is a cobalt-tungsten-phosphorus alloy, the second metal layer contains at least 2 atomic% of phosphorus, and the second metal layer contains at least 15 atomic% of tungsten.

Optionally, the thickness of the second metal layer is less than 5 μm.

Optionally, a dielectric layer is formed on one side of the silicon substrate, an opening region is formed on the dielectric layer to expose the silicon substrate, and the first metal layer is at least formed in the opening region.

Optionally, the third metal layer protrudes from the surface of the dielectric layer from the film opening region, and extends to the surface of the dielectric layer on both sides of the film opening region.

Optionally, the first metal layer covers the bottom surface and the side surfaces of the film opening region, and extends to the surface of the dielectric layer on both sides of the film opening region.

Optionally, an extension length of the first metal layer on the surface of the dielectric layer along one direction is less than or equal to half of the width of the open film region.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present invention, in which a dielectric layer is formed on a silicon substrate;

fig. 2 is a schematic structural diagram of a solar cell according to an embodiment of the present invention, in which an open film region is formed in a dielectric layer;

fig. 3 is a schematic structural diagram of a solar cell according to an embodiment of the present invention, in which a first metal layer is formed in an opening region;

fig. 4 is a schematic structural diagram of a solar cell according to an embodiment of the present invention, in which a second metal layer is formed on a first metal layer;

fig. 5 is a schematic structural diagram of a solar cell according to an embodiment of the present invention forming a third metal layer on the second metal layer;

fig. 6 is a schematic structural diagram of a solar cell according to an embodiment of the present invention, illustrating the removal of the redundant first metal layer on the dielectric layer;

fig. 7 is a schematic structural diagram of a solar cell according to an embodiment of the present invention, illustrating the removal of the excess second metal layer on the dielectric layer;

fig. 8 is a schematic structural diagram of the solar cell according to an embodiment of the present invention, illustrating the removal of the redundant third metal layer on the dielectric layer.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In one embodiment of the present invention, please refer to fig. 1-5, a solar cell includes a silicon substrate 10 and a gate line electrode formed on the silicon substrate 10;

the gate line electrode includes:

a first metal layer 30 directly formed on the silicon substrate 10, the first metal layer 30 containing nickel atoms;

a second metal layer 40 laminated on the first metal layer 30; the second metal layer 40 contains cobalt atoms;

and a third metal layer 50 laminated on the second metal layer 40; the third metal layer 50 contains copper atoms.

The solar cell is provided with the second metal layer and the first metal layer below the third metal layer; the second metal layer is cobalt or alloy thereof, the solid-phase solubility of copper atoms in cobalt is very low, and the copper atoms can be effectively prevented from entering the silicon substrate, so that a recombination center is prevented from being formed; the first metal layer is nickel or an alloy thereof, and can further prevent copper atoms from entering the silicon substrate to form a second barrier; and after the nickel atoms enter the silicon substrate, nickel silicide is formed between the nickel atoms and the silicon substrate, so that good ohmic contact can be realized, the resistance between the grid line electrode and the silicon substrate is further reduced, and the battery performance is favorably improved.

The silicon substrate 10 is a core component of the solar cell, the silicon substrate 10 may be a monocrystalline silicon wafer or a polycrystalline silicon wafer, and the silicon substrate 10 may be formed by one or more processes of texturing, diffusing, forming a doped polycrystalline silicon layer, forming a tunneling layer, and the like, through the silicon wafer.

In order to further improve the performance of the solar cell, it is preferable that a dielectric layer 20 is formed on one side of the silicon substrate 10, an open film region 21 is disposed on the dielectric layer 20 to expose the silicon substrate 10, and a first metal layer 30 is formed at least in the open film region 21. The first metal layer 30 makes electrical contact with the silicon substrate through the open film region 21.

The material of the dielectric layer may be, but is not limited to, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, silicon oxycarbide, aluminum oxide, aluminum oxynitride, or aluminum oxycarbide. The dielectric layer may be a single layer or a multi-layer structure. The open film region may be formed by performing a photolithography or etching process on the dielectric layer.

In a preferred embodiment of the present invention, the first metal layer 30 comprises at least 50% nickel. This ensures that good nickel silicide is formed to achieve good ohmic contact while effectively blocking copper atoms from entering the silicon substrate. The first metal layer may include any one or more of aluminum, silver, manganese, titanium, chromium, vanadium, tantalum, tungsten, ruthenium, germanium, zinc, rhodium, platinum, palladium, hafnium, molybdenum, niobium, antimony, iridium, indium, and tin, in addition to nickel. Of course, it is understood that the first metal layer is a pure nickel layer.

The first metal is deposited on the silicon substrate, then annealing treatment is carried out, so that nickel silicide is formed on one side of the first metal layer, which is in contact with the silicon substrate, ohmic contact can be formed between the first metal layer and the silicon substrate, the potential barrier of a contact interface of the metal and the semiconductor is reduced, and the series resistance is reduced.

The second metal layer is arranged between the first metal layer and the third metal layer, and the second metal layer is combined with the first metal layer to prevent copper atoms in the third metal layer from diffusing to the silicon substrate, so that the diffusion blocking effect is improved.

In one embodiment, the second metal layer comprises at least 90% cobalt, such that the solid phase solubility of copper atoms in the second metal layer is further reduced, further effectively blocking copper atoms from entering the silicon substrate.

In another embodiment, the second metal layer 40 is a cobalt-phosphorus alloy, and the second metal layer 40 contains at least 10 atomic% phosphorus.

In yet another embodiment, the second metal layer 40 is a cobalt tungsten alloy, and the second metal layer 40 comprises at least 2 atomic% tungsten.

In yet another embodiment, the second metal layer 40 is an alloy of cobalt, tungsten and phosphorus, the second metal layer 40 includes at least 2 atomic percent phosphorus, and the second metal layer 40 includes at least 15 atomic percent tungsten.

Further, the second metal layer 40 is less than 5 microns thick. Therefore, a good blocking effect can be ensured, and the resistance of the whole grid line electrode can be reduced.

The third metal layer may be a copper layer or a copper alloy layer. When the third metal layer 50 is a copper alloy layer, it may further contain at least one of silver, tin, zinc, nickel, and tungsten.

Preferably, a masking layer is further formed on the side of the third metal layer opposite to the second metal layer, and the masking layer is silver or tin. The capping layer may enhance corrosion resistance and weldability of the third metal layer. The thickness of the masking layer is preferably less than 2 microns.

The first metal layer, the second metal layer, and the third metal layer may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, electroplating, or electroless plating. The deposition process can make the first metal layer uniformly cover the bottom surface and the side surface of the film opening area. The first, second, and third metal layers may be formed by different deposition processes, or may be formed by the same deposition process but with different deposition parameters such as pressure, deposition rate, temperature, etc.

In one embodiment, referring to fig. 3, the first metal layer 30 covers the bottom surface and the side surfaces of the open film region 21 and extends to the surface of the dielectric layer 20 on the back and both sides of the open film region 21. That is, the deposition area of the first metal layer 30 is not limited to the open film area 21, but extends to both sides of the open film area 21, so that the surface of the dielectric layer 20 on the back both sides of the open film area 21 is covered with the first metal layer 30.

Further, the extension length of the first metal layer 30 on the surface of the dielectric layer 20 along one direction is less than or equal to one-half of the width of the film opening region 21. Optionally, an extension length of the first metal layer on the surface of the dielectric layer along one direction is less than or equal to one fifth of the width of the open film region.

Similarly, referring to fig. 4, the second metal layer may be the same as the first metal layer, and the deposition area is not limited to the film opening area 21, but extends to both sides of the film opening area 21, so that the surfaces on the back sides of the film opening area 21 are also covered with the second metal layer 40.

Further, the extension length of the second metal layer on the surface of the dielectric layer along one direction is less than or equal to half of the width of the film opening area. Optionally, an extension length of the second metal layer on the surface of the dielectric layer along one direction is less than or equal to one fifth of the width of the film opening area.

Similarly, the third metal layer 50 protrudes from the surface of the dielectric layer 20 in the opening region 21 and extends to the surface of the dielectric layer 20 on both sides of the opening region 21. That is, the surface of the third metal layer 50 is higher than the surface of the dielectric layer 20, and the third metal layer 50 does not cover the open film region 21 but covers the dielectric film 20 on both sides of the open film region 21. Similarly, the extension length of the third metal layer on the surface of the dielectric layer along one direction is less than or equal to half of the width of the open film area. Optionally, an extension length of the third metal layer on the surface of the dielectric layer along one direction is less than or equal to one fifth of the width of the film opening area.

The electrode grid line has a simple process, can form an electrode with a large area, and improves the conductivity of the electrode.

In another embodiment, referring to fig. 8, the gate line electrode is limited to the open film region 21 and extends to the dielectric layer on both sides of the open film region 21. Therefore, the area of a single electrode is reduced, the shielding of the electrode on the solar cell is small, and meanwhile, more electrodes can be arranged on the solar cell, so that the arrangement of the electrodes is tighter, and the current transmission distance is reduced.

The redundant first metal layer, second metal layer and third metal layer on the dielectric layer can be removed by a mechanical grinding or chemical etching process, and only the first metal layer, second metal layer and third metal layer at the membrane opening region 21 remain.

Wherein, after forming the first metal layer, the excess first metal layer on the dielectric layer can be removed, and the result is shown in fig. 6; after forming the second metal layer, removing the excess second metal layer on the dielectric layer, and the result is shown in fig. 7; after the third metal layer is formed, the excess third metal layer on the dielectric layer is removed, and the result is shown in fig. 8. After the first metal layer, the second metal layer and the third metal layer are formed, the redundant first metal layer, the second metal layer and the third metal layer on the dielectric layer can be removed together. And arranging a mask plate on the surface of one side of the dielectric layer, which is opposite to the silicon substrate, or performing directional precise deposition to ensure that the first metal layer, the second metal layer and the third metal layer do not extend on the dielectric layer.

Of course, it is understood that the present invention may not be provided with a dielectric layer.

It should be noted that all the drawings only show the case of the front gate line electrode, and the back gate line electrode can be understood by reference.

The utility model also provides a manufacturing approach of above-mentioned solar cell, including following step:

forming a first metal layer on a silicon substrate; the first metal layer contains nickel atoms;

forming a second metal layer on the first metal layer; the second metal layer contains cobalt atoms;

forming a third metal layer on the second metal layer; the third metal layer contains copper atoms.

Further, annealing the silicon substrate 10 formed with the first metal layer 30 is performed, so that nickel in the first metal layer 30 and the silicon substrate 10 form nickel silicide.

Further, the annealing temperature is 500-800 ℃.

In the embodiment of the present invention, the first metal layer may be annealed once at a temperature of 500-. The first metal layer can also be annealed twice, wherein the first annealing temperature is 500-550 ℃, and the second annealing temperature is 700-800 ℃. The two annealing treatments can effectively inhibit ion diffusion, reduce damage to the silicon substrate, ensure that the generated metal silicide has small resistivity and uniform property, and can form smooth appearance of the metal silicide and the silicon substrate.

In an embodiment of the present invention, the second metal layer and the first metal layer are disposed below the third metal layer; the second metal layer is cobalt or alloy thereof, the solid-phase solubility of copper atoms in cobalt is very low, and the copper atoms can be effectively prevented from entering the silicon substrate, so that a recombination center is prevented from being formed; the first metal layer is nickel or an alloy thereof, and can further prevent copper atoms from entering the silicon substrate to form a second barrier; and after the nickel atoms enter the silicon substrate, nickel silicide is formed between the nickel atoms and the silicon substrate, so that good ohmic contact can be realized, the resistance between the grid line electrode and the silicon substrate is further reduced, and the battery performance is favorably improved.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be understood by those skilled in the art that the scope of the present invention is not limited to the specific combination of the above-mentioned features, but also covers other embodiments formed by any combination of the above-mentioned features or their equivalents without departing from the spirit of the present invention. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A solar cell is characterized by comprising a silicon substrate and a grid line electrode formed on the silicon substrate;

the gate line electrode includes:

2. The solar cell of claim 1, wherein the third metal layer further comprises at least one of silver, tin, zinc, nickel, and tungsten.

3. The solar cell of claim 1, wherein the second metal layer is a cobalt-phosphorus alloy, and the second metal layer comprises at least 10 atomic percent phosphorus.

4. The solar cell of claim 1, wherein the second metal layer is a cobalt tungsten alloy, the second metal layer comprising at least 2 atomic% tungsten.

5. The solar cell of claim 1, wherein the second metal layer is a cobalt tungsten phosphorous alloy, the second metal layer comprises at least 2 atomic percent phosphorous, and the second metal layer comprises at least 15 atomic percent tungsten.

6. The solar cell of claim 1, wherein the second metal layer is less than 5 microns thick.

7. The solar cell of claim 1, wherein a dielectric layer is formed on one side of the silicon substrate, an opening region is formed on the dielectric layer to expose the silicon substrate, and the first metal layer is formed at least in the opening region.

8. The solar cell of claim 7, wherein the third metal layer protrudes from the open film region beyond the surface of the dielectric layer and extends to the surface of the dielectric layer on both sides of the open film region.

9. The solar cell of claim 7, wherein the first metal layer covers a bottom surface and a side surface of the open film region and extends to the surface of the dielectric layer on both sides of the open film region.

10. The solar cell of claim 9, wherein the first metal layer has an extension length along one direction on the surface of the dielectric layer of less than or equal to one half of the width of the open film region.