CN211906256U - 电子系统 - Google Patents

电子系统 Download PDF

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Publication number
CN211906256U
CN211906256U CN201921606117.9U CN201921606117U CN211906256U CN 211906256 U CN211906256 U CN 211906256U CN 201921606117 U CN201921606117 U CN 201921606117U CN 211906256 U CN211906256 U CN 211906256U
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CN
China
Prior art keywords
memory
information
processor
cache
piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn - After Issue
Application number
CN201921606117.9U
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English (en)
Chinese (zh)
Inventor
S·梅斯热
S·布里尼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
STMicroelectronics Grenoble 2 SAS
Original Assignee
STMicroelectronics Rousset SAS
STMicroelectronics Grenoble 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of CN211906256U publication Critical patent/CN211906256U/zh
Withdrawn - After Issue legal-status Critical Current
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201921606117.9U 2018-09-26 2019-09-25 电子系统 Withdrawn - After Issue CN211906256U (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1858771 2018-09-26
FR1858771A FR3086409A1 (fr) 2018-09-26 2018-09-26 Procede de gestion de la fourniture d'informations, en particulier des instructions, a un microprocesseur et systeme correspondant

Publications (1)

Publication Number Publication Date
CN211906256U true CN211906256U (zh) 2020-11-10

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Family Applications (2)

Application Number Title Priority Date Filing Date
CN201921606117.9U Withdrawn - After Issue CN211906256U (zh) 2018-09-26 2019-09-25 电子系统
CN201910912337.2A Active CN110955386B (zh) 2018-09-26 2019-09-25 管理向微处理器提供诸如指令的信息的方法和对应的系统

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201910912337.2A Active CN110955386B (zh) 2018-09-26 2019-09-25 管理向微处理器提供诸如指令的信息的方法和对应的系统

Country Status (4)

Country Link
US (1) US11275589B2 (fr)
EP (1) EP3629185B1 (fr)
CN (2) CN211906256U (fr)
FR (1) FR3086409A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110955386A (zh) * 2018-09-26 2020-04-03 意法半导体(格勒诺布尔2)公司 管理向微处理器提供诸如指令的信息的方法和对应的系统

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4811215A (en) * 1986-12-12 1989-03-07 Intergraph Corporation Instruction execution accelerator for a pipelined digital machine with virtual memory
US5848432A (en) * 1993-08-05 1998-12-08 Hitachi, Ltd. Data processor with variable types of cache memories
US5826109A (en) * 1994-01-04 1998-10-20 Intel Corporation Method and apparatus for performing multiple load operations to the same memory location in a computer system
US6516384B1 (en) * 1999-12-30 2003-02-04 Intel Corporation Method and apparatus to perform a round robin and locking cache replacement scheme
US20060075211A1 (en) * 2002-03-21 2006-04-06 Martin Vorbach Method and device for data processing
US8171225B2 (en) * 2007-06-28 2012-05-01 Intel Corporation Cache for a multi thread and multi core system and methods thereof
EP2271989A1 (fr) * 2008-04-22 2011-01-12 Nxp B.V. Circuit de multitraitement comportant des circuits de mémoire cache qui permettent l'écriture vers des lignes de cache non précédemment chargées
US8261019B2 (en) * 2009-02-13 2012-09-04 Oracle America, Inc. Conveying critical data in a multiprocessor system
KR101635395B1 (ko) * 2010-03-10 2016-07-01 삼성전자주식회사 멀티포트 데이터 캐시 장치 및 멀티포트 데이터 캐시 장치의 제어 방법
US8504777B2 (en) * 2010-09-21 2013-08-06 Freescale Semiconductor, Inc. Data processor for processing decorated instructions with cache bypass
KR20130057890A (ko) * 2011-11-24 2013-06-03 시게이트 테크놀로지 인터내셔날 하이브리드 드라이브 및 그 데이터 전송 방법
US11514001B2 (en) * 2018-04-17 2022-11-29 EMC IP Holding Company LLC Concurrent computations operating on same data for CPU cache efficiency
FR3086409A1 (fr) * 2018-09-26 2020-03-27 Stmicroelectronics (Grenoble 2) Sas Procede de gestion de la fourniture d'informations, en particulier des instructions, a un microprocesseur et systeme correspondant

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110955386A (zh) * 2018-09-26 2020-04-03 意法半导体(格勒诺布尔2)公司 管理向微处理器提供诸如指令的信息的方法和对应的系统
CN110955386B (zh) * 2018-09-26 2023-09-01 意法半导体(格勒诺布尔2)公司 管理向微处理器提供诸如指令的信息的方法和对应的系统

Also Published As

Publication number Publication date
EP3629185B1 (fr) 2024-06-26
EP3629185A1 (fr) 2020-04-01
US11275589B2 (en) 2022-03-15
CN110955386A (zh) 2020-04-03
CN110955386B (zh) 2023-09-01
FR3086409A1 (fr) 2020-03-27
US20200097294A1 (en) 2020-03-26

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