CN217007767U - Photoelectric packaging structure - Google Patents

Abstract

An embodiment of the present application provides an optoelectronic package structure, including: a light-conducting element; and a photonic integrated circuit having an active surface on which the photosensor is located and a passive surface on which the light-conducting element is disposed, and the light-conducting element and the photosensor face each other through a through-hole located in the photonic integrated circuit. The present invention is directed to a photoelectric package structure, which at least solves the problem of light dissipation.

Description

Photoelectric package structure

technical field

Embodiments of the present invention relate to optoelectronic packaging structures.

Background technique

In the existing silicon photonics (SiPh) packaging structure, light propagates from a fiber array unit (FAU) to a photonic integrated circuit (PIC) and needs to change its travel direction through a mirror before entering the photoelectric sensor of the PIC ( photo sensor), the optical coupling efficiency will be affected by the refraction of the mirror and the deviation of the light reflection angle, so that the energy of the light entering the PIC will be attenuated.

Utility model content

In view of the problems existing in the related art, the purpose of the present invention is to provide an optoelectronic packaging structure to at least solve the problem of light dissipation.

An embodiment of the present application provides an optoelectronic packaging structure, including: a light conducting element; a photonic integrated circuit having an active surface and a passive surface, a photoelectric sensor is located on the active surface, the light conducting element is arranged on the passive surface, and The light conducting element and the photosensor face each other through through holes in the photonic integrated circuit.

In some embodiments, the light conducting element is a fiber array unit (FAU).

In some embodiments, the lateral dimension of the through hole gradually decreases in the direction from the passive face to the photosensor.

In some embodiments, the material of the photonic integrated circuit includes silicon.

In some embodiments, the sidewalls of the through holes may reflect light.

In some embodiments, the active surface of the photonic integrated circuit includes a grating in the through hole, and the distance from the grating to the photosensor is smaller than the distance from the grating to the passive surface.

In some embodiments, the light emitted by the light conducting element may directly reach the grating.

In some embodiments, it further includes: a circuit layer, the photonic integrated circuit is located above the circuit layer and is electrically connected with the circuit layer through the first connection member, and the photoelectric sensor is located between the circuit layer and the photonic integrated circuit.

In some embodiments, it further includes: an electronic integrated circuit connected to the active surface of the photonic integrated circuit through a second connection member, the electronic integrated circuit and the photoelectric sensor are arranged side by side, and the electronic integrated circuit is located between the photonic integrated circuit and the circuit layer , the electronic integrated circuit is electrically connected with the circuit layer through the photonic integrated circuit.

In some embodiments, the method further includes: a first filling layer located between the circuit layer and the photonic integrated circuit, the first filling layer covering the first connecting member and the second connecting member.

In some embodiments, the method further includes: a second filling layer located between the electronic integrated circuit and the photonic integrated circuit, the second filling layer covering the second connecting member; a first filling layer located between the circuit layer and the photonic integrated circuit, the electronic integrated circuit Between the integrated circuits, the first filling layer covers the second filling layer and the first connecting piece.

In some embodiments, it further includes: an electronic integrated circuit located on the circuit layer, the electronic integrated circuit is electrically connected to the circuit layer through the third connection member and the photonic integrated circuit is electrically connected to the circuit layer through the circuit layer.

In some embodiments, the method further includes: a first filling layer located between the circuit layer and the photonic integrated circuit and the electronic integrated circuit, the first filling layer covering the first connecting member and the second connecting member.

In some embodiments, the sidewalls of the first filling layer are coplanar with the sidewalls of the wiring layer.

In some embodiments, the method further includes: a third filling layer covering the sidewall of the photonic integrated circuit and the upper surface of the first filling layer not covered by the photonic integrated circuit.

In some embodiments, the first fill layer also coats the sidewalls of the photonic integrated circuit.

In some embodiments, it further includes: a fourth filling layer encapsulating the light conducting element, the photonic integrated circuit and the first filling layer.

In some embodiments, the light conducting element is bonded to the passive side of the photonic integrated circuit by an adhesive layer.

In some embodiments, the photosensor is located directly below the light conducting element.

In some embodiments, both ends of the through hole are completely covered by the light conducting element and the photosensor, respectively.

Description of drawings

Figure 1 shows a prior art optoelectronic package.

2 to 26 illustrate the formation process of optoelectronic packages according to some embodiments of the present application.

27-33 illustrate optoelectronic packages according to various embodiments of the present application.

Figure 34 shows a carrier according to some embodiments of the present application.

Detailed ways

In order to better understand the spirit of the embodiments of the present application, further descriptions are given below with reference to some preferred embodiments of the present application.

Embodiments of the present application will be described in detail below. Throughout the specification of the present application, the same or similar components and components having the same or similar functions are denoted by similar reference numerals. The embodiments described herein with respect to the figures are illustrative, diagrammatic, and intended to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limitations of the present application.

As used herein, the terms "substantially," "substantially," "substantially," and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs proximately. For example, when used in conjunction with a numerical value, a term may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, Less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values is less than or equal to ±10% of the mean of the values (eg, less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values are considered to be "substantially" the same.

In this specification, unless otherwise specified or limited, relative terms such as: "central", "longitudinal", "lateral", "front", "rear", "right" of", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below" , "above," "below," "top," "bottom," and terms derived therefrom (eg, "horizontally," "downward," "upward," etc.) should be construed as references Orientation described in the discussion or depicted in the drawings. These relative terms are used for convenience of description only and do not require that the application be constructed or operated in a particular direction.

In addition, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is for convenience and brevity, and that it is to be flexibly construed to include not only the values expressly designated as the limits of the range, but also all individual values or subranges subsumed within the stated range, as if expressly Specify each numerical value and subrange generically.

Also, for ease of description, "first," "second," "third," etc. may be used herein to distinguish between different components of a figure or series of figures. "First," "second," "third," etc. are not intended to describe corresponding components.

FIG. 1 shows the existing silicon photonics (SiPh) package structure, in which the light guided by the FAU 10 to the PIC 12 is turned from the horizontal to the vertical, and in the vertical direction, there is also a fan-out circuit between the mirror 14 and the PIC 12 The additional distance due to the thickness of 18, the light path is long, and the transmission of light is affected by the refractive index and reflectivity index of the mirror 14 due to the use of the substrate 16, the FAU 10 at the edge above the substrate 16, and the mirror 14. The size (horizontal and vertical) of the entire package is larger.

The optoelectronic packaging structure of the present application will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 2 , a plurality of photosensors 22 are formed on the PIC board 20 , and a plurality of first pads 24 are formed around the photosensors 22 .

Referring to FIG. 3 , the first carrier 30 coated with the first buffer layer/release layer 32 is covered on the PIC board 20 , and the first release layer 32 covers the photosensor 22 and the first pad 24 . The first carrier 30 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The first carrier 30 may be a wafer (round wafer/square wafer), so that a plurality of package structures can be simultaneously formed on the first carrier 30 . The first release layer 32 may be formed of a polymer-based material, which may be removed together with the first carrier 30 from the overlying structure to be formed in a subsequent step. In some embodiments, the first release layer 32 is an epoxy-based thermal release material that loses its adhesion when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the first release layer 32 may be an ultraviolet (UV) glue, which loses its adhesive properties when exposed to UV light. The first release layer 32 may be dispensed and cured in liquid form, may be a laminate film laminated to the first carrier 30, or the like. The top surface of the first release layer 32 may be horizontal and may have a high flatness.

Referring to FIG. 4, the structure shown in FIG. 3 is reversed, and a first mask layer 40 is formed on the PIC board 20, and the first mask layer 40 is exposed in the direction indicated by the arrow. In some embodiments, the first mask layer 40 is photoresist (PR), and the first mask layer 40 is formed by performing a lamination process.

Referring to FIG. 5 , the first mask layer 40 is developed to form first openings 51 , which correspond to the photosensors 22 in one-to-one correspondence. A chemical etching process 52 is performed on the PIC board 20 exposed by the first opening 51 .

Referring to FIG. 6, after the chemical etching process 52 is performed, the first opening 51 extends into the PIC board 20 to form the through hole 50, and the PIC board 20 has not been etched through. The first mask layer 40 on the PIC board 20 is removed, and the second mask layer 60 is formed on the PIC board 20, and the second mask layer 60 located at the bottom of the through hole 50 is patterned in the direction shown by the arrow ( For example, by a photolithographic process) in the shape of a fence/grid. In some embodiments, the second mask layer 60 is photoresist (PR), and the second mask layer 60 is formed by performing a lamination process. In some embodiments, the material of the PIC board 20 where the through hole 50 is etched is Si. Due to the material properties of silicon, the sidewall of the through hole 50 is inclined after the etching is completed (the sidewall forms an acute angle with the horizontal plane). The angle is 10° to 80°), the lateral dimension of the through hole 50 gradually decreases from top to bottom, and the sidewall of the through hole 50 can reflect light to minimize the loss of optical signal.

Referring to FIG. 7 , the upper part of FIG. 7 shows a partial enlarged view at the position of the through hole 50 . A chemical etching process 71 is performed on the PIC board 20 exposed by the second mask layer 60 at the bottom of the through hole 50 to transfer the pattern of the second mask layer 60 to the PIC board 20 to form the grating 80 shown in FIG. 8 , The grating 80 has a plurality of micro-holes (μHoles), the distance from the grating 80 to the photosensor 22 is smaller than the distance from the grating 80 to the passive surface of the PIC board 20 (the upper surface as shown in FIG. 8 ), and the grating 80 contacts the photosensor twenty two.

Referring to FIG. 8 , the first carrier 30 and the first release layer 32 are peeled off from the PIC board 20 in the directions indicated by the arrows, leaving the photosensors 22 and the first pads 24 .

Referring to FIG. 9 , the structure left in FIG. 8 is turned over, and the electronic integrated circuit (EIC) 90 is electrically connected to the PIC board 20 , and the second pad 94 on the EIC 90 is bonded to the first pad through the micro bump (μbump) 92 twenty four. In some embodiments, EIC 90 has a length/width of tens or hundreds of microns and a thickness of 20 to 200 microns. In some embodiments, the diameter of the microbumps 92 is 10 to 30 micrometers, and the pitch between adjacent microbumps 92 is 15 to 60 micrometers. The side where the EIC 90 is located is the active side of the PIC board 20 .

Referring to FIG. 10 , the entire structure is tilted and a second fill layer 100 is filled between the PIC board 20 and the EIC 90 to protect the second connectors (microbumps 92 ) for electrically connecting the PIC board 20 and the EIC 90 . In some embodiments, the second fill layer 100 is an underfill material.

Referring to FIG. 11A, a singulation process (eg, dicing) is performed on the PIC board 20 to form the singulated PIC 110 as shown in FIG. 11B. Each PIC 110 has a corresponding photosensor 22 and EIC 90 thereon. In some embodiments, the PIC 110 has a length/width of tens or hundreds of microns and a thickness of 20 to 200 microns.

Referring to FIG. 12 , third pads 122 are formed on the second carrier 120 . In some embodiments, the second carrier 120 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The second carrier 120 may be a wafer (round wafer/square wafer), so that a plurality of package structures can be simultaneously formed on the second carrier 120 . A release layer similar to the first release layer 32 may be coated on the second carrier 120 .

Referring to FIG. 13, a first dielectric layer 130 is formed on the second carrier 120, and the first dielectric layer 130 is exposed in the direction indicated by the arrow. In some embodiments, the first dielectric layer 130 is a polyamide (PA) material layer, and the first dielectric layer 130 is formed by performing a lamination process.

Referring to FIG. 14 , the first dielectric layer 130 is developed to expose the third pads 122 , and a first seed layer 140 is formed on the first dielectric layer 130 and the exposed third pads 122 . In some embodiments, the material of the first seed layer 140 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, combinations thereof, or the like. The first seed layer 140 may be formed using a physical vapor deposition (PVD) process.

Referring to FIG. 15, a third mask layer 150 is formed on the first seed layer 140, and the third mask layer 150 is exposed in the direction indicated by the arrow. In some embodiments, the third mask layer 150 is photoresist (PR), and the third mask layer 150 is formed by performing a lamination process.

Referring to FIG. 16 , the third mask layer 150 is developed to expose the first seed layer 140 , and a first metal layer 160 is formed on the exposed first seed layer 140 . In some embodiments, the material of the first metal layer 160 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, combinations thereof, or the like. The first metal layer 160 may be formed using processes such as Physical Vapor Deposition (PVD), sputtering, electroplating, electroless (E'less) and/or printing, lamination and/or potting.

Referring to FIG. 17, the third mask layer 150 is removed. And the first seed layer 140 is patterned using the first metal layer 160 as a mask.

Referring to FIG. 18 , the steps similar to FIGS. 13 to 17 are repeated to form a second dielectric layer 180 , a third dielectric layer 182 and a second seed layer 184 located therein and thereon on the first dielectric layer 130 , respectively. , a second metal layer 185 , a third seed layer 186 , and a third metal layer 187 . In some embodiments, the material of the second metal layer 185 and the third metal layer 187 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys or combinations thereof, and the like. The second metal layer 185, the third metal layer 185, and the third metal layer 185 may be formed using processes such as Physical Vapor Deposition (PVD), sputtering, electroplating, electroless (E'less), and/or printing, lamination, and/or potting. Layer 187.

Referring to FIG. 19 , a fourth seed layer 190 is formed on the third dielectric layer 182 and the third metal layer 187 . In some embodiments, the material of the fourth seed layer 190 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, combinations thereof, or the like. The fourth seed layer 190 may be formed using a Physical Vapor Deposition (PVD) process.

Referring to FIG. 20, a fourth mask layer 200 is formed on the fourth seed layer 190, and the fourth mask layer 200 is exposed in the direction indicated by the arrow. In some embodiments, the fourth mask layer 200 is photoresist (PR), and the fourth mask layer 200 is formed by performing a lamination process.

21 , the fourth mask layer 200 is developed to expose the fourth seed layer 190, and a fourth metal layer 210 and a first solder 212 are formed on the exposed fourth seed layer 190, and the fourth metal layer 210 is formed as Conductive pillars, and the thickness/height of the conductive pillars is 80 microns to 200 microns. In some embodiments, the material of the fourth metal layer 210 may be Cu, Au, Ag, Al, Pd, Pt, Ni, alloys thereof, combinations thereof, or the like. The fourth metal layer 210 may be formed using processes such as Physical Vapor Deposition (PVD), sputtering, electroplating, electroless (E'less) and/or printing, lamination and/or potting. In some embodiments, the material of the first solder 212 includes Sn, anisotropic conductive paste (ACP) or anisotropic conductive film (ACF).

Referring to FIG. 22, the fourth mask layer 200 is removed. And the fourth seed layer 190 is patterned using the first metal layer 160 and the first solder 212 as a mask. So far, the circuit layer 220 of the present application is formed. In some embodiments, the thickness of each dielectric layer in the wiring layer 220 is 5 micrometers to 20 micrometers. The thickness of each metal layer in the circuit layer 220 is 1 to 20 microns, and the thickness of each seed layer is 0.1 to 1 micron. The materials of each dielectric layer in the circuit layer 220 may be organic substances, for example, polyimide (PI), epoxy resin (epoxy), polybenzoxazole (PBO), flame retardant grade 4 material ( FR4), semi-cured resin (prepreg, PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT); or/and inorganic substances such as silicon, glass , ceramics, oxides (eg, SiOx, TaOx), nitrides (eg, SiNx), and the like. In some embodiments, various dielectric layers in the wiring layer 220 are formed using processes such as deposition, lamination, printing, potting, dipping, etc., and organic photosensitive materials and/or non-photosensitive liquid and/or dry film materials are used. In some embodiments, copper, gold, silver, aluminum, titanium, nickel, palladium (Pd), platinum (Pt), and nickel alloys may be used for each metal layer and each seed layer.

Referring to FIG. 23 , the singulated PIC 110 to be formed in FIG. 11 is inverted and the first pad 24 is bonded to the first solder 212 .

Referring to FIG. 24 , the entire structure is tilted, and a first filling layer 240 is filled between the wiring layer 220 and the PIC 110 and the EIC 90 to protect the first connection (the fourth metal layer) for electrically connecting the PIC 110 and the wiring layer 220 210, the first solder 212), to fix the relative positions between the components to avoid warping of the structure, and also to reduce environmental disturbances (such as moisture, oxidation, vibration or noise). The first filling layer 240 and the second filling layer 100 may be organic substances, for example, polyimide (PI), epoxy resin (epoxy), polybenzoxazole (PBO), flame retardant grade 4 material (FR4 ), semi-cured resin (prepreg, PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT); or/and inorganic substances such as silicon, glass, Ceramics, oxides (eg, SiOx, TaOx), nitrides (eg, SiNx), and the like. In some embodiments, the first filling layer 240 and the second filling layer 100 are formed using processes such as deposition, lamination, printing, potting, dipping, etc., and organic photosensitive materials and/or non-photosensitive liquid and/or dry film materials are used .

25, the FAU 250 is attached to the passive side (back side) of the PIC 110 through the adhesive layer 252, then the second carrier 120 is removed, the light emitted by the FAU 250 reaches the photosensor 22 of the PIC 110 through the through hole 50. In some embodiments, the thickness of the adhesive layer 252 is 10 microns to 50 microns. The adhesive layer 252 may be an organic substance, for example, polyimide (PI), epoxy resin (epoxy), polybenzoxazole (PBO), flame retardant grade 4 material (FR4), semi-cured resin (prepreg , PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT); or/and inorganic substances such as silicon, glass, ceramics, oxides (eg, SiOx, TaOx), nitrides (eg, SiNx), and the like. In some embodiments, the adhesion layer 252 is formed using deposition, lamination, printing, potting, dipping, etc. processes, and employs organic photosensitive materials and/or non-photosensitive liquid and/or dry film materials.

Referring to FIG. 26 , the structure shown in FIG. 25 is reversed, and the second solder 260 is formed on the third pad 122 , and after a reflow process, the second solder 260 is formed into solder balls. In some embodiments, the diameter of the solder balls is 30 microns to 200 microns, and the pitch between adjacent solder balls is 50 microns to 400 microns. Figures 12 to 26 illustrate the structure of one unit. In actual production, the structures of multiple units are formed together, and a singulation process is performed after the step of Figure 26 to form a unit of optoelectronic package as shown in the figure. The structure 2600, therefore, the sidewalls of the first filling layer 240 and the sidewalls of the wiring layer 220 are coplanar.

FIG. 27 shows a different embodiment from FIG. 26 , in which the EIC 90 is directly bonded to the wiring layer 220 through a third connection (solder) 370 and is electrically connected to the PIC 110 through the wiring layer 220 .

FIG. 28 shows a different embodiment from FIG. 26 . In FIG. 28 , a third filling layer 280 is further included, covering the sidewall of the photonic integrated circuit 110 and the part of the first filling layer 240 not covered by the photonic integrated circuit 110 . upper surface. The third filling layer 280 may be an organic substance, for example, polyimide (PI), epoxy resin (epoxy), polybenzoxazole (PBO), flame retardant grade 4 material (FR4), semi-cured resin ( prepreg, PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT); or/and inorganic substances such as silicon, glass, ceramics, oxides (e.g. , SiOx, TaOx), nitrides (eg, SiNx), etc. In some embodiments, the third filling layer 280 is formed using deposition, lamination, printing, potting, dipping, etc. processes, and employs organic photosensitive materials and/or non-photosensitive liquid and/or dry film materials.

FIG. 29 shows a different embodiment from FIG. 28 . In FIG. 29 , the first filling layer 240 is not included, and the third filling layer 280 is located between the PIC 110 and the wiring layer 220 and covers the sidewalls of the PIC 110 .

FIG. 30 shows a different embodiment from FIG. 26 . In FIG. 30 , the second filling layer 100 is not included, and the first filling layer 240 is located between the PIC 110 and the wiring layer 220 , and between the PIC 110 and the EIC 90 .

FIG. 31 shows a different embodiment from FIG. 26 . In FIG. 31 , it further includes: a fourth filling layer 310 encapsulating the light conducting element (FAU 250 ), the photonic integrated circuit PIC 110 and the first filling layer 240 . The fourth filling layer 310 may be an organic substance, for example, polyimide (PI), epoxy resin (epoxy), polybenzoxazole (PBO), flame retardant grade 4 material (FR4), semi-cured resin ( prepreg, PP), Ajinomoto build-up film (ABF), bismaleimide triazine resin (BT); or/and inorganic substances such as silicon, glass, ceramics, oxides (e.g. , SiOx, TaOx), nitrides (eg, SiNx), etc. In some embodiments, the fourth filling layer 310 is formed using deposition, lamination, printing, potting, dipping, etc. processes, and employs organic photosensitive materials and/or non-photosensitive liquid and/or dry film materials.

FIG. 32 shows a different embodiment from FIG. 26. In the cross-sectional view of the optoelectronic package of FIG. 32, there are two sets of FAUs 250 and PICs 110 on the circuit layer 220 in one-to-one correspondence.

FIG. 33 shows a different embodiment from that shown in FIG. 26 , in which an interposer 330 is used instead of the conductive pillar/fourth metal layer 210 shown in FIG. 26 .

FIG. 34 shows a square panel level (PNL) carrier 3700 and a circular wafer level (WL) carrier 3702. In some embodiments, a plurality of EICs 90 of the present application can be arranged on the PNL carrier 3700 or WL carrier 3702, and then multiple EICs 90 are transferred to the PIC 110 (PIC board 20) of multiple units together. batch transfer to form the optoelectronic packaging structure of the present application in batches. The PIC and EIC are bonded by PNL (or WL) and flip-chip process, and placed on the surface of the fan-out wiring layer (fan-out redistribution layer) 220, and interconnected by solder/micro bumps, lower cost can be achieved And avoids the Known Good Die (KGD) loss problem.

The embodiment of the present invention has the function of receiver (Rx), the photoelectric sensor 22 is arranged on the active surface of the PIC 110, the FAU 250 is arranged on the back of the PIC 110, and directly faces through the through hole 50, and is emitted by the FAU 250 The light can reach the grating 80 directly, and the two ends of the through hole 50 are completely covered by the FAU 250 and the photoelectric sensor 22 respectively, so that the through hole 50 is kept in an unopened state to avoid environmental interference. Embodiments of the present application provide well-performing silicon photonics (SiPh) packaging applications, providing a direct (shortest) optical path from the FAU 250 to the PIC 110, which is located above the PIC 110 rather than at the edge of the structure as in the prior art , reducing the size of the optoelectronic packaging structure 2600 . The through hole 50 is provided in the PIC 110, and the through hole 50, the grating 80, and the photoelectric sensor 22 are located directly under the FAU 250, and the mirror in the prior art is not required to avoid loss of optical signals. The circuit layer of the embodiment of the present application adopts a thin circuit design, for example, the line width/spacing (L/S) < 2 μm/2 μm, so that the number of input/output (I/O) is more, and the traditional substrate is not required, Thus, package miniaturization and low cost are achieved. In the structure of the present application, multiple functional devices (multilayer structure of wiring layer 220, EIC 90, PIC 110 with grating 80 on the backside, and FAU 250) are integrated.

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. For those skilled in the art, the present utility model may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (10)

1. an optoelectronic packaging structure, is characterized in that, comprises: light-conducting elements; A photonic integrated circuit has an active surface and a passive surface, a photoelectric sensor is located on the active surface, the light conducting element is arranged on the passive surface, and the light conducting element is located on the photonic integrated circuit The through holes in the photoelectric sensor face each other. 2. The optoelectronic packaging structure of claim 1, wherein the light conducting element is a fiber array unit (FAU). 3 . The optoelectronic packaging structure according to claim 1 , wherein a lateral dimension of the through hole gradually decreases along a direction from the passive surface to the photosensor. 4 . 4 . The optoelectronic packaging structure according to claim 3 , wherein the sidewalls of the through holes can reflect light. 5 . 5. The optoelectronic packaging structure according to claim 1, wherein the active surface of the photonic integrated circuit comprises a grating located in the through hole, and the distance from the grating to the photoelectric sensor is less than the distance from the grating to the passive surface. 6. The optoelectronic packaging structure according to claim 5, wherein the light emitted by the light conducting element can directly reach the grating. 7. The optoelectronic packaging structure according to claim 1, further comprising: A circuit layer, the photonic integrated circuit is located above the circuit layer and is electrically connected to the circuit layer through a first connection member, and the photoelectric sensor is located between the circuit layer and the photonic integrated circuit. 8. The optoelectronic packaging structure according to claim 7, further comprising: An electronic integrated circuit is connected to the active surface of the photonic integrated circuit through a second connector, the electronic integrated circuit is arranged side by side with the photoelectric sensor, and the electronic integrated circuit is located between the photonic integrated circuit and the photonic integrated circuit. Between the circuit layers, the electronic integrated circuit is electrically connected to the circuit layer through the photonic integrated circuit. 9. The optoelectronic packaging structure according to claim 7, further comprising: An electronic integrated circuit is located on the circuit layer, the electronic integrated circuit is electrically connected to the circuit layer through a third connection member and the photonic integrated circuit is electrically connected to the circuit layer through the circuit layer. 10 . The optoelectronic packaging structure according to claim 1 , wherein both ends of the through hole are completely covered by the light conducting element and the photoelectric sensor, respectively. 11 .

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