CN222995403U - Alignment mark and semiconductor structure - Google Patents
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- CN222995403U CN222995403U CN202421561593.4U CN202421561593U CN222995403U CN 222995403 U CN222995403 U CN 222995403U CN 202421561593 U CN202421561593 U CN 202421561593U CN 222995403 U CN222995403 U CN 222995403U
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Abstract
The utility model provides an alignment mark and a semiconductor structure, which are applied to the technical field of semiconductor photoetching, and particularly can comprise a first mark pattern, a second mark pattern and a third mark pattern which are sequentially stacked and arranged in different pattern layers from bottom to top along a first direction vertical to the surface of a substrate, wherein at least one of the first mark pattern, the second mark pattern and the third mark pattern is overlapped with projections of other mark patterns in the first direction; the alignment between the multiple pattern layers is realized through the mark patterns arranged on the different pattern layers, and the substrate occupation area of the alignment mark in the first direction is reduced by utilizing the mode that the mark patterns in at least one pattern layer of the three pattern layers overlap with the projections of the mark patterns in other pattern layers in the first direction, namely, the alignment precision is ensured, and meanwhile, the effective wiring of the substrate and the manufacturing efficiency of the semiconductor structure are improved.
Description
Technical Field
The present utility model relates to the field of semiconductor lithography, and in particular, to an alignment mark and a semiconductor structure.
Background
Semiconductor Integrated Circuit (IC) fabrication involves forming multiple pattern layers on a semiconductor wafer. Each layer must be aligned with the previous layer(s) to allow the IC to function properly. Various marks, such as alignment marks, may be used to align the layers during the manufacturing process.
However, in order to improve the overlay accuracy, the number of alignment marks arranged on the existing semiconductor wafer is too large, so that the occupied area of the alignment area on the substrate is larger, and the effective wiring area of the substrate (or the substrate) is reduced.
Disclosure of utility model
The utility model aims to provide a novel structure of an alignment mark and a semiconductor structure, so as to save the effective wiring area of a substrate occupied by the alignment mark.
In order to solve the above technical problems, the present utility model provides a semiconductor structure, which specifically includes:
A substrate;
The pattern layer can comprise a first pattern layer, a second pattern layer and a third pattern layer which are sequentially stacked from bottom to top along a first direction;
An alignment mark comprising a first mark pattern disposed in the first pattern layer, a second mark pattern disposed in the second pattern layer, and a third mark pattern disposed in the third pattern layer;
Wherein, in the first direction, at least one of the first, second and third marking patterns at least partially overlaps with projections of the other marking patterns.
In some alternative examples, the first, second, and third marking patterns may include rectangular block, rectangular frame, or grid set markings, respectively.
In some alternative examples, the rectangular frame-type mark may include a closed rectangular frame-type pattern or an unsealed rectangular frame-type pattern surrounded by four rectangular mark bars, and the grid-bar group mark may include a plurality of grid-bar block-type mark bars or a plurality of grid-bar frame-type mark bars.
In some alternative examples, the first mark pattern and the second mark pattern may be rectangular frame marks, and the third mark pattern may be a grid bar group mark or a rectangular block mark extending along a second direction perpendicular to the first direction, wherein the shape of the first mark pattern and the second mark pattern after projection overlapping in the first direction is a zigzag shape, and the width of the third mark pattern in the second direction is greater than the width of the first mark pattern and the second mark pattern in the second direction.
In some alternative examples, the second mark pattern and the third mark pattern may be rectangular frame marks, the first mark pattern may be rectangular block marks extending along a second direction perpendicular to the first direction, wherein the shape of the second mark pattern and the third mark pattern after being overlapped by projection in the first direction is a zigzag shape, and the width of the first mark pattern in the second direction is larger than the width of the second mark pattern and the third mark pattern in the second direction.
In some alternative examples, the first pattern layer may include two first mark patterns, which are respectively located at both ends of the same diagonal line of the rectangular frame.
In some alternative examples, the second pattern layer may include four second mark patterns, and the four second mark patterns may enclose a rectangular frame and be located at four corners of the rectangular frame, respectively.
In some alternative examples, the third pattern layer may include two third mark patterns, where the two third mark patterns enclose a discontinuous L-shaped frame and are respectively located on two borders of the discontinuous L-shaped frame, and a notch is located at a corner of the discontinuous L-shaped frame.
In some alternative examples, the first pattern layer may include four first marking patterns, the four first marking patterns are grouped in pairs to form two rectangular block structures, the two rectangular block structures are respectively located at two ends of the same diagonal line of the rectangular frame, and two first marking patterns in each rectangular block structure are arranged at intervals along the third direction, and the third direction is perpendicular to the second direction and is in the same plane.
In some alternative examples, at least one of the first, second and third marking patterns may include a plurality of sets of repeating patterns, respectively, which may be arranged in parallel at intervals along the second or third direction.
In a second aspect, based on the same concept, the present utility model also provides an alignment mark, which may include:
A substrate;
A first mark pattern disposed on the substrate;
a second mark pattern disposed on the first mark pattern;
A third mark pattern disposed on the second mark pattern;
Wherein, in a first direction perpendicular to the substrate, at least one of the first, second and third marker patterns at least partially overlaps with the projection of the remaining two.
In some alternative examples, the first, second, and third marking patterns may include rectangular block, rectangular frame, or grid set markings, respectively.
In some alternative examples, the rectangular frame-type mark may include a closed rectangular frame-type pattern or an unsealed rectangular frame-type pattern surrounded by four rectangular mark bars, and the grid-bar group mark may include a plurality of grid-bar block-type mark bars or a plurality of grid-bar frame-type mark bars.
In some alternative examples, the first mark pattern and the second mark pattern are rectangular frame marks, the third mark pattern is a grid bar group mark or a rectangular block mark extending along a second direction perpendicular to the first direction, the shape of the first mark pattern and the second mark pattern after projection overlapping in the first direction is a Chinese character 'hui', and the width of the third mark pattern in the second direction is larger than the width of the first mark pattern and the second mark pattern in the second direction.
In some alternative examples, the second mark pattern and the third mark pattern are rectangular frame marks, the first mark pattern is a rectangular block mark extending along a second direction perpendicular to the first direction, the shape of the second mark pattern and the third mark pattern after being overlapped by projection in the first direction is a Chinese character 'hui', and the width of the first mark pattern along the second direction is larger than the width of the second mark pattern and the third mark pattern along the second direction.
In some alternative examples, the first pattern layer includes two first mark patterns, and the two first mark patterns may be located at two ends of the same diagonal line of the rectangular frame, respectively.
In some alternative examples, the second pattern layer may include four second mark patterns, and the four second mark patterns may enclose a rectangular frame and be located at four corners of the rectangular frame, respectively.
In some alternative examples, the third pattern layer may include two third mark patterns, where the two third mark patterns enclose a discontinuous L-shaped frame and are respectively located on two borders of the discontinuous L-shaped frame, and a notch is located at a corner of the discontinuous L-shaped frame.
In some alternative examples, the first pattern layer may include four first marking patterns, the four first marking patterns are grouped in pairs to form two rectangular block structures, the two rectangular block structures are respectively located at two ends of the same diagonal line of the rectangular frame, and two first marking patterns in each rectangular block structure are arranged at intervals along the third direction, and the third direction is perpendicular to the second direction and is in the same plane.
In some alternative examples, at least one of the first, second and third marking patterns may include a plurality of sets of repeating patterns, respectively, which are arranged in parallel at intervals along the second or third direction.
Compared with the prior art, the utility model has at least the following technical effects:
As described above, the alignment mark and the semiconductor structure provided by the utility model comprise a first mark pattern, a second mark pattern and a third mark pattern which are arranged in different pattern layers along a first direction vertical to a substrate surface, wherein at least one of the first mark pattern, the second mark pattern and the third mark pattern is overlapped with projections of other mark patterns in the first direction; the alignment between the multiple pattern layers is realized through the mark patterns arranged on the different pattern layers, and the substrate occupation area of the alignment mark in the first direction is reduced by utilizing the mode that the mark patterns in at least one pattern layer of the three pattern layers overlap with the projections of the mark patterns in other pattern layers in the first direction, namely, the alignment precision is ensured, and meanwhile, the effective wiring of the substrate and the manufacturing efficiency of the semiconductor structure are improved.
Drawings
Fig. 1 is a top view of one example of a first pattern of indicia disposed within a first pattern layer provided in some embodiments of the utility model.
Fig. 2 is a top view of another example of a first marker pattern disposed within a first pattern layer provided in some embodiments of the utility model.
Fig. 3 is a top view of another example of a first marker pattern disposed within a first pattern layer provided in some embodiments of the utility model.
Fig. 4 is a top view of one example of a second pattern of indicia disposed within a second pattern layer provided in some embodiments of the present utility model.
Fig. 5 is a top view of another example of a second marker pattern disposed within a second pattern layer provided in some embodiments of the utility model.
Fig. 6 is a top view of one example of a third pattern of indicia disposed within a third pattern layer provided in some embodiments of the present utility model.
Fig. 7 is a top view of another example of a third pattern of indicia disposed within a third pattern layer provided in some embodiments of the present utility model.
Fig. 8 is a top view of another example of a third pattern of indicia disposed within a third pattern layer provided in some embodiments of the present utility model.
Fig. 9 is a top view of another example of a third pattern of indicia disposed within a third pattern layer provided in some embodiments of the present utility model.
Fig. 10 is a top view of an example of a semiconductor structure or alignment mark provided in some embodiments of the utility model.
Fig. 11 is a top view of another example of a semiconductor structure or alignment mark provided in some embodiments of the utility model.
Fig. 12 is a top view of another example of a semiconductor structure or alignment mark provided in some embodiments of the utility model.
Fig. 13 is a top view of another example of a semiconductor structure or alignment mark provided in some embodiments of the utility model.
Fig. 14 is a top view of another example of a semiconductor structure or alignment mark provided in some embodiments of the utility model.
Fig. 15 is a partial top view of the semiconductor structure or alignment mark shown in fig. 10 and a corresponding relationship between the partial top view and the cross-sectional view.
Detailed Description
The following specific examples are presented to illustrate the present utility model, and those skilled in the art will readily appreciate the additional advantages and capabilities of the present utility model as disclosed herein. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model.
For convenience of unified description, the present utility model defines a first direction, a second direction and a third direction, and defines directions D1, D2 and D3 in the drawing of the specification, wherein the first direction corresponds to D1 in the drawing of the specification (hereinafter abbreviated as a first direction D1), the first direction D1 is a direction along a surface of a substrate, the substrate is a base material for forming the semiconductor structure or the alignment mark according to the present utility model, the second direction corresponds to D2 in the drawing of the specification (hereinafter abbreviated as a second direction D2), the second direction D2 is perpendicular to the first direction D1, a plane in which the second direction D2 is located is also perpendicular to a plane in which the first direction D1 is located, and the third direction corresponds to D3 in the drawing of the specification (hereinafter abbreviated as a third direction D3), and the third direction D3 is perpendicular to both the second direction D2 and the first direction D1 and the third direction D3 is located in the same plane as the second direction D2.
For the sake of convenience of observation, the semiconductor structure and the alignment mark provided by the present utility model will be described in detail by first showing the mark patterns on different pattern layers with different specification drawings, and then combining them in the same specification drawings.
Referring to fig. 1 to 3, fig. 1 to 3 are top views illustrating three examples of a first mark pattern disposed in a first pattern layer according to some embodiments of the present utility model. As shown in fig. 1 to 3, in the semiconductor structure and the alignment mark in the present utility model, multiple sets of repeated patterns may be disposed in a first pattern layer, and any one set of repeated patterns disposed in the first pattern layer may be referred to as a first mark pattern, for example, two (two sets) or four (four sets) first mark patterns may be disposed in the first pattern layer, specifically, when the first pattern layer includes two first mark patterns, the two first mark patterns are disposed at two ends of the same diagonal line of the rectangular frame, and when the first pattern layer includes four first mark patterns, the four first mark patterns are disposed in two sets to form two rectangular block structures, and the two rectangular block structures are disposed at two ends of the same diagonal line of the rectangular frame, respectively, and two first mark patterns in each rectangular block structure are disposed at intervals along the third direction D3.
As shown in fig. 1, as an example, the shape of each of the two first mark patterns in the first pattern layer may be a closed rectangular frame pattern in the rectangular frame marks, and the lengths of the four frames of the closed rectangular frame pattern along the second direction D2 and the third direction D3 may be the same or different, and in the present utility model, the lengths of the four frames are preferably set to be the same.
As another example, as shown in fig. 2, the shape of each of the two first mark patterns in the first pattern layer may be an unsealed rectangular frame pattern surrounded by four rectangular mark strips in the rectangular frame mark, and the lengths of the four rectangular mark strips along the second direction D2 or the third direction D3 may be the same or different, and in the present utility model, the lengths of the four rectangular mark strips are preferably set to be the same.
As another example, as shown in fig. 3, the four first mark patterns in the first pattern layer may be rectangular block marks, and the lengths of the four rectangular block marks along the second direction D2 and the third direction D3 may be the same or different, and in the present utility model, the lengths of the four rectangular mark strips are preferably set to be the same.
Referring to fig. 4 to 5, fig. 4 to 5 are top views of two examples of the second mark patterns disposed in the second pattern layer according to some embodiments of the present utility model. As shown in fig. 4 to 5, in the semiconductor structure and the alignment mark in the present utility model, a plurality of sets of repeated patterns may be disposed in the second pattern layer, and any one set of repeated patterns disposed in the second pattern layer is referred to as a second mark pattern, and illustratively, four (four sets of) second mark patterns may be disposed in the second pattern layer, and the four second mark patterns may enclose a rectangular frame and be disposed at four corners of the rectangular frame, and specifically, the four second mark patterns may be a closed rectangular frame pattern in the rectangular frame marks, or one of non-closed rectangular frame patterns enclosed by four rectangular mark strips in the rectangular frame marks.
As shown in fig. 4, as an example, the shape of each of the four second mark patterns in the second pattern layer may be a closed rectangular frame pattern, and the lengths of the four frames of the closed rectangular frame pattern along the second direction D2 and the third direction D3 may be the same or different, and in the present utility model, the lengths of the four frames are preferably set to be the same.
As another example, as shown in fig. 5, the four second mark patterns in the second pattern layer may be in the shape of an unsealed rectangular frame pattern surrounded by four rectangular mark strips, and the lengths of each rectangular mark strip in the unsealed rectangular frame pattern may be the same or different along the second direction D2 and the third direction D3, and in the present utility model, the lengths of the four rectangular mark strips in each unsealed rectangular frame pattern are preferably set to be the same.
Referring to fig. 6 to fig. 9, fig. 6 to fig. 9 are top views illustrating four examples of third mark patterns disposed in a third pattern layer according to some embodiments of the present utility model. As shown in fig. 6 to 9, in the semiconductor structure and the alignment mark in the present utility model, multiple sets of repeated patterns may be disposed in a third pattern layer, and any one set of repeated patterns disposed in the third pattern layer may be referred to as a third mark pattern, for example, two (two sets of) third mark patterns may be disposed in the third pattern layer, and the two third mark patterns may enclose a discontinuous L-shaped frame and be disposed on two rims of the discontinuous L-shaped frame, where a notch is disposed at a corner of the discontinuous L-shaped frame, or the two third mark patterns may be disposed on two ends of the same diagonal line of the rectangular frame, and in particular, the two third mark patterns may be closed rectangular frame patterns in the rectangular frame mark, and at least one of a plurality of grid block mark strips or a plurality of grid block mark strips in the grid block mark.
As shown in fig. 6, as an example, the two third mark patterns in the third pattern layer may be rectangular block marks, and the lengths of the rectangular block marks along the second direction D2 or the third direction D3 may be the same or different, and in the present utility model, it is preferable to set the lengths of the two rectangular block marks of the two third mark patterns to be the same.
As another example, as shown in fig. 7, the shapes of the two third mark patterns in the third pattern layer may be a plurality of grating block type mark stripes, and the lengths of the plurality of grating block type mark stripes in each of the third mark patterns may be the same or different along the second direction D2 or the third direction D3, and it is preferable to set the lengths of the plurality of grating block type mark stripes in each of the third mark patterns to be the same in the present utility model.
As another example, as shown in fig. 8, the shapes of the two third mark patterns in the third pattern layer may be a plurality of grid frame mark strips, and the lengths of the plurality of grid frame mark strips in each third mark pattern may be the same or different along the second direction D2 or the third direction D3, and it is preferable to set the lengths of the plurality of grid frame mark strips in each third mark pattern to be the same in the present utility model.
As another example, as shown in fig. 9, the shape of each of the two third mark patterns in the third pattern layer may be a closed rectangular frame pattern, and the lengths of the four frames of any one of the closed rectangular frame patterns in each of the third mark patterns may be the same or different along the second direction D2 and the third direction D3, and in the present utility model, the lengths of the four frames are preferably set to be the same.
Based on the various patterns of the first mark pattern, the second mark pattern and the third mark pattern shown in fig. 1-9, the following embodiments of the present utility model can be used to form the alignment mark and the semiconductor structure including the alignment mark shown in fig. 10-14.
Referring to fig. 10, fig. 10 is a top view of an alignment mark formed based on the first, second and third mark patterns shown in fig. 1, 4 and 6 and an example of a semiconductor structure including the alignment mark according to some embodiments of the present utility model. As shown in fig. 10, when the first, second and third marking patterns are closed rectangular frame patterns and the third marking pattern is a rectangular block-type marking extending in a second direction D2 or a third direction D3 perpendicular to the first direction D1, at least one of the first, second and third marking patterns at least partially overlaps with projections of the other marking patterns in the first direction D1, specifically, the shape of the first and second marking patterns after the projection of the first and second marking patterns in the first direction D1 is a zigzag shape, and the width of the third marking pattern in the second or third direction D2 or D3 is larger than the width of the first and second marking patterns in the second or third direction D2 or D3, that is, the width of the third marking pattern in the second or third direction D2 or D3 spans the first and second marking patterns.
Referring to fig. 11 or 12, fig. 11 or 12 is a top view of an example of an alignment mark formed based on the first mark pattern, the second mark pattern, and the third mark pattern shown in fig. 1, 4, and 7 (or fig. 8) and a semiconductor structure including the alignment mark according to some embodiments of the present utility model. As shown in fig. 11 or 12, when the first mark pattern, the second mark pattern, and the third mark pattern are a closed rectangular frame pattern, and the plurality of grid block type mark strips or the plurality of grid frame type mark strips in the grid strip group type mark extending along the second direction D2 or the third direction D3 perpendicular to the first direction D1, at least one of the first mark pattern, the second mark pattern, and the third mark pattern at least partially overlaps with the projection of the other mark pattern in the first direction D1, specifically, the shape of the overlapped first mark pattern and the second mark pattern in the first direction D1 is a zigzag shape, and the width of the third mark pattern in the second direction D2 or the third direction D3 is larger than the width of the first mark pattern and the second mark pattern in the second direction D2 or the third direction D3, that is, i.e., the width of the third mark pattern and the third mark pattern in the second direction D2 or the third direction D3 is larger than the width of the first mark pattern and the third mark pattern in the third direction D3.
Referring to fig. 13, fig. 13 is a top view of an example of an alignment mark formed based on the first, second, and third mark patterns shown in fig. 2, 5, and 7 and a semiconductor structure including the alignment mark according to some embodiments of the present utility model. As shown in fig. 13, when the first mark pattern, the second mark pattern are non-closed rectangular frame patterns surrounded by four rectangular mark strips, and the third mark pattern is a plurality of grid block mark strips (of course, a plurality of grid frame mark strips) in a grid group mark extending along a second direction D2 or a third direction D3 perpendicular to the first direction D1, at least one of the first mark pattern, the second mark pattern and the third mark pattern at least partially overlaps with projections of other mark patterns in the first direction D1, specifically, the shape of the overlapped first mark pattern and the second mark pattern in the first direction D1 is a zigzag shape, and the width of the third mark pattern in the second direction D2 or the third direction D3 is larger than the width of the first mark pattern and the second mark pattern in the second direction D2 or the third direction D3, that is, the width of the third mark pattern and the third mark pattern in the third direction D2 or the third direction D3 is a shape crossing the first mark pattern and the third mark pattern in the second direction D2 or the third direction D3.
Referring to fig. 14, fig. 14 is a top view of an alignment mark formed based on the first, second and third mark patterns shown in fig. 3, 5 and 9 and an example of a semiconductor structure including the alignment mark according to some embodiments of the present utility model. As shown in fig. 14, when the second mark pattern and the third mark pattern are closed rectangular frame patterns (of course, the second mark pattern and the third mark pattern may also be non-closed rectangular frame patterns surrounded by four rectangular mark strips), the first mark pattern is a rectangular block mark extending along a second direction D2 or a third direction D3 perpendicular to the first direction D1, wherein the shape of the second mark pattern and the third mark pattern after being overlapped by projection in the first direction D1 is a zigzag shape, and the width of the first mark pattern along the second direction D2 or the third direction D3 is larger than the width of the second mark pattern and the third mark pattern along the second direction D2 or the third direction D3.
It will be understood that, if the present utility model refers to the enclosed rectangular frame pattern and the non-enclosed rectangular frame pattern surrounded by the four rectangular mark strips collectively as the rectangular frame marks, and refers to the plurality of grid block mark strips and the plurality of grid frame mark strips collectively as the grid group mark, as can be seen from fig. 11 to 14 provided in this embodiment, the first mark pattern, the second mark pattern and the third mark pattern in the alignment mark and the semiconductor structure having three-layer mark patterns may be any combination of the fig. 1 to 3, the fig. 4 to 5, and the fig. 6 to 9, and fig. 11 to 14 provided in this embodiment are only preferred examples, so long as the projection of at least one of the alignment mark and the first mark pattern, the second mark pattern and the third mark pattern in the semiconductor structure and the projection of the other mark patterns in the first direction D1 are at least partially within the scope of the present utility model.
Referring to fig. 15, fig. 15 is a partial top view of the semiconductor structure or the alignment mark shown in fig. 10 and a corresponding relationship diagram of a cut-out view thereof. As shown in fig. 15, in the alignment mark and the semiconductor structure provided by the present utility model, the first mark pattern, the second mark pattern and the third mark pattern disposed along the first direction D1 are respectively located in different pattern layers or material layers, and as an example, the third pattern layer including the third mark pattern may be disposed on the second pattern layer including the second mark pattern along the first direction D1, and the second pattern layer including the second mark pattern may be disposed on the first pattern layer including the first mark pattern, but not limited thereto.
It should be understood that the methods, processes and flow steps involved in the present utility model are all prior art.
In summary, the alignment between the multiple pattern layers is realized by the mark patterns arranged on the different pattern layers, and the substrate occupation area of the alignment mark in the first direction is reduced by utilizing the overlapping mode of the mark pattern in at least one of the three pattern layers and the projection of the mark patterns positioned on other pattern layers in the first direction, namely, the effective wiring area of the substrate and the manufacturing efficiency of the semiconductor structure are improved while the alignment precision is ensured.
It should be noted that the foregoing description is merely illustrative of a preferred embodiment of the present utility model and an applied technical principle, and it should be understood by those skilled in the art that the scope of the present utility model is not limited to the specific combination of the foregoing technical features, but encompasses other technical solutions formed by any combination of the foregoing technical features or their equivalents without departing from the concept of the present utility model, such that the foregoing features and the technical features disclosed in the present utility model (but not limited to) have the similar functions and the technical features are replaced with each other.
Other technical features than those described in the specification are known to those skilled in the art, and are not further described herein to highlight the innovative features of the present utility model.
Claims (20)
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| CN202421561593.4U CN222995403U (en) | 2024-07-03 | 2024-07-03 | Alignment mark and semiconductor structure |
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| CN202421561593.4U CN222995403U (en) | 2024-07-03 | 2024-07-03 | Alignment mark and semiconductor structure |
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