CS210981B1 - Circuit for group release and locking of signals passage - Google Patents

Description

BACKGROUND OF THE INVENTION The present invention relates to wiring for group releasing and blocking the passage of signals in the field of dedicated controllers.

For the purpose of controlling production lines composed of a number of workplaces with the same or similar production process consisting of several production operations, there are no universal modular logical structures containing both logic circuits for the control of production operations in individual workplaces and on the other hand mutual interconnection of these workplaces.

These disadvantages are eliminated in their field of application by the group releasing and blocking of the signal passage according to the invention, comprising at least two sections each comprising at least two signal lines, at least two memory circuits, at least two combination circuits and at least two gates, characterized in that the first input of the first signal line of the individual section is connected to the input of the first gate of the individual section whose output is connected to the first output of the first signal line and whose control input is connected to the output of the first combinational circuit of the individual section; The sections of the section are connected, on the one hand, to the inputs of the combinational circuits of the individual section, and on the other hand, via a connecting line to the inputs of the combinational circuits of the other section.

The advantage of wiring for group releasing and covering the passage of signals according to the invention

210981 2 is the release or reimbursement of the passage of signals depending on the construction of the memory circuits in a single section, while simultaneously connecting the individual sections in sequential order, in a combined order and the like.

The wiring for group releasing and blocking the passage of signals according to the invention is shown in the attached drawing in an exemplary embodiment, where the figure shows the individual, in the order of the nth section and the next, in the order of n + 1 section. These sections are separated by a dashed line. All elements of the nth section are denoted by indices n, all elements of the n + 1 section are denoted by indices n + 1.

Each section consists of four signal lines. The first input 's _{n of the} first signal line is connected to the input of the first gate' H _n , the output of which is connected to the first output ¹ X _{n of} this first signal line. The control input of this first gate 'H _n' is o

connected to the output of the first combination circuit A _n · The second input S _{n of the} second signal line

22 is connected to the input h _{n of the} second gate 11, the output of which is connected to the second output X _n of the second signal line. The control input ² #n of this second gate ² Hn is connected to the output of the second combination circuit B _n ·

3 3

The third input S _{n of the} third signal line is connected to the input ^J h _{n of the} third gate H _n , the output of which is connected to the third output X X _n of the third signal line. The control input ^J & a of this third gate ^J Hn is coupled to the output of the third combinational circuit C _n · The fourth input ^ S _{n of the} fourth signal line is connected to the input ^ h _{n of the} fourth gate whose output is connected to the fourth output ^ X _{n of} this fourth signal line. . The control input of this fourth gate ^ H _n is connected to the output of the fourth combination circuit D _n · _v 12 3

This individual section further consists of three memory circuits P _n , P _n , P _n , with a recording 1 2 3 1 2 3 * m inputs z _n , z _n , ^J n and lubrication inputs mn, mn, ^J mn always connected to the memory circuit with identical indexes. The output of the first memory circuit p is connected to the first input ¹ a _{n of the} first combination circuit A _n , to the first input 'c _{n of the} third combination circuit C _n , to the first input' d _{n of the} fourth combination circuit D _n , and «About the line with the second input ^{and the} n +, Beer combination circuit A _{fi + 1 of the} next section.

* 2 3

The output of the second memory circuit P _n is connectable to the third input of ^J _n and the first combination circuit A _n, a first input 'b _n second combination circuit B, _Q, to the second input

2 d _{n of the} fourth combination circuit D _n , and secondly through a second connection line r _n with a second inlet 2 * p b _{n +} j of the second combination circuit 3 _n + j of the next section. Third Memory Circuit Output 3 3

P _n is connected to the third input b _{n of the} second combination circuit B _n , to the third input

3 c _{n of the} third combination circuit C _n , with the third input d _{n of the} fourth combination circuit D _n ,

2 and on the other hand through a third connection line r _n with a second input ® _{n +} , a third combination circuit C _{n +} j of another section.

2

The second input a _{Q of the} first combination circuit A _n , the second input b _{Q of the} second combination circuit B _n , and the second input c _{n of the} third combination circuit C _n are connected via the preceding signal line ¹ rn p ² rn-1, ³ r _n _ ₁ s outputs of the memory circuits of the previous section.

The next section consists of four signal lines of the palm section. The first input 's _{n + 1 of the} first signal line is connected to the input' h _{n + 1 of the} first gate 'H _{n +} p whose output is connected to the first output' x _{n +} 'of this first signal line. Control input J # _{n +} , this first

2 gates Η _β is connected to the output of the first combination circuit ^A n +, · The second input ^with n +) of the second

2 of the signal line is connected to the input h _{ft + of the} second gate whose output is connected to the second output ^2χ η + of this second signal line. Control input 3t- ² _{n +,} this second gate being connected to the output of the second combinational circuit B _{n +).}

3

The third input S _{n + of the} third signal line is connected to the input h _n + j of the third gate. The ^H n + 1 'output is connected to the third output ³ Xn + j of this third signal line. The control input ³ X-n + 1 of this third gate ³ H _{n + 1} is connected to the output of the third combination circuit (C ₊₎ . The fourth input of the fourth signal line is connected to the input of the fourth gate, the output of which is connected to the fourth output ^ ^x n + 1 of the fourth signal line. The control input of this fourth gate is coupled to the output of the fourth combination circuit.

* 1 2 3

This next section is further comprised of three memory circuits F _{n +>} ^P n + I '^ n + l' ^{is 2} ^ ^brand "multaneously inputs Zn +) ² Zn + ³ Zn +, and lubrication inlets ² MNT1 ³ »Η +, always connected to a memory circuit with identical indexes. The output of the first memory circuit ^p n + 1 is connected to the first input 'an +', the first combination circuit A _{n +)} , the first input 'c _{n +'} , the third combination circuit C _{n + 1} , and the first input 'd _{n +} j to the fourth combination circuit D _{n + 1} , and on the other hand through the first first connecting line ¹ r _{n +} , with the input of the combination circuit in the order of the next section.

v o 3

Output of second memory circuit? _{η + 1} is connected to the first input a _{n + 1 of the} first combination circuit ^A n + J, with the first input 'b _{n +} , the second combination circuit ^B n + p to the second

By the input of d _{n +} , the fourth combinational circuit D _{n +} ,, and on the other hand via another second connecting line ^r n +) ^{with the} input of the combinational circuit in the order of the next section. The output of the third memory circuit ³ ββ + is connected to the third input ³ bR + ^ of the second combination circuit B _{n +} ,> with the third input ³ cn of the third combination circuit CR + 1, with the third input ³ days +, the fourth combination circuit D _{n +} j. on the other hand via a further connecting line ³ r _{n +} j with the input of the combination circuit in the order of the next section.

The function of the gates is such that the signal applied to the control input releases the signal from the input 'hjj' of the gate * H _n to its output.

The function of the memory circuits is such that the signal applied to the recording input 'from _Q causes the signal to be excited at the output of the memory circuit' p, which lasts until the signal at the erase input 'n> _{n of} this memory circuit is applied.

2,0981

The first, second, third combination circuits are considered to be circuits with a logic function NOT-related to the first input 'b _n ,' c _n , the second input ² an, ² bn, ² cn, the third input ³ an, 3b _n , c _{n of the} first combination circuit A _n , the second combination circuit B _n , the third combination circuit C _{n <} As the fourth combination circuit, the circuit with the function of the logic product relative to the first input d _n , the second input d _n , the third input ^J d _n circuit D _n>

Under these assumptions, the signals at the signal line outputs of each section are determined by the following mathematical-logical relationships:

'x = ¹ S .'p,' r, ² P η η n-1 n ^2χ η ^{β 2S} n · ^2p n · 1 · ^3p „η η η η-1 n ³ X _n = ³ S_. 'p'. ³ r, η η n-1 n * ⁴ X '"n ^4S ·" ^{P "2} · P' · ^3p" η η η η n

Similarly, the signals at the signal lines of the next section are determined by the following mathematical-logical relations:

n + 1 n +, * n +, n * n + 1

2γ 3 2p 2p 3p n + 1 ^and n + 1 * n +, 'n' ^r n + 1

3γ - 3o 1p 3p 3p ^Λ η + 1 - ^a n + 1 * ^ť n + 1 * n ' ^ť n + 1

4y _and 4q 1 P 2 P 3 P n ^and n + 1 · ^T N + 1 'n + 1 + ^T n + 1

By default, all the memory circuits of the individual section and the next section are in the reset state. Signal applied to the recording input 'of _n causes the excitation signal at the output of the first memory circuit' P _n, which passes the one hand to the first input and _n first com binačního circuit A _R, the first input ¹ c _n third combination circuit C _n for the first the input 'd _{n of the} fourth combinational circuit D _n , and secondly through the first connecting line' r _n to the second input 2 & _{n + of the} first combinational circuit A _{Q + of the} next section. As a result, the first combination circuit A _{n +) of the} next section is blocked.

The signal applied downstream of the recording input from _n causes the signal at the output »2 λ of the second memory circuit 'P to be switched to the third input and _{n of the} first combination circuit A _Q to the first input b _{n of the} second combination circuit B _n . second input d _n fourth ·

2 _{n of the} combination circuit D _n , and secondly through the second connection line r _n to the second input b _{n + 1 of the} second combination circuit ^B n + 1 of the next section.

As a result, the signal at the output of the first combination circuit A _{n is excited} , thereby releasing the signal from the first input 's _{n of the} first signal line through the first gate' h _k to the first output 'x _n of the first signal line. _{n +} j of the next section.

Signal supplied subsequently to the recording input of ^three marks causes the excitation signal at the output of a third memory circuit ^ Pn, which passes the one hand to the third input-BN second combination circuit Bn, and to the third input? CN third combination circuit Cn, to the third input ^ dn fourth combinational circuit Dn, and on the other hand via a third connecting line 40 to the second input ^2c n + 1 of the third combinational circuit C _{n +} , of another section.

The result is both the excitation signal at the output of combination circuit B _R and TIM 2 release passage signal from the second input S _n second signal line via the second gate ² Hn to the second output ² Xn of the second signal line, the excitation signal at the output of the third combinational circuit C _n and thereby releasing the signal from the third input ^ S _{n of the} third signal line through the third gate ^ H _n to the third output ^ X _n of the third signal line, exciting the signal at the output of the fourth combinational circuit D _n and thereby releasing the signal S _{n of the} fourth signal line through the fourth gate 4 H _n to the fourth output X X _n of the fourth signal line, and secondly, the blocking of the third combination circuit C _{n +) of the} next section.

When changing the wake-up order of the memory circuits of an individual section, in the order of ř,

O v

P _n releases signals through the gates of the individual signal lines in the following order:

1. ^ H _n - when memory circuits' Ρ _β ,,

2. 'Hjj, ² Hn, ^ Hn - when the ² Pn memory circuit is subsequently excited ·

If ae considers a circuit having a logical sum function as the fourth combinational circuit I> _n , the gate of the fourth signal line is released when the at least one memory circuit of the individual section is energized.

In general, the structure and function of the wiring for group releasing and blocking the passage of signals according to the invention is modified by selecting the type of combinational circuits and by selecting the inputs of these combinational circuits with the outputs of the memory circuits.

One notable group of these modifications is that the inputs of the memory circuits of a single section are connected to the inputs of the combinational circuits of another section.

The structure, as well as the output signals of the combinational circuits of a particular section or another section, expresses the overall mathematical-logical relation:

^And n ^{'B n, C} n ^"D n" ^{κ (' 1-Γ η} _Λ η -1> \ - 1 ^{'1ρ η} · ^{2ρ η> 3ρ η>}

alternatively:

^A n + 1 ^'B n + 1' ^C n + ^'D n + 1' ^{Κ (1ρ} η ^'2ρ η> ^3ρ η> ^1ρ η +1' ^2ρ η + 1> ^ η + Ι ¹ wherein the symbol Κ is character general logic combinations.

A longer significant group of these modifications is that the outputs of the perimeter circuit of a single section are connected to the inputs of the combinational circuits of another section, and at the same time to the outputs of the memory circuits of the other section are connected to the inputs of the combinational circuits of the individual section.

The structure, as well as the next section, are expressed by the output signals of the combinational circuits of the individual section, or, as the case may be, by a summary mathematical-logical relationship:

^A n ' ^B n' ^C n ' ^D n ^{= K (} ' ^r n-1 ' ^2r n-1' ^3r n-1>' ^P n' ^2p n ' ^3p n'' ^P n + 1> ^2p n + 1 '^ η + Ι ¹ or:

n + ^{1, B} n + ^{1, C} n + ^{1, D} n + 1 'n' ^R n '* n' n + 1 'n + 1' * n + 1 where the symbol K represents the character common logical combination.

1τ> 2 3_, ¹ n + 2 ' ^Γ η + 2 · ^r n + 2''

Further connection of the sections depends on the fact that the outputs of the signal lines of the individual section are connected to the inputs of the combinational circuits of the next section or the outputs of the signal lines of the next section are connected to the inputs of the combinational circuits of the individual section.

Said connection achieves a chain connection of any number of sections.

The wiring for group releasing and covering the passage of signals is used in the solution of logical controllers structures in production lines composed of individual workstations with a relatively small number of two-position production operations.

It can be used in branched production lines of foundries.

Claims (1)

1. A wiring for group releasing and covering the passage of signals comprising two sections each comprising at least two signal lines, at least two memory circuits, at least two combination circuits and at least two gates, characterized in that the first input ('s _n ) of the first signal line the individual section is connected to the input ('h _n ) of the first gate ( ¹ ¾) of the individual section whose output is connected β by the first output (' x ') of this first signal line, and whose control input (''') is connected to the output of the first combinational circuit (A _n ) of the individual section, wherein the outputs of the memory circuits ('P _n ; ² P') of the individual section are connected to the inputs (* 6 ^ » ^b n) of the combinational circuits (A _n , B _n ) of the individual section and on the other hand through the connecting line Cr _n , r _n ) with the inputs (a _{n +} ,, b _{n + J} ) of the combination circuits (A _{n +} ,, B _{n + J} ) of another section.