CS231126B1 - Wiring of the basic programmable frequency divider module - Google Patents

Abstract

Connection of the basic module of a programmable frequency divider consisting of a programmable frequency prescaler of the type n; (n + 1)/1 connected by its output to a frequency divider, which is connected by its outputs to a comparator of two binary numbers X<Y, to which a sum circuit is connected by its outputs. The output of two binary numbers X4Y is connected to a programmable frequency prescaler of the type, nj (n + 1)/1.

Description

The invention relates to a basic programmable frequency divider base module comprising a n-type programmable frequency divider; (n + 1) / 1 connected by its output to a frequency divider.

At present, the HEF 4751, a universal frequency divider ^, is produced on the above principle, which, including the function, is described in detail in Giles: Versatile LSI Frequency Synthesiser System ”. A block diagram of a Giles-based programmable frequency divider base module is shown in Figure 1. This basic module consists of a n-type programmable divider; (n + 1) / 1, 10/1 frequency divider and speed selector. The 10/1 frequency divider is a four-bit frequency divider adjusted to generate 1, 2, 4, and 8 pulses at the 1,2,4,8 outputs within one output qignal period. The speed selector processes the signals from the 10 / 1 so that a pulse train dependent on the setting of the number n · ^ and the input transmission P ^ _n according to the relation f _zv - (P _in + η _χ ) * f _{ou is} generated at its frequency divider control output, where P _in »O or 1 and η _χ = 0 to

A disadvantage of the module solution according to FIG. 1 is the complex logic structures in the 10/1 frequency divider and the speed selector. In addition, a conventional binary or BCD counter cannot be used at the 10/1 frequency divider position.

These disadvantages are solved by the circuit according to the invention, fig. 3, which is based on the fact that the frequency divider of the typu type is connected to the first input, the second input up to the k-th comparator input of two binary numbers X <Y, itsS output - 2 -

231 126 is coupled to a second input of a programmable frequency divider type n; (n + l) / l, whereby k-plus first input, plus second input up to k-plusent input of comparator of two binary numbers X <Y is connected to-plus first output, k-plus second output to k-plusent output of addition circuit which has a first input for inputting transmission information from the following frequency divider control building blocks, wherein the second input, the third input up to the th-th sump input &apos; are intended for data entry.

FIG. 1 shows a known block arrangement of a programmable frequency divider base module consisting of a n-type programmable divider; (n + 1) / 1 A, frequency divider 10/1 B, to which a speed selector RS C _f connected to a programmable sub-divider A is connected. Fig. 3 shows the wiring of a base module of a programmable frequency divider according to the invention consisting of a programmable frequency divider type n; (n * 1) / 1 1, frequency dividers N / l 2, comparator of two binary numbers X <Y 3 and from the adder 4. The connection of these elements is as follows: first output 23, second output 24 to k-th output 2k N / 12 is connected to the first input 32, the second input 33, except for the k-th input 3k of the comparator of two binary Numbers X <Y 3, whose output 31 is connected to the second input 12 of the programmable n-type divider; (n + 1) / 1 1, with the k-plus first input 3k-1. k-plus second input 3k-2 up to plusent input 3k-n of comparator of two binary numbers X <Y 3 is connected to-plus first output 4k + 1, k-plus second output 4k + 2 to k-plus output 4k + n addition circuit ^ 4, whose first input 41 is for inputting transmission information from the following controlled frequency building blocks, the data n ₁₀ being added to its second input 42. the third input 43 except for its k-th input 4k.

The novelty of the invention is that the speed selector RS (FIG. 1) is replaced by a comparator of two binary numbers X <Y 4. This greatly simplifies the logical structure of the frequency divider N / l 2 and can be used at this position binary or BCD code. Another advantage of the basic module of the programmable frequency divider according to the invention is its shape

- 3 231 126 a signal for controlling the split ratio of the programmable frequency divider n; (n + 1) / l 1, This signal, at the output 31 of the compressor

X <Y 3, within a period of the output signal, has the form of a single pulse whose width varies depending on the setting of the number nj © of the input transmission P ^ _n <> This justifies the assumption that the cutoff frequency of the basic module of the programmable divider is higher than the cut-off frequency of FIG. 1, wherein the split ratio control signal n; (n + 1) / l is in the form of a pulse train whose number is determined by setting the n-^ number and the input transmission. The function of the programmable frequency divider base module 111 will be further explained in a circuit that conforms to the BCD code provided that the programmable divider n; (n + l) / l is adjustable for n ₂ = 1 to 9, in the divider N / l is set the dividing ratio 10 and the comparator of two binary numbers X <Y 4 is simplified to the comparator of two four-bit numbers - see Fig. 2. frequency 10/1 divides the period of the output signal f _{QU and} h and 10 sub-modes in which there is a n ₂ divider; (n ₂ + 1) / l divide ratio (n ₂ + 1) is assigned for n ^ subperiod and for the remainder, that is (10-n- ^) subperiod, divide ratio n ₂ is included. 2 may be expressed in the form

N = n- ^. (n ₂ + 1) + (10-β 1). n ₂ , which can be easily converted to

N = 100. n ₂ + n - ^.

From this equation it can be seen that the divider shown in Fig. 2 represents a programmable frequency divider adjustable by a BCD code within the range of 10 to 99. Any binary code request in the circuit shown in Fig. 2 can simply be accomplished by replacing the 10/1 divider with by extending the divide n ^; (n ₂ +1) / 1 from setting n ₂ «1 to 9 to n ₂ = 1 to 15. If the last equation is n ₂ » hj «0, then formally N = 0, but for n ₂ = O loses the divider n ₂ (n ₂ +1) / 1 physical meaning. It follows that the minimum dividing ratio Ν ^ _{η of the} divider according to Fig. 2 is equal to 10 (n ₂ can be chosen from the range of integers 1 to 9).

231 128

- 4 Unlimited number of programmable type 10 dividers can be connected to the basic module; (11) / 1 (BCD data) or type 16; (17) / 1 (data in binary, code) with gradually increasing cut-off frequencies. In terms of function, it is necessary to supplement the basic module in Fig. 2 with further comparators of four-bit numbers 5 ^ <Y _n and synchronization of programmable dividers. Added comparators is required from the numbers K _n connected in parallel to the base of the comparator, that is, the binary-valued outputs of splitters 10.1 (see Figure ₂₎ »Adder (or polosčítačka) in the base module of FIG. 2 and FIG. 3 implements the so-called fractional split ratio in cooperation of the described circuit with the circuit of the programmable module for creating the fractional split ratio in the universal frequency divider, which is the subject of another application of the invention. The comparators that extend the base module do not have any upstream adders in the data stream, so the numbers are directly individual data inputs _by

Connection of the basic programmable frequency divider module, in conjunction with the connection of the programmable frequency divider type n; (n + 1) / l according to AO 231127 and with the involvement of the programmable module for generating a fractional split ratio in the universal frequency divider according to AO 231128, a universal programmable frequency divider with multiple feedback can be assembled.

This wiring of the base module of the programmable frequency divider according to the invention allows several programmable type 10 splitters to be upstream; (11) / 1 (data in BCD code), or type 16; (17) / 1 (data in binary code). The tip of the programmable divider is independent of the lowest weight distribution of the digit, which corresponds to a certain frequency grid of the synthesizer output frequency, thus allowing very simple programming of the lowest digit without interfering with the higher digits programming. Therefore, the frequency divider system in multiple feedback can be considered as the most modern and at the same time also the most universal on a global scale.

Claims (1)

Ρ 8 B D ATTENTION OF THE INVENTION 231 126 Connection of the basic programmable frequency divider module consisting of a n-type programmable frequency divider; (n + 1) / l connected by its output to a frequency divider, characterized in that the frequency divider (2) is connected to the first output (23), the second output (24) to the th output (2k) an input (32) of a second input (33) to a 1 th input (3k) of a comparator of two binary numbers (3) whose output (31) is connected to a second input (12) of a »n programmable frequency divider; (n + l) / l (1), with k-plus first input (3k-l), plus second input (3k-2) 'and up to k-plus * input (3k-n) of the comparator of two binary numbers (3) a k-plus first output (4k-1), a k-plus second output (4k-2) and a k-plus output (4k-n) of the adder circuit (4) having a first input (41) for inputting information transmitting from the following frequency divider control building blocks, the second input (42), the third input (43) to the th-th input of the adder circuit (4) being for data input ( ^nl ).