CS231703B1 - Wiring for Logic Signal Passage - Google Patents

Abstract

The connection consists of at least two signal lines, where the first input of the first signal line is connected to the input of the first gate, the output of the first gate is connected to the first output of the first signal line, and the control input of the first gate is connected to the output of the second gate. The output of the first gate is longer connected to the control input of the second gate. The advantage of the connection is the mutual coupling and conditionality of the passage of logical signals in the system of coupled signal lines. Application - in special cases of solving logical automata with a combined function.

Description

The invention relates to the connection of a logical network for releasing the passage of logical signals in electronic, current or other systems, in particular in the field of direct control of production processes or production facilities.

Connections for releasing signal passage according to quite simple dependencies are known, for example with a predetermined order of pass priority, sequentially in order of Sas and the like.

The disadvantage of these wiring is the fact that it solves only simple dependencies, such as the order, time delay of input signal generation and the like.

These disadvantages are overcome by a circuit according to the invention comprising at least two signal lines, characterized in that the first input of the first signal line is connected to the input of the first gate, where the output of the first gate is connected to the first output of the first signal line, the gate is connected to the output of the second gate.

The output of the first gate is further associated with the control input of the second gate. Any combination logic circuit with an input, an output, a control input is considered as a gate, where the passage of the signal from the input to the output is released or closed by the action of a signal of a specified logic level at the control input. For example, a combinational logic circuit with a logic conjunction function relative to the input and the control input may act as a gate.

The control input is further doubled or multiple, and comprises, for example, a first control input, a second control input. The passage of the signal from the input to the output is released or closed by a specified logical combination of the signals at the control inputs.

The advantage of the connection according to the invention is mutual interconnection and conditionality of the passage of logical signals in the system of interconnected signal lines.

The circuit according to the invention is illustrated by way of example with reference to the accompanying drawing, in which FIG. 1 shows the principle circuit, and FIG. 2 shows further interconnection of the signal lines.

FIG. 1 shows a first signal line consisting of a first input Sj connected to a first output X connected via a first gate so that this input Sj is connected to an input h _{1 of} this gate H, whose output <H, > is connected to the first output X ₁ circuit, the second signal line comprises a second input Sg coupled with the second procedures "Xg circuit via a second gate Hg, so that this input SG is connected to the input hg of the gate Hg whose output <Hg > is coupled to the second wiring output Xg, the third signal line comprising a third input S ^ connected to the third wiring output X ^ via the third gate so that this input Sj is connected to the input h ^ of this gate Hj, whose output <H ^> is connected to the third output Xj wiring, etc., another signal line consists of another input S _N connected to another output X _N wiring through another gate Hjj so that this input is connected to input h _N to The output <Nj _i > is connected to another output X _{N of the} circuit.

Linking these signal lines is such that the output <Hg> second gate Hg is further connected to the control input H, the first gate H _1, the output <H ^> the third gate is further coupled to the control input of Hg second gate Hg, etc., the output <H ^> of the next gate H ^ is connected to the control input of the previous gate.

In Fig. 2, the interconnection of the signal lines is such that the output <H,> of the first gate H is

i 703

The wiring function y of the exemplary embodiment of FIG. 1 is such that the one logic input signal that arrives at the first input Sj and which passes to the input h | first gate Η ,, passes under the effect of a zero logic signal at the control vstupuT on output <H> of gate Hj and further to the first output connections X _1.

Upon subsequent arrival of the one logic input signal at the second input Sg, which passes further to the input hg of the second gate Hg, and when a zero logic signal is applied to the control input Hg, the output <Hg> of this gate Hg results in input H _{1 of the} first gate and closes its passage. The signal at output <H |> of the first gate H, and on the first output Xj of the circuit, is terminated.

Upon the next arrival of the one logic input signal at the third input Sj, which passes further to the input hj of the third gate H ^, and when a zero logic signal is applied to the control input H ^, the one logic signal is output at the output <H - ^> it passes to the control input Hg of the second gate and closes its passage.

The signal at the output <Hg> of the second gate Hg and at the second output Xg of the circuit is terminated. The result is a zero logic signal at control input H _{{of the} first gate and a re-release of the one logic input signal ~ - of the first input S _t to the first output Xj. connection.

Collectively are one-logic input signal at the input S ^ with the serial number i, my loose passage to output X ^ engagement with the serial number i, closes the passage are one-logic input signal at the input S _i _ ₁ IL with a serial number.

One logic input signal at input S1g with sequence number i-2 has the passage to output i1 = 2 wiring enabled. The sequence number i represents any natural number 1, 2, 3, .TT / N.

With a different logic structure and the function of the gate release releases used by the one logic signal at the gate control input each, the one logic input signal at input S1 having a cleared passage at the output X1 opens the passage for the one logic input signal at the input.

The one logic input signal at the input then has a cleared pass to the output ^ i-2 ^at P ° 3 ^en ^ when the signal passes to the output <Η ^ _ ₍ > gate H ^ _ _] with sequence number il.

In the extreme case, the one logic input signal on the first input Sj has a cleared passage to the first output X, connected only when the one logic input signals pass to all other outputs, i.e. outputs Xg, X ^, ..., X ^.

The one logic input signal at gate control input Hjj frees the passage for the one logic input signal from input Sjj to output X1 of the wiring. At zero logic input signal at this control input, Hjj closes the passage of all signal lines.

The wiring function in the exemplary embodiment of FIG. 2 is such that the one logic input signal that arrives at the second input S _o and which passes to the input h _{o of the} second gate -X —ά 1

Hg, when a zero logic signal is applied to the first control input Hg and a zero logic signal is applied to the second control input ^ Hg, the output <Hg> of this gate Hg is switched to the second output Xg of the wiring.

p

The signal at the output <Hg> of gate Hg passes further to the second control input of the H ₁ of the first gate H, and closes the passage for the downstream are one-logic input signal to the first input j, and passes further to the first control input "h ^ third gate H and closes its passage for the subsequent one logic input signal at the third input S1.

As a result of the open passage of the unity logic input signal ns, the second input _{of G} to the second output Xg involvement and the subsequent formation of the unity of the input signal at the first input S, or on a third input S ^ at «•« early closing of the passage of the unity of the input signal The first input _1, or the unity of the input signal on the third input S ^.

Collectively are one-logic input signal at the input with the serial number i, which has loose passage to output zepojení with serial number i, closes the passage for are one-logic input signal at the input S _i _ ₁ with serial number i-1, and simultaneously closes the passage for A * logical input signal on input with i + 1 sequence.

A * logic input signal at input S _i _G with serial number i-2 has a passage to the outlet connections is released, are one-logic input signal at the input S _{1 + 2} with sequence number i + 2 has a passage at the output X ^ _+] loose. The sequence number i represents any natural number 1, 2, 3, ..., Ň.

With different logic composition and function of used gates with the release of passage always one logic signal on the first gate control input and zero logic signal on the second gate control input, the one logic input signal on the first input S passes to the first output X, wiring on one logic signal at the first control input ^, H _{1 of the} first gate Hp while at the same time releasing the passage from the second input Sg to the second output JL, and the connection.

The result is the release of signals in sequential order. The single logic signal at the input passes to the output X ^ of the wiring only as these signals progressively pass to all wiring outputs with a lower order index.

By interrupting the one logic signal at control input ¹ H, the first gate, or by interrupting the one logic signal at first input 'S', the passage of all signal lines is closed.

A further use of the circuitry according to the invention is that the circuit inputs Sp, 4, ..., Sj may be multiple and may consist of several elementary inputs. It is then a matter of releasing the passage of groups of input signals from the multiple wiring input to the respective multiple wiring output with the same sequence index.

The circuitry according to the invention is used in special cases of combined-function logic controllers, for example in the field of fixed-logic control systems.

Claims (2)

SUBJECT OF THE INVENTION !. A logic signal release circuit comprising at least two signal lines characterized in that the first input (S ₁ ) of the first signal line is connected to the input (hj) of the first gate (H,), where the output (<Hj>) of the first gate (H) ,) is connected to the first output _(X1) of the first signal line and a control input (Hp first gate signal (H ₁₎ is connected to the output (<Hg>) of the second gate (Hg). ² Wiring according to claim 1, characterized in that the output (<Η ^>) of the first gate (H ₍ ) is longer connected to the control input ( ¹ Hg) of the second gate (Hg).