CS238951B1 - N-bit pseudo-random code generator - Google Patents

Abstract

The invention relates to the field of generating logical signals with the possibility of setting the probability of a pseudo-random signal. The subject of the invention solves the problem of reducing the component complexity for n-bit word generators. The essence of the invention lies in the fact that in the time-multiplexed mode, the pseudo-random signal of the generator is written sequentially into the n-bit register after a predetermined modification, and thus the desired signal is created. The invention can be used in the construction of testers, especially of the service type.

Description

(54)

N-bit pseudo-random code generator

The workbook relates to the field of generating logical signals with the possibility of setting the probability of a pseudo-random signal. The present invention solves the problem of reducing the component demand for n-bit word generators.

SUMMARY OF THE INVENTION In a time-multiplexed mode, the pseudo-random generator signal, after a predetermined modification, is written successively to the n-bit register to produce the desired signal.

The invention can be used in the construction of testers, particularly of the service type.

238 951

238 951 (B1) (51) Int. Cl. ¹

II 03 C 19/00 • a

238 951

The invention relates to the generation of a sequence of pseudo-random words which they use to stimulate digital circuits.

Existing pseudo-random n-bit word generators with a sequence length of 2 ^m steps are generated mainly in two ways.

The first method is by means of linear feedback registers, each register being m-bit. The change in signal probability is made, for example, by changing the linear feedbacks. This method of obtaining pseudo-random code is simple, but very demanding in terms of the number of components.

Another way is to create a generator using a register that has (m + n) bits. The N-bit parallel output is generated by a combinational logic network. This method is not as demanding as the previous součástkový, but you can not simply changes the probability of ¹ · output logic signals for each output.

The above-mentioned disadvantages are overcome by the solution according to the invention, which consists in interconnecting a serial pseudo-random code generator of at least (2 ^{m + n} -1) bits, a modifier circuit, by which the probability of logic level, demultiplexer and n-bit memory can be changed. The memory outputs are used to drive the primary inputs of the network under test.

Technical progress is characterized in that the generator provides the possibility of generating a pseudo-random signal that allows only a single change of the logical state at the memory outputs at a given point in time. This will largely

238 981 eliminate gambling states in a stimulated logical network that may arise from the concurrentity of several simultaneously changing logic signals. Another advantage is the wide range of possibilities of changing the probabilities of the logical signal, which allows to improve the diagnostic coverage of the tested logical network.

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The attached drawing shows a block diagram of a generator according to the invention.

The pseudo-random code generator G generates a serial pseudo-random code synchronously with a clock signal that is applied to the synchronization input 11. The length of the generated sequence is given by the relation (2 ^{m + n} -1) of bits, where m is the number of required test steps and 2 ⁿ is the number of data outputs Z. In order to match the character of the generator sequence for each test cycle signal

The selected generator outputs 01 to Or, whose number is determined by the number of signal probability modification stages required, are connected to inputs I1 to Ir of modifier B. The logic processing of the signals at inputs 11 to Iv allows the probability of the 0¾ output signal to vary control signals that are on control inputs C1 to Ck. The output Ov is connected to the input I n of the n-bit demultiplexer D. If the signals on the address inputs A1 to Ap of the demultiplexer are synchronized with the clock signal of the generator G, the logic level Iv can be assigned to the inputs Y1 to Yn. which is written to these circuits.

The signal outputs Z1 to Zn always form a pseudo-random word with a width of 2 ⁿ bits for 2 ⁿ clock pulses, the generator generating 2 ^m -1 for these different test words.

The character of the series of signals on each of the outputs ZA to Zn is also pseudo-random and the probability of this signal is determined by the state of the control inputs C1 to Ck at the time of writing the value of the input signal Iv into one of the memories Pn. If the states of the inputs are synchronous

238 951

G1 to Ck with the state of the address inputs of the demultiplexer AI to Ap and if the state of the inputs C1 to Ck is dependent on the state of the address inputs of the demultiplexer AI to Ap _t, then we can obtain signal sequences with different probabilities. Changing the level of a logic signal can occur at a given time only on one of the outputs. Z1 to Zn.

Said circuit can be used to generate n-bit pseudo-random logic signal sequences and can be used to stimulate the test logic circuits, for example in testers.

Claims (1)

SUBJECT OF THE INVENTION 238 951 An n-bit pseudo-random code generator, characterized in that the clock generator output (G) is connected to the synchronization input (1) of the code generator (G) and to the setting input (2) of the code generator (G). 01 to Or) of the code generator (G) are connected to the data inputs (11 to Ir) of the signal probability modifier (B), while the control inputs (C1 to Ck) of the signal probability modifier (B) are connected to control signal sources, Ov) the signal probability modifier (B) is applied to the input (Iv) of the n-bit demultiplexer (D), the address inputs (A1 to Ap) of the n-bit demultiplexer (D) are connected to an address bus, the data outputs (XI to Xn) ) n-bit demultiplexers are connected to individual data inputs (Y (to Yn) of memory circuits (P1 to Pn) and to signal outputs (Z1 to Zn) of memory circuits (P1 to Pn) the n-bit word of the random code is stored.