CS256845B1 - Combined pulse modulator connection - Google Patents

Abstract

The connection concerns the modulator and is solved by the programmer of the PROM memory for this modulator. The modulator converts the analog signal of the controller's action quantity into a pair of two-valued signals, in which the average switching time corresponds to the absolute value of the action quantity. The modulator consists of a block for determining the pulse parameters and a pulse circuit. The pulse parameters, i.e. the required pulse width and the required length of the gap between pulses, are determined by the modulator using a multiplier, a divider, two selection blocks and a difference element in both the width modulation mode and the frequency modulation mode. The transition between the modes is controlled by a comparator based on the condition of observing the minimum permissible pulse period. In addition to the pulse parameters, the pulse circuit consisting of a counter with auxiliary circuits is also controlled by a sign input, which usually indicates the direction of rotation of the controlled servomotor. The connection is used in automatic control of technological processes in all industrial sectors.

Description

BACKGROUND OF THE INVENTION The invention relates to the connection of a combined pulse modulator for converting an analog signal of an actuator to a pair of two-valued signals in which the mean switching time corresponds to an absolute value of the actuator.

The known pulse modulator connections used in the field of automatic process control work as width modulators, that is, as level / duty converters. For these converters, the repetition frequency of the pulses is chosen to meet the requirements of the converter dynamics. For x * constant values, near steady state modes, and when using asynchronous motor servomotors, in situations where the modulator output should match the very small required actuator speeds, the controller-servo linearity cannot be maintained at a fixed repetition rate . The resulting dead band in some cases unnecessarily limits the achievable control accuracy. A more serious drawback is also the unnecessarily high switching frequency of the actuator, which affects the probability of motor overload and wear of the mechanical parts of the actuator. It is related to the quantization of the input signal of the converter to a relatively small number of levels, determined in addition to the repetition frequency of the pulses, also by the minimum width of the output pulse causing a defined response of the servomotor. The requirement to reduce quantization errors for a width modulator is in contrast to the requirement to reduce the modulator delay.

- I 256 845

Increasing the pulse period can cause undesirable ripple of the controlled variable if the controlled system does not additionally filter the pulse frequency. For small output signals, it is preferable to use a frequency modulator also called an interval pulse modulator with a fixed pulse width, which, however, often gives an inadmissible number of actuator switching for larger input values.

These drawbacks are overcome by the wiring of the combined pulse modulator of the invention, in which the wiring signal input is coupled to the first divider input and the first multiplier input. The multiplier output is coupled to the first input of the first selection block, the second input of which is connected to the second divider input and the second wiring parameter input. The first parametric wiring input is coupled to the second multiplier input, the first input of the second selection block, and the first input of the first comparator. The second input of the first comparator is connected to the output of the divider and to the second input of the second selection block. The control input of the second selection block is coupled to the output of the first comparator and to the control input of the first selection block, the output of which is coupled to the first input of the differential member. The second input of the differential member is coupled to the output of the second control block. The essence of the invention is that the output of the first selection block is connected to the first input of the third selection block, the second input of which is connected to the output of the differential member and the input of the coincidence member. The output of the coincidence member is coupled to the second Auxiliary Gate Inlet and the flip-flop input. The flip-flop output is coupled to the control input of the first output gate, the control input of the second output gate, and the input of the third selection block. The output of the third selection block is connected to the second input of the second comparator, the first input of which is connected to the counter output.

- 3,256,845

The output of the second comparator is coupled to the first input of the secondary gate. The output of the auxiliary gate is connected to the flip-flop input of the flip-flop and to the second input of the logic sum block whose output is connected to the reset input of the counter. The first input of the logical sum block is connected to the flip-flop reset input and the non-equivalent block output. The second input of the non-equivalent block is coupled to the output of the sign bit memory, the input of which is connected to the sign input of the circuit, the first input of the non-equivalent block, the gating input of the first output gate and the gating input of the second output gate. The output of the second output gate is connected to the second wiring output. The first wiring output is coupled to the output of the first output gate.

An advantage of the arrangement according to the invention is the possibility of automatically switching from the width modulation mode to the frequency modulation mode and vice versa. The user has the possibility to enter, or continually change, two parameters of the combined modulator, which are illustrative and determine the conditions of transition between the two modes. The first parameter is the minimum permissible pulse period. The second parameter is the minimum permissible pulse width. The modulator has advantageous dynamic properties. When the input signal changes rapidly, the modulator enters a new mode with a small delay, or dynamically lengthens or shortens the pulse, or the pulse gap. When the input passes through the zero level, it changes the polarity of the output, that is, it switches to the pulse of the alternative output. The static characteristics of the converter show very little insensitivity, given the length of the word used. At the same time, it introduces a dynamic insensitivity suppressing restlessness in the control circuit when the input signal fluctuates with a relatively short period around zero.

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The modulator allows high precision control in frequency modulation mode. It also allows to achieve high quality transient processes in the width modulation mode. At the same time, it gives the possibility to limit the number of output pulses and thereby contribute to a higher reliability and service life of the actuator. The advantages of the modulator are particularly evident in the control of faster, low-order objects having a high rise-to-draw-time ratio and in those cases where constant speed servo drives without positional feedback and a limited number of switching cycles are used. If the wiring is used as part of the actuator control end member, it can also process "more" * and "less" emergency commands and satisfy the requirement to adjust the actuator at maximum speed over a large range with the possibility of rapid stop or reversal. By selecting two modulator parameters, a very diverse behavior can be achieved, suited to different fields of application, and is therefore suitable as a basis for a universal system modulator unit for automatic process control. The wiring can be easily realized by digital integrated circuits, or hybridized by combining low and medium density integrated circuits and a processor. For fixed modulator parameters, the wiring can be used to prepare PROM memories, for specific modulators, or to test the effect of both parameters on the control process with a particular object.

An example of an arrangement according to the invention is shown in the attached drawing in a block diagram.

Individual wiring blocks can be characterized as follows.

The multiplier 01 is formed from PROM memories, or from a processor and support circuits. It is used to multiply the signals on its inputs.

256 845

The partition 02 is made of PROM memories, or a processor with support circuits, or an arithmetic logic unit with support circuits. Divides the value at its second input by the value at its first input. The first comparator 02 is an integrated comparator that compares the value at its first input to the value at its second input and outputs its first selection block 04 and the second selection block 05. The first selection block04 is formed by an integrated multiplier circuit. It determines the required pulse width according to the logic signal on its control input. The second selection block Οχ consists of an integrated multiplexer. It determines the required pulse period according to the logic signal and its control input. The differential member 06 is formed from an integrated binary sumper with auxiliary inverters.

Subtracts the value at its first input from the value at its second input, and the difference of these values affects the desired pulse gap length. The auxiliary coincidence circuit 07 consists of open-collector inverter integrated circuits with a common working resistance. Used to test the required pulse gap. The sign bit memory 08 is formed by a JK type flip-flop. At its output, it specifies the older sign input value. The non-equivalent block οχ consists of two inverters and a 0R gate. Together with the sign bit memory 08, it evaluates the passage of the input signal at zero. The third selection block 10 is formed by a multiplexer. It provides the required pulse width or gap length. The second comparator 11 is formed in an integrated embodiment. It is used to test whether the actual pulse width or the actual pulse gap length has exceeded the desired value. The auxiliary gate 12 is formed by a NAND circuit. Depending on the signal at its second input, it blocks or transmits the signal from its first input. The logical sum block 13 is formed from an OR-type gate. Based on information about achieving or

AND

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256 845 exceeding the desired pulse width or the desired pulse gap length creates a reset signal for the counter, the counter 14 being formed by the return counter integrated circuits. Uses a zero-up counting mode. The flip-flop 15 is an integrated flip-flop type JK. Flips to the opposite state with a space / pulse meaning in each cycle in which log.l enters its flip. At the evaluated zero crossing, it is reset to zero by the zero input and is cast at its zero input at zero coincidence. The first output gate is a NAND gate. If the sign input of the wiring is positive, it passes the signal to the wiring output 006. The second exit gate is also a NAND gate. Passes the signal at the wiring output with the negative polarity of the wiring input 001 wiring.

The individual blocks are connected as follows. The wiring signal input 002 is coupled to the first input 021 of the divider 2 and to the first input 011 of the multiplier 01. The output 013 of the multiplier 01 is coupled to the first input 041 of the first selection block 04. whose second input 042 is coupled to the second input 022 of the divider 02. input 004 wiring. The first wiring parameter input 003 is coupled to the second input 012 of the multiplier 01, the first input 051 of the second selection block 05 and the first input 031 of the first comparator 03. The second input 032 of the first comparator 03 is connected to the output 023 of the divider 02 and the second input 052 of the second The control input 053 of the second selection block 05 is connected to the output 033 of the first comparator 03 and to the control input 043 of the first selection block 04. whose output 044 is connected to the first input 061 of the differential member 06 and the first input 101 of the third selection block 10. 054 of the second control block 05 is coupled to the second input 062 of the differential member 06. The output 063 of the differential member 06 is coupled to the second input 102

256 845 of the selection block 10 and with the input 071 of the coincidence element 07 The output 072 of the coincidence element 07 is connected to the second input 122 of the auxiliary gate 12 and to the input input 153 of the flip-flop 15. with a control input 172 of the second output gate 17 and a control input 103 of the third selection block 10.

The output 104 of the third selection block 10 is connected to the second input 112 of the second comparator 11, the first input 111 of which is connected to the output 142 'of the counter 14. The output 113 of the second comparator 11 is connected to the first input 121 of the auxiliary gate 12. connected to flip-flop input 151 of flip-flop 15 and to second input 132 of logic sum block 13. whose output 133 is connected to reset input 141 of counter 14. First input 131 of logic sum block 13 is connected to reset input 152 of flip-flop 15 and output 093 non-equivalent block 2 ,. The second input 092 of the non-equivalent block 2 is coupled to the output 082 of the sign bit memory -08, the input 081 of which is connected to the sign input 001 of the wiring, the first input 091 of the non-equivalent block to the gating. The output 173 of the second output gate 17 is coupled to the second wiring output 006. The first wiring output 005 is coupled to the output 163 of the first output gate 16.

The block used to determine the pulse parameters includes a multiplier 01, a divider 02, a first comparator 03, a first selection block Oj ·, a second selection block 05, and a differential member 06. These blocks determine the momentary pulse width required at the output 044 the first selection block 04. and the desired pulse gap length that is outputted by the differential member 063 06. Block,

The 256 845, which is used to determine the pulse parameters, may be part of a modulator or memory fixture

PROMs that can replace the entire pulse parameter block in a particular modulator. · The other wiring blocks included under 07 to 017 create their own pulse circuit.

All wiring blocks operate periodically. The pulse circuit processing period may be equal to or less than the processing period for the pulse parameter determination block. It is assumed that the time synchronization pulses come from the outside. The sign input 001 of the wiring receives the sign information of the modulator input signal. This information comes to the input 081 of the sign bit memory 08, to the first input 091 of the non-equivalent block 2, to the gating input 162 of the first output gate 16, and to the gating input 171 of the second output gate 17. . This information comes to the first input 011 of the multiplier 01 and to the first input 021 of the divider 02. At the first parametric wiring input 003 there is information about the minimum allowable pulse period that arrives at the second input 012 of the multiplier 01, the first input Q31 of the first comparator 03 and beer input 051 of second selection block 05. On the second parametric input 004 the minimum permissible pulse width information that comes to the second input 022 of the divider 02 and the second input 042 of the first selection block 04. The multiplier determines the multiplier from its inputs 011 and 012 01 a pulse width setpoint value for a width modulator with a repetition period determined by the parameter from the first wiring parameter input 003. The product of both signals at inputs 011 and 012 of multiplier 01 is normalized so that for the maximum value at the first input of multiplier 01, at its output 013, the value of the first parameter is the same as on the first parameter.

256 845 input 003 wiring. The splitter 02 determines from the signals at its inputs 021 and 022 the desired pulse period, the ratio being normalized so that for the maximum value at the wiring signal input 002, the second parameter input 004 at the wiring output 023 is the size of the second parameter. In the first comparator 03, the signal carrying the pulse setpoint information at the first input 031 of the first comparator 03 is compared to the signal carrying the minimum pulse value information at the second input 032 of the first comparator 02 · If a frequency modulation period is required greater than the minimum permissible pulse period, which is on the first wiring input parameter 003, the log.l signal is output 033 of the first comparator 03, thereby determining the frequency modulation mode for the modulator. The signal log.l arrives at control input 053 of the second control block 0. At the output 054 of the second control block 05, a pulse period is required that comes from the output 023 of the divider 02. The first selection block 04 indicates at its output 044 the minimum allowable pulse width, which value is at the second input 042 of the first selection block 04. pulse period for frequency modulation less than the parameter from the first wiring parameter 003, is there a log 0 signal at the output 033 of the first comparator 03 _? and thus the width modulation mode is determined for the modulator. In this mode, the first selection block 04 outputs the desired pulse width at its output 044. The desired pulse width information arrives at the first input 041 of the first selection block 04 from the output 013 of the multiplier 01. The second selection block 05 provides at its output 054 information on the desired period length equal to the minimum allowable period length determined at the first wiring parameter 03 . Information from the outputs of both selection blocks is

256 645 leads to the inputs 061 and 062 of the differential member 06. In the differential member 06, the desired pulse gap length is determined by subtracting the desired pulse width from the first input pu 061 of the differential member 06 from the desired pulse period from its second input 062. 044 of the first selection block 04 and at the output 063 of the differential member 06 determine the pulse parameters for the pulse circuit. These parameters correspond to the values at the wiring signal input 002 and at both the wiring parameter inputs 003 and 004. The counter 14, which is part of the pulse circuit, counts in ascending order until the read value at its output 142 is equal to or greater than the upper limit specified at its output 104 by the third selection block 10. The selection block 10 alternately determines the desired pulse gap length. or desired pulse width. The distinction between pulse gap and pulse width is provided by flip-flop 15. The signal from output 154 of selection block 15 controls control input 103 of third selection block 10, so that for status - pulse width - it passes to output 104 of third selection block 10. a signal from its first input 101 of the desired pulse width. Pro stav

pulse gap - a signal from its second input 102 of the desired pulse gap length is output to output 104 of the third selection block 10. Counter 14 is reset by a signal at its reset input 141. Reset is performed by a logic sum block 13 by a signal at its output 133. Reset is performed whenever the state changes.

pulse gap - and - pulse width -. That is, at the second input 132 of the logic sum block 13, there is a log.1 signal. Resetting is also performed when the modulator input signal is evaluated to be zero.

This is the case when there is a log.1 signal on the first input 131 of the logical total block. The zero-crossing of the input signal is evaluated by the non-equivalent block 09 together

11 256 845 and the sign bit memory 08. If the current sign on the wiring sign input 001 differs from the sign recorded in the last measure that is recorded in the sign bit memory 08, then the log.l signal appears at the output 093 of the non-equivalent block 09. This signal resets counter 14 via logic sum block 13. At the same time, this signal resets the flip-flop 15 via its reset input 152. Flip-flop 15 goes to the gap state. If the setpoint pulse gap value at input 071 has a coincidence member 07 zero value, the output 072 of the coincidence member 07 is a log.O. This signal blocks the passage of the signal from the first input 121 of the auxiliary gate 12 to its output 123. At the same time, the signal log.l.

The signal from the flip-flop output 154 passes to the control input 161 of the first output gate 16 and to the control input 172 of the second output gate 17. The first input gate 16 passes the signal from its control output 161 to its output 162 and first wiring output 005 if the sign on the sign input 001 the wiring is positive. The second output gate 17 transmits a signal from its control input 172 to its output 173 and to the second wiring output 006 if the sign on the wiring input sign 001 is negative.

The invention is used in devices for the automatic control of technological processes, for example in flow control circuits, as slave loops for level control or temperature control.

Claims (1)

COURSE YOURSELF, 256 845 Connection of the combined pulse modulator, where the wiring signal input is connected to the first input divisively, and the first multiplier input, the output of which is connected to the first input of the first selection block, the second input is connected to the second divider input and the second parametric wiring input. the first parametric input is coupled to the second input of the multiplier, the first input of the second selection block, and the first input of the first comparator whose second input is connected to the output of the separator and the second input of the second selection block whose control input is connected to the output of the first comparator and the control input a first selection block, the output of which is connected to the first input of the differential member, the second input of which is connected to the output of the second control block, characterized in that the output (044) of the first selection block (04) is connected to the first input (101) of the third selection block The second input (102) is connected to the output (063) of the differential member (06) and the input (071) of the coincidence member (07), the output (72) of which is connected to the second input (122) of the auxiliary gate. (12) and with a flip-flop input (153) of a flip-flop (15) whose output (154) is coupled to a control input (161) of the first output gate (16), a control input (172) of the second output gate (17) and a control input (103) of a third selection block (10) whose output (104) is connected to a second input (112) of the second comparator (11), the first input (111) of which is connected to the output (142) of the counter (14) and the output (113) ) of the second comparator (11) is connected to the first input (121) of the auxiliary gate (12), the output (123) of which is connected to the flip-over input (151) of the flip-flop (15) and the second input (132) of the logical sum block ), whose output (133) is connected to the reset input (141) of the counter (14) and the first input (131) tového block (13) is connected to the reset input (152) of the flip-flop (15) and an outlet (093) from the non-equivalent block (9), whose second input -3 256 845 (092) is coupled to the output (082) of the sign bit memory (08), the input (081) of which is connected to the sign input (001) of the wiring, to the first input (091) of the non-equivalent block (9) an input (162) of the first output gate (16) and a gating input (171) of the second output gate (17), the output (173) of which is connected to the second wiring output (006), the first output (005) of which is connected to the output (163) ) of the first exit gate (16).