CS266423B1 - Multiple automatic delay corrector for digitized video signals - Google Patents

Abstract

A multiple delay corrector of digitized image signals containing two or more memory blocks is solved, to whose data inputs are input digitized signals with different delays and from whose outputs a time-aligned digital signal is taken. Writing into partial memory blocks is controlled by address generators of write addresses, which are time-linked to the sources of synchronization signals of the respective image sources. Reading data from all memory blocks is controlled by a single generator of read addresses, which is time-linked to the reference synchronization generator of the center.

Description

The present invention relates to a multiple automatic delay corrector for digitized video signals in a television center, which solves the time equalization of signals by means of digital memories.

Delay correction of video signals from different distances at the input of the overhead device is essential to ensure a smooth transition between signals during their overhead processing. · This correction is currently performed in a number of ways. pulse power supply or manual or automatic adjustment of the advance of the secondary synchronizers for aped signal sources · Each of these methods has its specific disadvantages and only the development of digital technology allowed optimal solutions · Digital technology allows to implement a very simple system of automatic correction in the image signal path using digital memories · A digitized image signal is recorded in these memories, while the storage of data in the memory is controlled by address generators for writing and reading of data from the memory is controlled by address generators for reading · A similar method using large-capacity memories is commonly used esynchronous signals from external sources using so-called · synchronizers, as well as for the correction of time errors of magnetic recording, etc. · Recently, this principle is beginning to be used to correct the delay of video signals, especially in centers with digital signal processing · The disadvantage of known solutions is that each input signal has a digital signal

- 2 266 423 memory, including an address generator for writing and an address generator for reading with the relevant circuits, which results in a relative complexity of the device and considerable economic demands ·

This disadvantage is solved by a multiple automatic delay corrector of digitized video signals according to the invention, comprising two or more digital memory blocks, the data input of which is connected to the output of a digital signal source and the input of write addresses is connected to the output of a write address generator. The essence of the present invention is that an output from a single read address generator is connected to the read addresses of the memory blocks, the input of which is connected to the output of the reference synchronization signal source for the overhead device.

The advantage of the multiple automatic delay corrector of the digitized video signals according to the invention is a substantial circuit simplification, which results in a reduction in volume, power consumption and price.

An example of an arrangement of a multiple corrector according to the invention is schematically shown in the accompanying drawing.

The corrector consists of a series of memory blocks 11, 21, etc. in this particular case only two of them are drawn · The output of the first digital signal source 12 is connected to the data input of the first memory block 11, the output of the second source is connected to the data input of the second memory block 21 22 of the digital signal and analogously any other memory blocks and signal sources can be connected. signals for the digital signal source 12 · The output of the second generator 23 * 3 * is connected to the input of the write addresses of the second memory block 21

266 423 write addresses, the input of which is connected to the output of the second source 24 of sync signals, which is simultaneously the source of sync signals for the second source 22 of digital signal. · All sources 12. 24 · or other synchronization signals are frequency-controlled from the reference generator £ of the center · The output of the read addresses of all memory blocks 11, 21 etc. · The data outputs of the memory units 11 and 21 marked in rows 15 and 25 are connected to the inputs of the overhead device. resorts · Velvet multi-multiple kerekter delay digitalizeva signals is marked on the enclosed drawing inside the dashed eblast ·

The data inputs of the first and second memory blocks 11 and 21 are received from the respective, i.e. first and second sources 12 and 22 of the digital signal, the digital signals. 23 write addresses which are time-bound to the first and second sources 14 and 2, respectively, of the synchronization signals of the respective signal sources. but the phase is different, because it depends on the length of the cables, the delay in the partial regulations aped · Data storage corresponding to the same ebrazeven elements of the first and second memory of the flash 11 and 21 therefore takes place in different time intervals ·

The data signals read from the partial memory blocks 11 and 21, or others, must have the same phase at the input of the overhead device 2, and therefore only one ge is sufficient for their reading.

- 4 ·

266 423 a read address regenerator χ, which is also connected to the reference synchronization generator £ of the center and supplies read addresses to all memory bis ΐχ, 21 «or others.

The invention can be used in multiple time correctors for digital and analog centers * who bring further savings by reducing the number of secondary synchronization circuits, the possibility of common generation of embedded recovered synchronization signals, etc.

Claims (1)

OBJECT OF THE INVENTION Multiple automatic delay corrector of digitized video signals comprising at least two memory blocks, to the data input of which the output of the digital signal source is connected and to the input of the write addresses the output of one write address generator is connected, the input of which is connected to the output of the sync signal source. of the respective image source, characterized in that the output of the single read address generator Bick (3) is connected to the read address inputs of the memory blocks (11, 21), the input of which is connected to the output of the reference synchronization signal generator (4).