CS270260B1 - Connection for uniform decoding of sequential circuit states in two-wire logic - Google Patents

Abstract

The solution concerns decoding the states of sequential circuits used in two-wire logic. So far, two separate branches have been used in the construction of secure logic systems, one of which operates in positive logic and the other in negative logic. The disadvantage of such connections is the fact that functionally identical circuits in both branches operate in the opposite mode of operation. This complicates the evaluation of states, especially in counters and similar sequential circuits, which makes it necessary to solve similar circuits in both branches of the logic with different connections. These disadvantages are eliminated by the circuit arranged in such a way that the output (11) of the sequential circuit (1) is connected to the group of address inputs (21) of the permanent memory (2) with two subranges, whose address input (22) of the highest address order is connected to the output (53) of the switch (5), whose first input (51) is connected to the output (31) of the source (3) of the logical one, while the second input (52) of the switch (5) is connected to the output (41) of the source (4) of the logical zero. The data output (23) of the permanent memory (2) with two subranges is connected to the output terminal (6) of the decoded state. The circuit is used in the circuits of the external adapter of the disk module and the two-channel module of the EC 1027 computer.

Description

(57)

The solution relates to the decoding of sequential circuit states used in two-wire logic. So far, two separate branches have been used to design secure logic systems, one working in positive logic and the other in negative logic. The disadvantage of such wiring is that the functionally identical circuits in both branches operate in the opposite mode of operation. This complicates the evaluation of states, especially for counters and similar sequential circuits, making it necessary to solve similar circuits in both branches of the logic with different connections.

These disadvantages are overcome by an arrangement arranged in such a way that the output (11) of the sequential circuit (1) is connected to a group of address inputs (21) of a dual sub-range non-volatile memory (2). a switch (5), the first input (51) of which is connected to the output (31) of the logic one (3), and the second input (52) of the switch (5) is connected to the output (41) of the logic zero. The data output (23) of the dual memory sub-range permanent memory (2) is connected to the output terminal (6) of the decoded state. The wiring is used in the external disk module adapter and dual channel EC 1027 computer circuits.

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The invention relates to a circuit for uniformly decoding sequential circuit states in two-wire logic.

So far, two separate branches have been used to design secure logic systems, one working in positive logic and the other in negative logic. The disadvantage of such wiring is that the functionally identical circuits in both branches operate in the opposite mode of operation. This complicates the evaluation of states, especially for counters and similar sequential circuits, making it necessary to solve similar circuits in both logic branches with different wiring.

These disadvantages are eliminated by the circuitry for uniformly decoding sequential circuit states in the two-wire logic of the present invention, wherein the sequential circuit output is connected to a group of two sub-range permanent memory address inputs whose address input of the highest address order is connected to the switch output. the first input of which is connected to the output of the logic 1 source, the second input of the receiver being connected to the output of the logic zero source, and the data output of the dual sub-range permanent memory is connected to the output terminal of the decoded state.

The main advantage of the circuitry according to the invention is that the sequential circuits in both branches of the two-wire logic can be solved identically; the actual resolution is made only by connecting the first or second switch input. Permanent steam! with two sub-ranges then evaluates the states of sequential circuits.

The attached drawing illustrates an example of a wiring for uniformly decoding sequential circuit states in two-wire logic.

The output 11 of the sequential circuit 2 is connected to the group of address inputs 21 of the permanent memory 2 with two sub-ranges, whose address input 22 of the highest address order is connected to the output 53 of the switch 2. switches 52 2 s ^e connected to the output of source 41 £ logic zero. The data output 23 of the dual sub-range non-volatile memory 2 is connected to the output terminal 6 of the decoded state.

The function of the circuit according to the invention is as follows:

The permanent memory 2 with two sub-ranges simultaneously decodes the states of the sequential circuit 7 needed for both branches of the two-wire logic. Decoding is performed by selecting the appropriate memory location group. The signals on the output group 23 of the dual sub-range non-volatile memory 2 corresponding to the selected branch are switched by the branch select signal; this signal is transmitted to the address input 22 of the highest address order of the permanent memory 2 with two cell sub-ranges from the logical one source 2, or from the logical zero source 6.

The circuitry for uniformly decoding sequential circuit states in two-wire logic is used in the external disk module adapter and dual channel computer EC 1027 circuits.

Claims (1)

SUBJECT OF THE INVENTION A circuit for uniformly decoding sequential circuit states in two-wire logic, characterized in that the output (11) of the sequential circuit (1) is connected to a group of address t-inputs (21) of a dual memory sub-range (2) whose address input (22) the highest address order is connected to the output (53) of the switch (5), the first input (51) of which is connected to the output (31) of the logic one (3), the second input (52) of the switch (5) 41) logic zero sources (4) and the data output (23) of the dual memory sub-range permanent memory (2) is connected to the output terminal (6) of the decoded state.