CS271518B1 - Connection of current parallel analog-to-digital converter with feedback - Google Patents

Abstract

The solution eliminates a multitude of comparators and resistors as well as the large decoder in comparison with the parallel analogue-digital converter and shortens the conversion time in comparison with other parallel analogue-digital converters. This enables the conversion of the quickly changing analogue signal into the digital signal parallel in the binary and direct code, or in the direct code with a drift and self-complementing code, according to the configuration. The current Norton comparators enable the use of an asymmetric current supply and asymmetric reference source. The merit of the solution concerns the fact that the terminal of the input signal is connected to the input resistance network, which is connected to the inverting input of the first to an n-th current comparator, where n is the number of bits of the current parallel analogue-digital converter with the feedback. An adjusting inverter is connected to the direct output of each voltage comparator and to the inversion output of the first current comparator. The control inputs of the coupling switches are connected to the inversion output of each of the n-1 current comparators. The analogical inputs of the coupling switches are connected to the dividing resistance network with the outputs to the coupling resistance network, which together with the reference resistance network, setting the resistance network and quantising resistance network are connected to the first to the n-th current comparator. The bias diode is connected to the dividing resistance network and through the leakage resistance networks to the coupling resistance networks. The terminal of the reference source is connected to the reference resistance network, dividing the resistance network and to the analogue input of the setting switch, to whose control input, the setting terminal and to who's output the setting resistance network is connected.<IMAGE>

Description

• The present invention relates to the involvement of a current of the parallel analog to digital converter with feedback that solves the problem of converting an analog signal into a signal digital binary code directly, or directly with the movement and the complementary code, the short conversion with a minimum number of the active power, _(tronic components.

The parallel analog to digital converter used so far is the fastest and in principle the simplest converter, but for each quantization level it has a comparator and a resistor in the reference voltage divider involved, which means that the number of comparators m ^ and the number of resistors i ^ increase with n. by relationship:

m _K =, m _R = 2 ⁿ -1.

By increasing the number of bits, the decoder circuit at its output is unbearable. Moreover, analog-to-digital converters are characterized by a substantially longer conversion time, which makes it impossible to convert rapidly changing analog signals and, when sensing multiple signals sequentially connected to a single converter, increases the time between sensing individual signals.

The above drawbacks are overcome by the wiring of a parallel-to-analog current-to-analog current converter in accordance with the invention. SUMMARY OF THE INVENTION The input signal terminal is connected to an input resistive network connected to the inverting input of the first through n th current comparator, where n is the number of bits of a parallel-to-analog back-to-back converter. A multiplier inverter is connected to the direct output of each current comparator and to the inverse output of the first current comparator. Each direct and inverse output of the first η - 1 current comparators is connected to the control input of one of the coupler switches, whose analog inputs are connected to the splitter resistor network and the outputs to the coupler resistor networks, which together with the reference resistor network, resistor network and quantization resistor are connected to inputs of the first to η'th current comparator. The biasing diode is connected to a resistive divider network and via leakage resistive networks to coupling resistive networks. The reference source terminal is connected to the reference resistor network, the resistor network, and to the analog input of the setting switch, to whose control input the setting terminal is connected, and to the setting resistor network.

The advantages of connecting a parallel-to-analog back-to-back converter with poor coupling are that the conversion takes place in a short time and with a minimum number. current Norton comparators, where the number of resistors ^M m _R increases with the number of bits n according to the relation:

m _R = 2n + 3n + 2

This implies that as the number of bits exceeds 6, the number of resistors drops sharply compared to a parallel analog-to-digital converter. The adjustment switch allows the work of a water sprite in a binary code direct. or in direct offset and in additional code. Current Norton comparators allow to use unbalanced power supply and unbalanced reference source.

An example of wiring a parallel parallel analog-to-digital converter with a bad coupling is shown in the attached drawing.

From the drawing, it is clear that the transducer expand the Perchlorethylene bits inserting a current comparators with respective the matching inverters and resistance to _r with op resistor networks, the lines between the current comparators 2 a ^and inserting a pair binding switches with appropriate binding and leakage resistor networks in the column between the coupler switch 12 and 13, to places marked by dashed lines.

For the sake of clarity, I describe the connection of a four-bit current parallel analog-to-digital converter with bad coupling. The description of the multi-bit converter is similar. The current from the input signal terminal 28 is routed through the input resistor network 18 to the inverting input py of the current Norton comparators 2, 2, 4, 6. The direct outputs of the current comparators 2 ^& apos ;, 2 &apos; ^{and the} inverse output of the current comparator 2 &apos; are coupled to the multiplier inverters 2, 2, 2 &_apos;, which adjust the output voltage of the current comparators 2 &apos; The direct outputs of the current comparators 2 »2, 2 control the switching switches 11, 13, 22» which, via the coupling resistor networks

21, 23, 25 connect the currents from the reference source terminal 37 to the inverting inputs of the current comparators 2, 6, 7. The inverse outputs of the current comparators 2, 2, 2 control the couplers χ2, 14, 22, which, via the resistive networks 22, 24, 26, connect the currents from the reference source terminal 37 to the non-inverting current comparator inputs 2, 4, 6. The resistive divider network 17, 27 together with the reference resistive network 19, the bonding resistive networks 21, 22, 23, 24, 25, 22 »the lead resistive networks 31, 32, 33, 34, 35, 22 ^{and the} quantization resistive network 29 form a ladder resistive network a network with resistance values R and 2nR, as denoted by 44 in the drawing, wherein "n" is the number of bits of the converter. The value of the currents connected to the inputs of the current comparators 2 »2» 2 3 ^{e is} proportional to half the value of the current comparator bit 2) 2 »2» which this current by means of the switch 22, 22 »

13, 14, 22 »22 connects. In addition, currents from the reference source terminal 37 are permanently coupled to the inverting inputs of all current ^comparers 2 ^, 2 ^, 2 ^, 2 through the quantization resistor network 29. The value of these currents is proportional to the half value of the least significant bit, LSB. These currents adjust the correct position of the quantization levels. Currents whose value is proportional to the value of the weight of the least expensive bit, MSB, are connected to the non-inverting inputs of all current comparators 2, 2, 2, 2 via the reference resistor network. These currents represent the flip-over levels of all current comparators 2, 2, 2, 3, and their effect is canceled by the same value currents connected from the reference source terminal 37 by the setting switch 10 controlled by the logic level signal applied to the setting terminal 30. These currents are routed through the adjusting resistor network 20 to the inverting inputs of all current comparators 2 &apos;, 2 &apos; and 2 &apos;. This solution also maintains a permanent bias at the current (Norton) comparator inputs. 2 »2» 2 »2 · ^{When the} setting switch 10 is open, the converter operates in binary direct code, the output signal is at terminals 39, 41, 22» £ 2 · ^{When the} setting switch 10 is closed, the converter operates in binary direct code with offset, output signal is at terminals 39, £ 2 »£ 2, £ 2 ^{and in the} full code, the output is at terminals 40, £ 2, £ 2, £ 2 · Part of the currents of the bonding resistor network 22» 22 »22» 2 £ »22 »2 ^e J ducted creeping distances resistor network £ 2» 22 »22» £ 2 »22» £ 2 and a bias dioadou 38 к zero potential. The bias voltage drop on the diode 38 is equal to the bias of the inputs of current comparators 2 »2» 2 »£ · ^The bias diode 38 is also connected resistive divider network 22, 27th

For the sake of a simplified description of the function of the current parallel analog-to-digital feedback converter, I call the flip of the current comparator 2 »2» 2> £ ^{to the} state as output: 39, £ 2 »£ 2 ^e logical value of H, H Flip inverting the current comparator 2 »2» 2 »£ L and ^r which is the output ^e 22» £ 1 »£ 2» £ 2 of the matching of the inverter 5, £, £, £ logic value L, In our example, we assume a 4-bit current parallel analog-to-digital converter with a feedback (hereinafter referred to as a converter). The setting switch 10 is open, which means that the converter is operating in binary direct code. The current, which is proportional to the least significant bit weight, LSB is I. Then the currents in resistive networks 2θ> 20, 22 »22»

22, 23, 24, 25, 26, 29 at which it will к inversion of the individual nozzle komparáto ^Equation 2 »2» 2 »£ ^{Budd me} t values:

7.5 + 0 + 0.5

3.5 + 0 + 4 + 0.5 + 0

1.5 + 0 + 4 + 2 + 0.5 8 + 0 + 2

0.5 + 0 + 4 + 2 + 1 + 0.5 + 0 + 0 + 0 = 8 I current comparator £ = 8 I = 81 current comparator 2 = 8 I = В I current comparator 2 = 8 I = 81 current comparator £ = 8 I

The distribution of the current values is identical to the distribution of the individual resistances of the resistor networks 18, 20, 19, 22, 22 »22, 24, 22, 24, 22» ^{in the} drawing through which these currents flow.

The current connected to the input signal terminal 28 is n multiple of the input current of one current comparator 8, 2, 2, 6. In our example, 4 times, at zero input current, all current comparators 8, 2, 2, 4 are switched to L. Binding switches 11, 2, 15 are switched on and connect to inverting inputs of current comparators 2, 3, 6 via bonding resistive networks 21, 23, 25 of current from terminal 37 of the reference source. At the output of the converter 22, 4L, 42 43, the value is 0000. The flip-flop of the current comparator 6 into H occurs when the input current level exceeds 4 x 0.5 = 21. At the output of the converter 22, 42, 42 »42 ^{e e} value 0001. When the input current rises above 4 x 1.5 -61, the current comparator 3 flips to H. At the same time the coupling switch 15, the switch opens the coupling switch 16 and connects via the coupling resistor 26 the current from the reference source terminal 37 to the non-inverting input of the current comparator 6, which flips to L. At the output of the converter 22, 42, 42, 42 0 ^{e the} value 0010. The currents at which the current comparator 6 flips will have values;

2.5 + 0 + 4 + 2 + 0 + 0.5 = 9 I

Θ + 0 + 0 + 1 = 90

It has shifted the flip-over level of the current comparator 6 from 0.5 l to 2.5 l. When the input current rises above 4 x 2.5 = 10 l, the current comparator 4 flips to H. At the output of the converter 22, 42, 42 »42. Ó ^e value ООП. When the input current rises above 4 x 3.5 = 14 I, the current comparator 2 flips to H. At the same time, the coupling switch 13, the spin switches the coupling switch 14 and connects the currents from the reference source terminal 37 to the non-inverting inputs of the comparators 2. 4, which flips to L. At the same time as the current comparator 2 is switched ^{to L, the} switch 6, the switch 15 opens and connects the current from the reference source terminal 37 to the inverting current comparator input 6 via the coupling resistor 25. However, it does not flip because the value of the current connected by the switch 14 is twice the value of the current connected by the switch 15. At the output of the converter 22, 42 »42, 42 the value 0100. The currents at which the current comparators 2, 4 :

5,5 + 0 + 4 + 0 + 0.5 = 10 8 + 0 + 2 = 10 4,5 + 0 + 4 + 0 + 1 + 0.5 = 10 8 + 0 + 2 + 0 = 10

Current comparator

The current comparator 8

I

Flip levels shifted:

from 1.5 l to 5.5 l for current comparator 3 and from 2.5 l to 4.5 l for current comparator 6

The increase in the input current of 4 x 4.5 = 18 I, a current comparator flips £ to C. At the output of the converter 22, А2 »42» 42 I ^t is the value of 0101. The increase in the input current of 4 xx 5,5 22 tilts current I ^the comparator 2 · ^H-bond extends parallel switch £ 2, spina-bond the switch 16 and connected through a resistor 26, the binding terminal 37 of the current reference source · the non-inverting input of current comparator-4, which tilts the L at the output of the converter 39, 41, 42, 43 is the value of 0110. The currents at which the current comparator 4 is overturned will have the following values:

6.5 + 0 + 4 + 0 + 0 + 0.5 = 11 I + 0 + 2 + 1 = 11 I

The flip-flop level of the current comparator 8 has been shifted from 4.5 I to 6.5 I. If the input current rises above 4 x 6.5 = 26 I, the flip-flop current comparator 4 to H. At the converter output 39, 41, 22, 43 value 0111. When the input current rises above 4 x 7.5 -301, the current comparator 2 toggles ^to H. At the same time, the coupler switch 11, the spin coupler switches 12, and connects the current from the reference source terminal 37 to the non-inverting current inputs. When the current comparators 2, 2 are flipped ^to L, the coupler switches 14, 2a, switch the coupler switches 13, 15 and connect currents from the reference source terminal 37 through the coupling resistor networks 23, 25. the inverting input of current comparator 2, £ · ^For the tilting will not occur, however, because the total current of the binding of connected switches 13, 15 L ^much smaller than the currents accompanying the binding sp By the switch 22 · The output of the converter 22, 41, 42, 43 is the value 1000. The currents at which the current comparators 2, 2, 2 are overturned will have values:

11.5 + 0 + 0 +0.5 + 4

9.5 + 0 + 9 + 2 +0.5 + 4 + 0

I current comparator 2

I

I current comparator 2

I

8.5 + 0 + 0 + 2 + 1 + 0.5 = 12 I current comparator 4

8 + 4 + 0 + 0 = 121

Flip levels shifted:

from 3 5 I on the 11 = > 5 I at current comparator 2 from 5 5 I on the 9th 5 I at current comparator 2 until 6 5 I on the 6th 5 I at current comparator 4

It is evident from the present description that we can continue in the same way up to the maximum converter range, 1111. As the input current decreases, the current comparators 2, 2, 2, 2 are flipped ⁱⁿ reverse order to the zero value of the input current.

When the setting switch 10 is switched on, the converter operates in a binary direct code with offset and in an additional code. Then flows through the resistor network 18, 20, 22, 22, 22, 22, 24, 25, 2, 22 F ^or who develop к inversion of each current comparator 2 2>2> 2 will have the values:

-0,5-8 8 + 0.5 = 8 = 8 I I jet comparator 2 3.5 + 8 + 0 + 0.5 = 12 I jet comparator 2 8 + 4 1.5 + 8 + 0 + 2 + 0.5 = 12 I jet comparator 2 8 + 4 + 0 0.5 + 8 + 0 + 2 + 1 + 0.5 = 12 I jet comparator 4 8 4 + 0 + 0 = J2 I

CS 271518 Bl

At zero input current, the current comparator 6 is flipped to H and connects via a link switch 12 through the resistive network 22 of the current from terminal 37 of the reference source to the non-inverting current comparator inputs 2 »2» ktoré which are flipped to L. 41, 42, 43 in offset binary direct code is 1000. At the output of converter 0, 41, 42, 43 in additional code is 0000. From the distribution of input currents it is clear that the current comparator 8 of the most valid bit, MSB determines sign of the polarity of the input signal both in the direct offset code and in the supplementary code. Moreover, current comparators 2, 2> 1 are F ^or the pitch of the input current to operate, as in the work of the transmitter in the direct code. Next, I describe the work of the converter in binary direct code with offset, when the input current decreases. When the input current drops below 4 x (-0.5) = 2 I, the current comparator 6 flips to L. At the same time, it opens the switch 12, the spin switch 11 and connects the current from the reference source terminal 37 to the inverting inputs At the same time as the current comparators 2, 3 are flipped to H, they switch the coupling switches 13, 5, switch on the other switches 16, 16 and connect them via the coupling resistor networks 24, 26. from terminal 37 of the reference source for the non-inverting input of current comparator 2 »A · ^their flipping does not occur because the value of the currents flowing binding resistive network 21 is larger, but the sum of currents flowing binding resistor network 2 £ 26 at the output of the converter 39, 41 .

42, 43 the value 0111. Streams, which occurs when к flipping individual current comparator COM 2, 2 »2» £ HUD T ^has values:

- 0.5 + В + 0.5 = 8 = - 4.5 + 8 + 4 + 0.5 =

0 + 0

- 2.5 + 8 + '.4 + 0 + 0,5 = 8 + 0 + 2 = -1,5-8 + 4 + 0 + 0 + 0,5 = 8 + 0 + 2 + 1 =

I current comparator 1

I

I current comparator 2

I

I current comparator 2

I

The current comparator 8

I

Flipping levels shifted:

from 3.5 L to - 4.5 L for the current comparator 2, from 1.5 L to - 2.5 L for the current comparator 2, and from 0.5 L to - 1.5 L for the current comparator 6.

If the input current drops below 4 x (-1.5) = - 6 I, the current comparator lá flips to L. At the output of the converter 22 »£ 1» £ 2.43 the value is 0110. When the input current drops below 4 x (-2 5) = -10 I, the current comparator 2 flips to L. At the same time, it disconnects the coupler 16, the spin coupler 15 and connects the current from the reference source terminal 37 via the coupling resistor 25 to the inverting input of the comparator 6, which flips to H. 22 converter »£ 1» £ 2 »£ 2 J ^e 0101. value of current at which dčjde к flipping current comparator £ will have values:

- 3.5 + 8 + 4 + 0 + 1 + 0.5 = 10 I 8 + 0 + 2 + 0 = 10 I

The flip-flop level of the current comparator £ has shifted from - 1.5 I to - 3.5 I. If the input current drops below 4 x (-3.5) = 14 I, the current comparator £ flips to L. At the output of the converter 22 »£ 1 »£ 2» £ 2 value 0100. When the input current drops below 4 x (- 4,5) = - 18 I, the current comparator 2 flips ^to L. At the same time it opens the coupling switch £, the switch opens the coupling switch 13 and connects via the coupling resistor. current network 23 from terminal 37 of the reference source to inverting inputs of current comparators 24 which flip to H. When current comparator 2 ^{d is} switched, ^d 9 H opens the switch 15, switches the switch 16 and connects the current from terminal 37 via the resistor 26 reference source on noninvert

However, the current comparator input 2 is not flipped because the current flowing through the resistor network 23 to the current comparator input 4 has twice the value of the current flowing through the coupling resistor 26. At the output of the converter 39, 41, 12 »43 is 0011 The currents at which the current comparators A are overruled will have values:

-6,5-8 + 4 + 2 + 0.5 = 8 I jet comparator 3 8 + 0 + 0 -5,5-8 + 4 + 2 + 0 + 0.5 = 9 I jet comparator 4 8 + 0 + 0 + 1 = 9 I There has been a shift levels tilting:

from - 2.5 L to - 6.5 L for the current comparator 2 and from - 3.5 L to - 5.5 L for the current comparator 4.

It is already apparent from the present description that the current parallel-to-analogue converter with bad coupling works equally with both positive and negative input signals.

Wiring a parallel parallel-to-analog back-to-back converter can be used wherever it is necessary to convert an analog signal to a digital signal in a binary direct code or in a direct offset and ancillary code. Its use can be extended by connecting the comparator with the polarity sign and the absolute value circuit in front of the input signal terminal 28. When the setting switch 10 is opened, the signal converter is thus obtained in a binary direct code sign.

Claims (1)

Inverse current-coupled parallel analog-to-digital converter connection, characterized in that the input signal terminal (28) is connected to an input resistor network (18) connected to the inverting input of the first to nth current comparators (1, 2, 3, 4), n is the number of bits of the current parallel analog-to-digital converter with a bad vazboy, with an adaptive inverter (5, 7, 8, 9) connected to the direct output of each current comparator (1, 2, 3, 4) and to the inverse output of the first current comparator (1) , 6) and on each direct and inverse output of the first η - 1 current comparators (1, 2, 3) is connected control input of one of the couplers (11, 12, 13, 14, 15, 16), whose analog inputs are connected to the resistive network (17, 27) and outputs to the coupled resistive networks (21, 22, 23, 24, 25, 26), which together with the reference resistive network (19), the adjusting resistive network (20) and the quantization resistor network (29) are connected to the inputs of the first to nth current comparator (1, 2, 3, 4), the biasing dio da (38) being connected to the resistive divider network (17, 27) and via a leakage resistor networks (31, 32, 33, 34, 35, 36) to the three-phase resistor networks (21, 22, 23, 24, 25, 26), and the reference source terminal (37) is connected to the reference resistance network (19) , a resistive divider network (17, 27), and an analogue input of the adjusting switch (10) to which the control terminal (30) is set and the adjusting resistor network (20) is output.