CZ20003371A3 - A method and system for high-speed signaling for connecting an LVSI CMOS circuit to an interface - Google Patents

Abstract

The method and system uses a small amplitude differential synchronous voltage source and time reference signals (SSVTR and /SSVTR) to compare simple signals with the same time offset, generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals are toggled each time valid signals are controlled by the transmitting integrated circuit. Each signal receiver (210) includes two comparators (410a, 410b), one for comparing the signals against the SSVTR and the other for comparing the signal against the /SSVTR. The binary value of the signal present determines which comparator (410a, 410b) is connected to the output of the receiver, optionally using XOR logic with the SSVTR and /SSVTR. A connected comparator (410a410b) in the receiver detects whether a change in the binary value of the signal has occurred or not until SSVTR and/or SSVTR have changed their binary value. The same comparator (410a, 410b) is connected if the signal changes. The comparator (410a, 410b) is disconnected when no change occurs. The system uses a first set of oscillating reference signals on a first bus to detect changes in control information and a second set of oscillating reference signals to detect changes in data information.

Description

Method and system for high-speed signaling for interfacing LVSI CMOS circuits

Technical area

The present invention relates generally to computer signal communication, and more particularly to integrated circuit interfaces and to a method of high-speed, block-based signaling of data, control, and address signals between a group of integrated circuits on a bus or from one to another, with reduced power consumption.

State of the art

Semiconductor integrated circuits used in digital computing and other digital applications often use a group of interconnected VLSI (Very Large Scale Integration) circuits to implement binary communication over single or multi-segment transmission lines. Conventional transmission lines comprise traces that are formed on a suitable substrate, such as a printed circuit board. Each transmission line may be constructed, for example, using so-called microstrip traces from tape traces to form a transmission line having a characteristic impedance of the order of about 50 to 70 ohms. Each transmission line may optionally have its opposite ends terminated with their characteristic impedance as well. The output load on the control circuit for such a transmission line may be as low as about 25 to 35 ohms.

In order to consume a reasonable amount of current, high-frequency signaling requires signals with small amplitude. In order for the receiver to easily detect voltage swings (for example, from 0.8 V to »··« «4 ·· • · · · · · · ·

1.2 V) in a noisy environment such as GTL, HSTL, SSTL or RAMBUS, the current must also be very large (for example, on the order of 50 to 60 milliamps per control circuit). A typical receiver uses a comparator with a reference voltage signal (VREF) located midway between the input high voltage (VIH) and the input low voltage (VIL). The VREF signal is a high-impedance DC reference voltage that tracks the supply current freely in time but cannot respond to instantaneous noise. The high output voltage (VOH) and low output voltage (VOL) conventionally refer to the signals coming out of the transmitting source, and VIL and VIH refer to the signals coming into the input of the receiving device, although they can be considered the same signal.

Fig. 1A is a block diagram illustrating a prior art receiver 10 using RAMBUS technology. The system 10 includes a solder pad (PAD) 100 connected by signal lines 103 to internal input receivers 110. A VREF signal 105 is connected to each internal receiver 110. VREF is generated from a current supply. The DC value of the current supply typically varies by 5%. Fig. 1B is a timing diagram 125 illustrating an example of a signal waveform versus a high reference voltage (VREFh) and a low reference voltage (VREF1). The values of VREFh and VREF1 are typically dependent on the variation of the current supply used to generate the VREF signal. For reliable detection of signal polarity, a large voltage swing, i.e., the difference between the high voltage signal (VIH) and the low voltage signal (VIL), and stable signal levels above and below the VREF signal are required. The voltage range of current single-signal technologies is conventionally around 0.8 V.

Fig. 1C is a block diagram schematically illustrating a prior art receiver 150 using RAMBUS technology. Receiver 150 samples the level of input signal 167 and VREF signal 154 until the signal reaches a stable level, at which point pass gates 160 and 165 are turned off. Once pass gates 160 and 165 are turned off, sense gate 172 is activated to eliminate current ingress. Fig. 1D is a timing diagram 175 illustrating the operation of receiver 150 for an example signal. Receiver 150 samples the input reference signal and the input signal until the signal reaches a stable level, e.g., a logic low (VIL), and while the input signal is stable, receiver 150 senses the value of the input signal. As noted above, for signal detection to be reliable, the signal voltage swing must be fast enough to allow all receivers 150 to sample a stable signal with adequate margin for setup and hold times. This voltage swing should occur during less than 30% of the minimum cycle time to allow margin for the signal time shift, setup, and hold times. As the minimum cycle time decreases below 1 nanosecond, the margins for the time shift, setup, and hold times decrease, and an additional load on the current in the control circuit is the high capacitive load from the high-frequency operating environment. Low-voltage differential signaling (LVDS) used in IEEE P1596.3 can overcome these problems by using a 250 mV voltage swing at the expense of running complementary signals. Running complementary signals inevitably increase the number of pins and the size of the package.

Computer systems also typically utilize a bus system in which multiple devices are connected to the bus. Most of these use a clock to check the validity of data, address, and control signals. Fig. 21 shows a prior art system 21QQ for DRDRAM that uses a clock line 2130 having two segments 2136 and 2138. One segment 2136 extends from one end of the data bus to a turning point 2137 near the other end of the bus. A second clock segment 2138 extends from the turning point 2137 back to the first end of the data bus. The signal bus 2120 carries data, address, and control signals. This topology ensures that a signal sent onto the bus 2120 always travels simultaneously with and in the same direction as the clock 2132 used by the device to receive the signal. This works well if the sampling of all signals and clock pulses is nearly identical and the 2132 clock is used to sample and receive the signal. However, sometimes a system might require twice as much bandwidth for data, in which case this type of bus system requires double the number of signals even though the address and control signals are identical and could be shared.

Accordingly, there is a need for low power control circuits and reliable receivers for high frequency operation of a large number of simple signals in existing technology for low cost VLSI digital systems.

The essence of the invention

The system according to the present invention uses small-amplitude synchronous voltage and timing reference signals from a differential source (Smali Swing differential source synchronous Voltage and Timing Reference signals, hereinafter abbreviated as SSVTR and /SSVTR) to compare simple signals of the same amplitude, generated from the same integrated circuit for high-frequency signaling. It will be considered an advantage that / is used to indicate a logical NOT (NOT). All signals are terminated with their characteristic impedances at both ends of the transmission lines. SSVTR and /SSVTR switch each time valid signals are transmitted by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal with SSVTR and the other for comparing the signal with /SSVTR. The binary value present in the signal determines which comparator is connected, ··*» ·«

9· 999 ·9 99« or by using EXCLUSIVE-OR logic with SSVTR and /SSVTR. As long as SSVTR and /SSVTR do not change their binary value, an associated comparator in the receiver detects whether a change has occurred in the binary value of the signal. Again, it will be considered advantageous that SSVTR and /SSVTR change their binary value every time the signal can change its binary value. SSVTR and /SSVTR are preferably synchronized with the signal.

The method of the present invention includes the steps of obtaining an oscillating source of a synchronous voltage and time reference and its complementary signal (SSVTR and /SSVTR), and receiving an input simple signal. The method compares the oscillating reference signal with the input signal /by a first comparator to produce a first result and compares the complementary signal with the input signal by a second comparator to produce a second result. The method then selects one of the first result or the second result as an output signal based on the previous signal. The step of selecting one of the results includes comparing the output signal with the reference signal (SSVTR) and with the complementary signal (/SSVTR). The step of selecting further includes manipulating the output signal from the previous signal to the first result or the second result according to the comparator that is currently connected. If the input signal changes, the step of selecting includes keeping the same comparator connected. If the input signal remains the same, the step of selecting includes disconnecting the currently connected comparator and connecting the second comparator. The method then allows the circuit to stabilize.

The system and method advantageously eliminate the need for a high impedance VREF signal for comparison of small amplitude simple signals. This reduces the need for three distinct voltage levels (output high level, output low level, and VREF level) to two distinct voltage levels (output high level and output *

9··· low level). Elimination of VREF reduces the required voltage swing and consequently reduces current consumption. The use of a receiver with two comparators allows the receiver to be connected to the same comparator when the signal changes every cycle. Based on the instantaneous binary value of the signal and SSVTR, only one comparator is connected. The system has an individually adjustable delay for each receiver to connect or disconnect the comparator, thereby reducing the effect of time shift during the transmission of the source synchronous signals. The system may have multiple differential sources of synchronous voltage and time reference signals to compare multiple simple signals in the same integrated circuit, such as a microprocessor or a system controller that has many signals. The system and method provide the advantages of differential signaling in a simple signaling system.

Using the same concept, a complementary source of synchronous reference signals can be used to compare bidirectional single signals. The system may have a control circuit or transmitter to control the signal tracking rate so that it is a substantial portion of the total signal period, thereby reducing the output current. The system may have internal impedance matching circuits such as pull-up resistors or a grounded gate p-channel to match the characteristic impedance of the transmission line at both ends of the connection between the CPU and the cache or between the CPU and the system controller. The system has a comparator pair circuit to convert a single bus with two complementary signals intended to be transmitted and received with comparable noise immunity to a differential bus for an internal memory data bus, processor, or other wide data bus type integrated circuits. The system advantageously has a variable size transmitter device with slow turn-on and slow turn-off to have similar tracking speeds for all signals in each SSVTR and /SSVTR group and the group of signals that are transmitted together. It will further be considered an advantage that the control signals and address signals can be transmitted on a different channel than the data signals. This allows the control and address channels to operate at a different frequency than the data channel and allows different loads to be used for each of the channels.

Overview of images on the drawing

Fig. 1A is a block diagram illustrating a RAMBUS-based receiver according to the prior art.

Fig. 1B is a timing diagram illustrating signal levels in the prior art receiver shown in Fig. 1A. Fig. 1C is a schematic diagram illustrating another prior art RAMBUS-based receiver.

Fig. 1D is a timing diagram illustrating the operation of the prior art receiver of Fig. 1C.

Fig. 2A is a perspective view of a block diagram illustrating a master-slave system according to the present invention.

Fig. 2B is a block diagram illustrating the system of Fig. 2A having transmission lines with impedances corresponding to the resistors at the ends.

Fig. 3A is a timing diagram showing differential reference signals SSVTR and /SSVTR in relation to signal sampling times.

Fig. 3B is a timing diagram showing SSVTR and /SSVTR versus a simple signal.

Fig. 4 is a high-level diagram illustrating single signal receivers.

Fig. 5 is a flow chart illustrating a method of transmitting signals from a transmitter over a transmission line to a receiver.

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4444 44 44 44« 44 444

Fig. 6A is a circuit diagram showing a slow-on and slow-off control circuit for all signals.

Fig. 6B is a circuit diagram showing control circuits having adjustable signal tracking rates and time shifts between signals.

Fig. 7A is schema engagement receivers simple-minded signal shown in fig. 4, in the first version * Fig. 7B is schema engagement receivers simple signal shown in fig. 4 in the second execution. Fig. 7C is schema engagement receivers simple signal shown in fig. 4 in the third execution. Fig. 7D is schema engagement receivers simple-minded signal

shown in Fig. 4 in the fourth embodiment.

Fig. 8A is a circuit diagram showing the details of the SSVTR to /SSVTR comparator circuit of Fig. 4.

Fig. 8B is a circuit diagram showing the details of the SSVTR to /SSVTR comparator circuit of Fig. 4.

Fig. 9 is a circuit diagram showing receivers with individually adjustable delays to eliminate time drift during transmission.

Fig. 10 shows the signal waveforms and the time shift between them. Fig. 11 is a three-dimensional view of the hardware arrangement of the system shown in Fig. 2.

Fig. 12A is a block diagram illustrating a device-to-device interconnection system according to the present invention.

Fig. 12B is a block diagram illustrating an interconnection system according to the block diagram of Fig. 12A having impedance-matched gate p-channel devices within an integrated circuit.

Fig. 13A is a block diagram in perspective showing a unidirectional signaling system and a bidirectional signaling system on a single integrated circuit.

Fig. 13B is a block diagram in perspective showing four signaling systems on a single integrated circuit.

«»·· ·* ** ·»» ·· ··«

Fig. 14A illustrates a fixed reference voltage, according to the prior art, whose value is around the midpoint of the logic high level and the logic low level voltage.

Fig. 14B shows a complementary reference signal that has the same voltage range as each other signal.

Fig. 15A shows a differential amplifier that amplifies the difference between the data signal and the reference signal.

Fig. 15B is a block diagram illustrating the control logic.

Fig. 16 is a circuit diagram showing a single signal receiver with differential amplifiers gated by a current drop or receiver enable signal to turn off current to the receiver when not in use.

Fig. 17 is a timing diagram illustrating the signal transfer time for an application requiring a rapid bus transition from a read to a write state or vice versa.

Fig. 18 is a block diagram illustrating a system of connections from one device to another.

Fig. 19 shows a system having multiple buses where signals are received simultaneously.

Fig. 20 is a block diagram illustrating a system having three buses to achieve higher bandwidth.

Fig. 21 illustrates a prior art system for DRDRAM that uses a clock line having two segments.

Examples of embodiments of the invention

The present invention provides a signaling system and method for high-speed communication on multiplexed buses or device-to-device connections between a group of VLSI devices and provides lower power consumption compared to current methodologies for interfacing single signals. The signaling system can be used to connect a group of memory devices with a multiplexed bus to a memory controller for • ·*· • «

- 10 block transfer of data, address and control information. By using multiple buses, devices such as DRAMs, cross-field switches, processors, wide SRAMs and system controllers can be brought together to achieve bandwidths in excess of four gigabytes per second. Essentially all signals needed for a computer or other digital system can be sent over this bus. Those skilled in the art will appreciate that all devices such as CPUs in a computer system need the methodologies and bus structures of this system.

Fig. 2A is a perspective view of a block diagram illustrating a system 200 with a master device (transmitters) 205 connected via a bus architecture (transmission lines) 215 to a group of slave devices (receivers) 210 according to the present invention. As shown, the master device 205 is arranged to communicate, for example, twenty (20) signals, including simple signals S0 through S17, small amplitude synchronous voltage and time reference signals SSVTR and /SSVTR from a complementary source, power lines (not shown), and ground lines (not shown) in parallel with the transmission lines 215 to each slave device 210. 2a It will be appreciated that / is used to denote a logical NOT (NOT). Signals S0 to S17 may be data, control, or address, either multiplexed or non-multiplexed, as defined by the protocol. There may be other signals, such as clock or initialization, for other purposes required by the protocol or for system synchronization.

As shown in FIG. 3A, the signals SSVTR and /SSVTR are toggled each time valid signals are controlled by the control device 205. It will be appreciated that the slave device 210 may include a group of receivers 405, see FIG. 4, each receiver 405 including two comparators, one for • »*·

- 11 comparing the signal with SSVTR and the second for comparing the signal with /SSVTR. The binary value of the signal present determines which comparator is connected to the output terminal 420, optionally using EXCLUSIVE-OR logic with SSVTR and /SSVTR. As long as the binary value of SSVTR and /SSVTR does not change, the activated comparator in the receiver 405 detects whether a change in the binary value of the signal has occurred.

For chip-to-chip communication on a bus or device-to-device, all signals are preferably transmitted substantially simultaneously from the same chip to another chip or group of chips connected to the bus and preferably have substantially the same load, amplitude and tracking speed (when the signals are transient). For intra-Chip communication, signals are also preferably driven at substantially the same time, from the same area or block to other areas or other blocks on the same chip and preferably have substantially the same load, amplitude and tracking speed (when the signals are transient). Figs. 19 and 20, described below, illustrate a system and method for ensuring that the signals are driven at substantially the same time.

To facilitate extremely high data rate transfers over this external bus, bus cycles are invoked when SSVTR is low (i.e., /SSVTR is high). The entire block transfer will begin during the cycle when SSVTR is low and will end when SSVTR begins to fall to facilitate presetting the receiver 405 for the last binary value of the signal. This allows for even-numbered bit burst transfers. When signals need to change direction (due to the multiplexed nature of the signals), one or more dead cycles may be required to quiet the bus due to propagation delays or to quiet the SSVTR and /SSVTR when they are bidirectional. Fig. 17 described below illustrates the bidirectional timing for bus turnaround to avoid lost dead cycles.

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Fig. 2B is a block diagram illustrating a system 200 (Fig. 2A) having transmission lines 215 with external impedance matching resistors 220 having a termination resistance equal to their characteristic impedance, which is preferably in the range of 50 to 70 ohms at the ends. The voltage at the ends is designated VTT and is preferably about 1.8 V at an operating voltage of 2.5 V (for VCC being 2.5 V and VSS being 0 V). The nominal voltage swing is preferably set to less than IV, preferably less than 40% of the supply voltage, and most preferably is set to 500 mV. Therefore, as shown in Fig. 3A, the output high voltage (VOH) is 1.8 V and the output low voltage (VOL) is 1.3 V.

Fig. 3A is a timing diagram showing the complementary reference signals SSVTR and /SSVTR versus the signal read times. SSVTR initiates at VOL and /SSVTR initiates at VOH. In the first cycle, the controller 205 drives all low signals including /SSVTR to VOL simultaneously and the termination resistors 220 pull SSVTR to VOH. Single signals that are high are held at VOH by the termination resistors. The proper read time, i.e. the time to read the logic level of the input signal, is after the transition of the SSVTR and /SSVTR connections and before the stable time, i.e. when SSVTR or /SSVTR reaches a steady state at VIH or VIL. SSVTR and /SSVTR preferably have equal rise and fall times, with each rise and fall time being approximately half the cycle time of one of the reference signals.

Fig. 3B is a timing diagram showing SSVTR and /SSVTR relative to a simple signal. The simple signal starts out equal to /SSVTR at a high voltage and then changes with /SSVTR to a low voltage. The simple signal then remains at a low voltage, becoming equal to SSVTR, and then changes with SSVTR to a high voltage. The simple signal then remains at a high voltage, becoming equal to /SSVTR.

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- 13 Fig. 4 is a high-level diagram illustrating a simple signal slave device 210 having a receiver 405 for each signal line 215. Each signal receiver 405 has two comparators 410, one comparator 410a for comparing the input simple signal SNx with SSVTR and a second comparator 410b for comparing SNx with /SSVTR. Both comparators 410 have output terminals selectively connected by switches 415 to an output terminal 420. It will be appreciated that the output signal (SN) to the output terminal 420 is preferably a full-range signal (0 V to 2.5 V).

As noted above, SSVTR is initially set to VOL and /SSVTR and SNx are initially set to VOH. SN is initially set to a high full-scale output voltage. Accordingly, comparator 410a amplifies the high voltage SNx minus the low voltage SSVTR, thereby providing a high output signal. Comparator 410b amplifies the high voltage SNx minus the high voltage /SSVTR, which provides an unknown output signal given the noise gain. The selection of switch 415 is controlled by EXCLUSIVE-OR (XOR) logic gates 425. More specifically, XOR gate 425a compares the full-scale amplified SSVTR signal (VT) against the output signal SN and produces a control signal for control switch 415a. XOR gate 425b compares the full-scale /SSVTR (/VT) against the output signal SN and produces a control signal for control switch 415b. In this initial state, only SSVTR and accordingly VT are low, causing XOR 425a to drive switch 415a closed. Accordingly, the output (high) of comparator 410a reaches output pin 420. XOR 425 drives switch 415b open, thereby preventing the input of an unwanted output signal from comparator 410b. Receiver 405 is stable.

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- 14 According to the example shown in Fig. 3B, the simple signal SNx changes to a low voltage. As always, SSVTR and /SSVTR change in opposite directions to each other. Accordingly, once SSVTR and /SSVTR reach a predetermined difference (preferably 250 mV) between each other, VT and /VT change. Similarly, once SSVTR and SNx change to a predetermined difference (preferably 250 mV) between each other, the output of comparator 410a also changes (to a low output voltage). It will be appreciated that the path from the external signal SNx to produce the output signal SN and the path for the full-scale signal VT and /VT each include one comparator 410 or 435 and two inverters 430 or 440. Each XOR gate 425 therefore receives new input signals based on the comparison rate of comparators 410 and 435. In this example, as can be seen in the example timing diagram of FIG. 3B, SSVTR and /SSVTR reach a predetermined difference at the same time that SSVTR and SNx reach the same predetermined difference. Accordingly, XOR 425a will continue to receive differential inputs, thereby keeping the same switch 415a closed and allowing the low output voltage from comparator 410a to pass to output terminal 420. Receiver 405 is still stable.

Also, according to the example of Fig. 3B, the simple signal SNx is not converted. As always, SSVTR and /SSVTR are changed relative to each other. Accordingly, the comparator 410a, which has just been activated, continues to drive a low output voltage. When SSVTR and /SSVTR reach a predetermined difference with respect to each other, but before SSVTR reaches the same voltage as SNx (thus preventing the possibility of an indeterminate output signal state), XOR 425a is turned off and XOR 425b is turned on. It will be considered advantageous that since /SSVTR begins to increase, comparator 410b could drive a low output voltage. Receiver 405 is still stable.

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ΒΒΒ ΒΒΒ ΒΒΒ «ΒΒΒ ΒΒ ΒΒ ··· ΒΒ Β·Β

- 15 Each receiver 405 can easily detect and amplify very small signals on the order of 100 to 250 mV. If the transformation has occurred in the simple signal SNx, the output signal SN has a new level that is the opposite of its previous signal level. Since both the SSVTR (or /SSVTR) and the simple signals have changed, the same comparator 410 is still connected to the signal output terminal. If the simple signals SNx have not changed, then the signal output SN does not change, the comparator 410 connected at the beginning of the transformation is disconnected from the output after the receiver SSVTR and /SSVTR have amplified their new binary state (VT & /VT) and the second comparator 410, which has the opposite /SSVTR (or SSVTR) is connected to ensure the signal output. The old output level is thus restored.

It will be appreciated that the receiver 405 can be implemented without the use of XORs. This can be implemented by using the known polarity of SSVTR and /SSVTR in the initial cycle and by having all simple signals start high. SSVTR and /SSVTR change on each cycle. Their polarity on each cycle can thus be determined by checking the system clock in a synchronous system and defining the cycle start on even clock cycles (i.e., SSVTR is low on even clock cycles and /SSVTR is high). Only the output signal SN is then monitored as it connects and disconnects the comparators 410 based on whether or not the output signal SN changes state each cycle. If the output signal SN changes state, the connected comparator is left alone. If the output signal SN does not change, the connected comparator is disconnected and the other comparator is connected, etc.

It will be considered a further advantage that the system according to the invention allows all signals to be connected to low impedance sources, allows all signals to present voltage and noise conditions substantially differentially in noise immunity and allows for a reduction in voltage swing compared to other working technologies « ···

- 16 with simple signals such as RAMBUS, HSTL or GLT. The small 0.5 V swing implemented in this exemplary embodiment allows for very high signal rates with much lower current consumption compared to other simple signal processing technologies. It is further advantageous that each receiver 405 amplifies the simple SNx signals during signal conversion without the need for a conventional clock or other timing signal other than SSVTR, /SSVTR and their amplified versions VT and /VT.

Fig. 5 is a flow chart illustrating a method 500 of communicating signals from a control device 205 over a transmission line 215 to a receiver 405. The method 500 begins with the control device 205 setting SSVTR to VOL and all single signals (/SSVTR and SNx) to VOH in step 505 and setting all single outputs (SN) of the receiver to full high in step 510. The receiver 405 connects a comparator 410a, which compares SSVTR to each single signal SNx, to an output terminal 420 of the receiver 405 in step 515. The receiver 405 settles all signals on the transmission lines in step 517. Steps 505 through 517 are referred to as system initialization.

The controller 205, in step Λ2.0, simultaneously drives SSVTR n /SSVTR to their opposite states and all simple signals SNx to their desired levels. The receiver 405, in step 530, compares the simple signal SNx against SSVTR and /SSVTR in the respective comparators 410. The receiver 405, in step 540, determines whether the simple signal has been converted. If so, then the receiver 405, in step 545, transmits the result to the output terminal 420 and maintains the same comparator 410 connected to the terminal 420. If not, then the receiver 405, in step 550, disconnects the previous comparator 410, connects the second comparator 410 to the output terminal 420 and maintains the same output signal (SN). Transmitter 405 in step 555 • ·44 • 4 · ·

4 4 4 4 4 *

- 17 determines whether the signal burst continues. If so, then method 500 returns to step 520. Otherwise, method 500 ends.

Fig. 6A is a schematic diagram illustrating the slow turn-on and slow turn-off of the control device 205 for a single signal in a first embodiment referred to as a transmitter 600. The transmitter 600 includes a pull-down NMOS device 605 connected to a transmission line 610 for precisely adjusting the output swing to 500 mV below VTT. The pull-down NMOS device 605 includes a pull-down NMOS transistor TI having its source connected to the transmission line 610, its collector connected to ground, and its gate connected to a time shift control circuit 620. The time shift control circuit 620 includes a CMOS inverter including two transistors T2 and T3 connected between two resistors, R1 and R2. The input to the CMOS inverter is connected to a signal control device 625. For example, to generate SSVTR or /SSVTR, the signal control device 625 may be an oscillator. It will be appreciated that the amount of pull-down can be adjusted using a register (not shown) and a serial pin (not shown) during initialization to set the correct voltage range for all variations of the method and device. Other methods may also be used, such as using coupling techniques for control, as shown in Hans Schumacher et al., (CMOS Subnanosecond True-ECL Output Buffer), J. Solid State Circuits, vol. 25(1), pp. 150-154 (February 1990). Maintaining the current at 20 mA and having parallel 50 ohm terminals at both ends of the transmission line 610 (as controlled by R1 and R2) produces a 500 mV swing under all conditions. In order to have slow rise and fall times at the output and to minimize reflections, noise from network switching when connecting and disconnecting the signal, the shift control circuit 665 controls the pull-up transistor TI to turn on and off slowly. The preferred tracking speed is 1.6 ns/V with transition times 0.8 ns for 500 mV.

For a uniformly varying ramp-like signal, the preferred signal tracking speed is four times the sum of the two inverter delays and the EXCLUSIVE-OR delay in the given technology. For 0.25 μ CMOS technology with an operating voltage of 2.5 V, the inverter delay is 50 picoseconds and the EXCLUSIVE-OR delay is approximately 120 picoseconds. The preferred tracking speed is approximately 880 picoseconds. For signals transmitted above 600 MHz, the signal tracking speed is preferably less than 110% of the signal speed. The preferred tracking speed for exponential signals is slightly faster if the signal reaches 75% of its final value earlier than during the transition period. Differential signals preferably cross over halfway through the voltage change. In the middle of the voltage change, the signals have a difference of about 250 mV, which can be quickly converted to a large-swing signal. To avoid noise amplification and to avoid coupling the signal to the receiver output after receiving non-transitional simple signals, the transition time between 75% and the final signal value is preferably greater than the sum of the two inverter delays and

EXCLUSIVE-OR delay. It will be appreciated that the tracking speed can be as fast as the amplified noise reaches the output of comparator 410, the output of which is connected to output pin 420. This means that upon receiving a non-changing signal, switches 415 switch states before the comparator output changes state based on the noise amplification. The output of the currently connected comparator 410 is approaching an indeterminate state (only the noise amplified). Switches 415 must switch states before the indeterminate output becomes available. It will be appreciated that device mismatches, manufacturing tolerances, and signal reflections will affect the speed at which the output of comparator 410 reaches the indeterminate state. As technology improves, gate delays, faster tracking speeds, and faster signal speeds can be achieved.

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Fig. 6B is a schematic diagram illustrating a control device 205 having adjustable signal tracking rates and time shift between signals for another exemplary embodiment referred to as a transmitter 650. The transmitter 650 includes an NMOS pull-down device 655 connected to a transmission line 610 for precisely adjusting the output amplitude to 500 mV below VTT. The NMOS pull-down device 655 includes pull-down NMOS transistors 660 connected in parallel, each having its source connected to the transmission line 610, its collector connected to ground, and its gate connected to a time shift control circuit 665. The time shift control circuit 665 includes a CMOS inverter including two transistors T2 and T3 connected between two sets of resistors 670 and 675 connected in parallel. The input to the CMOS inverter is connected to a signal control device 625. Resistor sets 670 and 675 tune the rise and fall times. It will be appreciated that the rise and fall times are preferably as symmetrical as possible, so as to have the midpoint of all signals crossing and sensing all signals by the differential receivers appear simultaneously. Achieving symmetry and adjusting the tracking speed and output swing can be accomplished during the test phase by fuses (not shown) or during initialization on the board by setting a register (not shown).

It will be considered an advantage that the signal change times can be slightly greater than the signal rate. On some heavily loaded buses, the swing can be increased to take care of transmission losses and still get 500 mV to the receiver 210 for easy sensing. It will be considered an additional advantage that different tracking speeds, exponential transition times and voltage swings are possible based on the technology, the load and reception and the receiver resolution delays. Even transition times slightly greater than the signal rate are possible with • ··· «···· «··· »·* ·· ·· ·»· ·· ♦··

- 20 transition signals reaching 90 to 95% of their final value during clustering. Also during testing, the offset between the single signals and the SSVTR and /SSVTR is adjusted using the size of the NMOS pull-down and the resistors in the gate ahead of it using well known techniques such as laser fuse burning or register code adjustment to achieve the signal waveform as shown in Fig. 10. As shown in Fig. 10, all of the single SNx signals should be coincident or less than 50 ps before the SSVTR and /SSVTR transitions. This time offset can be adjusted after testing to be within this range.

Fig. 7A-7D illustrate alternative embodiments of each signal receiver 405 of Fig. 4. It will be appreciated that the comparators 410 of the receiver 405 need to operate during each cycle, requiring small acquisition and discrimination delays, drawing no input current and returning no current to the signal lines. A conventional differential amplifier satisfies all of these requirements. Referring to Fig. 7A, the receiver 210 uses dual differential amplifiers 702, one differential amplifier 702a for comparing the SNx signal to the SSVTR and the other differential amplifier 702b for comparing the SNx signal to the /SSVTR. A brief overview of the differential amplifiers 702 is provided for completeness. The differential amplifier 702 is always enabled. Based on the channel sizes, when the SSVTR voltage is higher than the SNx voltage, more current is drawn through the ΡΜΟΞ transistor T10, pulling the output voltage at node 707 up (approaching VCC or 2.5 V). When the SSVTR voltage is less than the SNx voltage, more current is drawn through the NMOS transistor T1, pulling the output voltage at node 707 down (approaching VSS or 0 V). The differential amplifier converts a small-scale (0.5 V) input to a large-scale (0 V to 2.5 V) output.

• 999 • 99 ttt 9 9 9 9*99 99 99 999 «9 99«

- 21 The outputs from the differential amplifiers are amplified and inverted by inverter 704, passed through CMOS transmission gates 706, and connected together at node 708. Transmission gates 706 are selectively operated depending on the amplified state of the previous signal (SN) subjected to an EXCLUSIVE-OR operation with the amplified state of SSVTR or /SSVTR, i.e. VT or /VT. The EXCLUSIVE-OR is designed to be stable without short spurious pulses for small timing variations between Sn, VT, and /VT reaching their respective logic levels.

Various embodiments are illustrated. Fig. 7A shows differential amplifiers always enabled, with only the transmit gates selectively enabled for a small number of devices and higher speed as an alternative embodiment 700. Fig. 7B shows the differential amplifier and transmit gates enabled or disabled simultaneously as an alternative embodiment 720. Fig. 7C shows differential amplifiers that are enabled by the same EXCLUSIVE-OR for low current, fast deactivation of the transmit gates during the EXCLUSIVE-OR output transfer, and slow activation of the transmit gates after the EXCLUSIVE-OR is stable as an alternative embodiment 740. Fig. 7D shows P-channel differential amplifiers with a 1.2 V terminal voltage for lower current applications as an alternative embodiment 760. All gates of the differential amplifier can be disabled to reduce current when no receiver is selected or when no device is selected or when the device is deep in a low current mode. The differential amplifier can be disabled by turning off transistor Til.

By using a 1.2 V termination and a 405 receiver as shown in Fig. 7D, the current consumption can be further reduced by another 33%. This means that the voltage swing will be from 1.2 V to 0.7 V, allowing for decent margins from undershoot and lower • ··· • · · · · · · ·· ·»«

- 22 power consumption for portable systems. The operating frequency may be comparable with fewer devices on the buses, which is common with portable devices for a smaller form factor. Transmitter 205 may still be an NMOS pull-down TI or a parallel connection of pull-down NMOS transistors 660. Receiver operation is similar except that differential amplifier 706 becomes a mirror image, thereby increasing the gate capacitance of signals going to the P-channel gate for comparable operation by approximately twofold due to the increased size of the p-channel device. Other differential amplifier configurations that rapidly convert small amplitude differential signals to large amplitude differential signals may alternatively be used in place of the differential amplifiers shown. One skilled in the art will appreciate that another embodiment may use two different VTTs, one for signals equal to 1.8 V with a 500 mV swing and the other for oscillating reference signals equal to 1.7 V with a 300 mV swing. All signals change simultaneously and have similar rise and fall times. The same transmitter and receiver pair may handle a multiple VTT system.

It will be considered advantageous that the DC bias point of each differential amplifier in receiver 405 is arranged such that the output voltage of receiver 405 is above half of VCC when both small swing voltages (single signal SNx and SSVTR or /SSVTR of the activated differential amplifier) are close to VIH and below half of VCC when both small swing voltages are close to VIL. This DC bias allows for proper margin and protection of the output signal SN when the single signal SNx does not change state and the SSVTR or /SSVTR of the activated differential amplifier closes the differential signal before it is disconnected.

• ·· ·«·*·« 9 · 9 • 999 ·» 99 *« *· ···

- 23 Because the receiver 405 operates during signal conversion for a low-amplitude single signal, the concept of a setup and stable time from a specified time after the signal level reaches VIH/VIL or VREF, used in previous signal processing techniques, is no longer used. There is also no VREF (reference voltage) to compare with the signal voltage. By eliminating the timing required for setup and hold and the timing required to activate the voltage edges to sense around VREF, the operating frequency is greatly increased with lower current consumption. Furthermore, all receivers 405 are self-clocked, without the need for a global clock, which allows the receivers 405 to be individually adjusted to eliminate board or package level transmission timing drift.

Fig. 8A and 8B are schematic diagrams illustrating in detail the circuit details of the comparators 435 of Fig. 4. Each comparator 435 includes a differential amplifier 802 (Fig. 8A) or 852 (Fig. 8B) similar to the differential amplifier 702 of Fig. 7A and multiple inverters 804 (Fig. 8A) or 854 (Fig. 8B) in series. The full-range output signals of the comparators 802 and 852 (VT1, VT2, VT3, /VT1, /VT2, and /VT3) are transmitted to all of the XOR gates 425 of the single-signal receivers (Fig. 4). The selection of VT1, VT2, or VT3 is determined based on signal speed testing in much the same way as the selection of the output signal generation path SN of the receiver 405.

Fig. 9 is a schematic diagram showing receivers 405 with individually adjustable delays to eliminate time drift during transmission and convert small swing to large swing using comparators 410. In order to tune the operating frequency or voltage swing for optimum operation, each receiver 405 has a data storage register 905 to enable the delivery of one of three • ··· • · • · · · ··*·· ··· ··· »· ι» ««r ···

- 24 VT1 and /VT1, VT2 and /VT2 or VT3 and /VT3 to XOR gate 425 (Fig. 4).

Fig. 11 is a perspective view of a hardware arrangement of a combined control device 1100 for bidirectional signal communication. The control device 1100 includes receivers 405 and return transmitters 1105 coupled together. More specifically, each simple signal received as signal S0 is coupled to a corresponding receiver 405 as receiver S0 and to a corresponding transmitter 1105 as transmitter TO. All of the simple signals SNx may advantageously be grouped together with a single pair of reference signals SSVTR and /SSVTR. However, those skilled in the art will appreciate that for a given operating frequency, the loading of SSVTR and /SSVTR and signal imbalance reduce the number of SNx signals that may be grouped together. As can be seen in Fig. 11, the arrangement is implemented such that the capacitances, resistances, and inductances on SSVTR and /SSVTR and all of the simple signals SNx are balanced. Since SSVTR and /SSVTR also lead to all receivers 405, the total load on SSVTR and /SSVTR needs to be minimized.

By using very low-loss devices and physical compaction, the bus can be made as short as possible, which in turn allows for short propagation times and high data rates. As shown in Fig. 2B, resistor-terminated, controlled-impedance transmission lines can operate at signal rates of 1 GHz (lns cycle). The performance of transmission lines is greatly affected by the loading caused by integrated circuits such as DRAMs that are mounted on the bus. These integrated circuits add one-time capacitance to the line, which both reduces the line impedance and reduces the transmission speed. In a loaded environment, the bus impedance will likely be on the order of 25 ohms and the propagation speed will be 7.5 cm/ns. Care must be taken to ensure that the bus is not controlled from « ··· • ·

- 25 two devices simultaneously, so for buses smaller than about 12 cm, one dead cycle (e.g. 2 ns) is needed to stabilize the bus to switch from one master device to the other master device. For longer buses, more than one cycle may be needed to allow the signals to stabilize before the new transmitter can control the signals. Unlike RAMBUS, the length of the bus does not reduce the operating frequency in burst mode from the same device.

Fig. 12A is a perspective block diagram illustrating a point-to-point system 1200 that includes a bidirectional master device 1205 connected by transmission lines 1215 to a bidirectional slave device 1210. Transmission lines 1215 include an upper signal SNx line 1220, a lower signal SNx line 1225, and SSVTR and /SSVTR lines 1230. As shown in Fig. 12B, a perspective block diagram illustrating a point-to-point system 1200 that includes termination resistors 1235 internally using grounded gate P-channel devices. This eliminates the need for external resistors and reduces cost. It will be appreciated that termination resistors 1235 can be implemented using internal resistors instead of grounded gate P-channel devices. Termination of both ends with a suitable characteristic impedance is advantageous for bidirectional signals on the bus. Since the on-chip blocks are physically close together, impedance matching resistors are not necessary. Small step-up devices are sufficient. Similarly, when the on-chip connections are physically close together, impedance matching resistors can be replaced with small step-up devices to reduce cost and current and to maintain the same tracking speed.

It will be appreciated that multiple buses are desirable for devices such as SLDRAM, DDR SDRAM, or various DDR SRAMs where signals are transmitted and received simultaneously. Fig. 13A « · « · Β · «ΒΒ ««ΒΒ ΒΒ ΒΒ ·«« «« ΒΒΒ is a perspective view of a block diagram illustrating a combined unidirectional and bidirectional system 1300 for SLDRAM on a single integrated circuit. The system 1300 includes a control device 1305 (e.g., a memory controller) connected via transmission lines 1315 to slave devices 1310 (e.g., SLDRAMs). The controller 1305 transmits address and control signals over address and control lines 1320 and 1325, transmits and receives data signals over data lines 1330 and 1335, transmits a first set of SSVTR and /SSVTR reference signals (i.e., SSVTR0 and /SSVTR0) on SSVTR and /SSVTR lines 1340 for checking the address and control signals, and transmits a second set of SSVTR and /SSVTR reference signals (i.e., SSVTR1 and /SSVTR1) to the slave devices 1310. The address and control portion of the system 1300 organizes unidirectional signals needed only by the slave devices 1310. The data portion of the system 1300 is bidirectional, based on whether the control signal specified a READ or WRITE operation.

For SLDRAM, the 40-bit command and address are sent in a packet of four 10-bit words. SSVTR0 and /SSVTR0, which may be referred to as the differential system clocks, operate at 500 MHz. A phase-locked loop (not shown) is used to lock the clock frequency and timing for various internal purposes and to control the data output with SSVTR1 and /SSVTR1 at both edges for a 1 GHz data rate. All high-frequency signals are terminated at both ends of the bus with their characteristic impedances. Termination at the end of the memory controller may include external resistors, internal resistors, or internal grounded gate P-channel devices, since this memory controller is typically the master device and is fixed. Since the number of components (SLDRAMs) 1310 (which operate as slave devices) is variable, components 1310 are preferably terminated with external resistors at the end of the transmission lines. 18-bit bidirectional • ··· ·»·»·· · · · ···· 94 94 ··* ·* ··*

- 27 data bus 1330 and 1335 operate at the same frequency as the system clock for synchronization and send data in eight 18-bit words in four clock cycles (8ns) of the clock or 2.25 gigabytes/s from a single SLDRAM. Care is taken to balance the load on SSVTRO and /SSVTRO by adding dummy gates and lines to make them appear comparable to SSVTR1 and /SSVTR1. This load balancing causes the tracking speed given by the load to be similar and allows similar margins for all signals.

When higher bandwidth is required, the system 1350 may utilize four buses as shown in FIG. 14B. Two separate channels of SLDRAMs 1310 are used with a single memory controller 1305. This arrangement allows for a peak data bandwidth of 4.5 gigabytes/s. Although the system 1350 does not require a synchronous clock for the transmitter 1305 or the receiver 1310, the system 1350 may utilize a synchronous clock to transmit data at a specific time and frequency for ease of testing and usability with existing synchronous DRRM and SRAM protocols. It may be desirable to use an on-chip multiplier or slow clock or internal circuit oscillator to transmit data at a high frequency without a high-speed clock for synchronization to reduce system noise and current. It will be appreciated that those skilled in the art can achieve variously sized, synchronous, or asynchronous very wideband systems using the teachings of the present invention.

Five concepts are explained in more detail below, which further explain the input and output circuits 210 of FIG. 4,

The first concept concerns the existence of complementary reference signals. As shown in Fig. 14A, prior art systems use a fixed reference voltage VREF whose value is around the midpoint of the logic high voltage level (VOH) and the logic low voltage level (VOL). The VREF generator (not

Μ· ·*···« · · · *«·· ·· ·· ·«· ·*

- 28 shown) typically has some DC bias from fluctuations in the power supply used to generate it, these fluctuations being shown as VREFH" and VREFL. It also has some AC noise due to instantaneous voltage fluctuations in the power supply, ground reflection, capacitive coupling and inductive coupling with adjacent signals. The differential swing to the comparator used in the prior art receiver is shown by the arrows. It should be noted that the differential signal in the worst case according to the prior art will be on the order of 1/3 to 1/4 of the total voltage swing of the signal.

As shown in FIG. 14B, the systems and methods of the invention employ a complementary reference signal SSVTR and /SSVTR that have the same voltage range as each signal (e.g., data or control). In a particularly preferred embodiment, this voltage range is 500 mV with a logic high voltage (VOH) of 1.8 V and a logic low voltage (VOL) of 1.3 V. It will be advantageous to consider that the average of the complementary reference voltages is about the center of VOH and VOL at any time during operation of this signaling system. The signals and the complementary reference signal have the same transition times and voltage ranges and are initiated simultaneously from the same source (same device for inter-chip communication or the same general location for intra-chip communication) to be sent to the receiver. In other words, the complementary reference signals look the same as any other signal, but the complementary reference signals are flipped each time other signals need to be transmitted. Since the complementary references use the power supply and ground simultaneously, all noise is common mode. Therefore, the variation of the VREF value (VREFH and VREFL) of the signal amplitude, required in the prior art, is no longer required in the systems and methods of the present invention. Due to the binary nature of digital signaling, there will always be one complementary reference signal • ··* βββββ·β··ββ • Β Β Β Β « · · · »»·» ** ΒΒ ΒΒΒΒ ΒΒΒΒ ΒΒΒΒ

- 29 opposite polarity than the signal at the beginning of the reference signal transition and at the end of the reference signal transition. Therefore, one reference value present at a time will have a total swing of about 500 mV, allowing the comparator to sense the signal voltage more easily than a prior art system that has only 1/3 to 1/4 of the total signal swing. The signal and reference signal conversion time may be half the conversion time required by the prior art to achieve the same differential signal during a signal change. Those skilled in the art will appreciate that for optimal operation, VOH and VOL should be set somewhere between a few hundred mV below the power supply and a few hundred mV above ground, with a difference of 500 mV between them. The difference can be further reduced to 200 mV to 300 mV if device mismatch is reduced and the signals have little or no reflections, especially for intrachip communication.

The second concept involves having two comparators for each incoming signal. Referring again to FIG. 4, since the signal is compared to two complementary reference signals, each receiver 210 has two comparators. One compares the SNx signal to SSVTR and the other compares the SNx signal to /SSVTR. At the beginning of the burst conversion, the comparator with the fully differential signal at its input is connected to the output of the receiver 210, and the other comparator, which has no differential signal, is disconnected from the output of the receiver 210. This is done by initialization. If the SNx signal and the connected reference signal change, then the comparator quickly senses the signal as a differential amplifier, rapidly amplifying the signal and driving the output to the opposite state. If the SNx signal does not change (i.e. only the reference signal changes) then the differential input to the comparators, which is connected at the beginning of the reference signal conversion, will decrease continuously during the conversion time, eventually until no differential input is provided. The differential input to the comparators, which is disconnected at

1-14 at the beginning of the reference signal conversion, will increase continuously during the conversion time, possibly until a full differential signal is provided. The originally connected comparator without a differential signal at the end of the conversion is disconnected and the originally disconnected comparator with a full differential signal at the end of the conversion is connected. The present invention uses two comparators to sense a single signal. Furthermore, the binary nature of digital signals ensures a full amplitude signal on one of the comparators at the beginning of each possible valid conversion.

The third concept concerns initialization. Since only one comparator is connected to the receiver output at a time, it is important for proper operation to have a comparator with a fully differential input signal connected to the output of receiver 210 at the beginning of a burst. Therefore, all signals SOx through SNx are initialized to a logic high VOH. By turning off all control devices, initializing SSVTR to VOL, initializing /SSVTR to VOH, and connecting the signals to termination resistors or p-channel pull-ups with their gates turned on, and with the source connected to VTT (VTT is 1.8 V), current consumption is reduced. The receiver outputs 210 for SO through SN are biased high to VCC using a p-channel device 1615 as shown in FIG. 16 to ensure that the control logic (explained below) connects the fully differential comparator to the output of receiver 210.

The fourth concept concerns the discrimination of signal changes. As is known to those skilled in the art, a differential amplifier is characterized by amplifying small voltage differences into large voltage differences. The voltage gain is typically 3 to 5 times, depending on the size of the device and corresponds to the transistor. An inverter placed after the differential amplifier provides further amplification to achieve almost full swing, depending on the size of the • ···

- 31 devices. The speed of the differential amplifier and inverter in achieving full swing depends on the differential signal available at its input. As shown in Fig. ISA, the differential amplifier (and inverter) 1501 can amplify the conversion of both SNx and SSVTR 1500 very quickly, but when SNx does not change, the signal to the differential amplifier is reduced to noise only and the speed is much slower (relative to mismatch and noise). The converting signal SN' (the output of the differential amplifier and inverter) is shown as a dotted line 1503. The area 1502 to the left of the converting signal 1503 is labeled Change.” The area to the right of the changing signal SN' 1503 is labeled No Change. As noted above, when the signal is not changing, the amplifier 1501 is limited to amplifying only the noise, which is labeled as the indeterminate region 1506. The time period before the amplifier reaches the indeterminate region 1506 is labeled as the time delay region 1504. The present invention has the advantage of allowing the control logic described below to pass the changing signal to the receiver output and to prevent the indeterminate signal from passing through. By choosing the right device sizes and conversion times, a time delay sufficient to operate the control logic so that the signal change passes through, but no signal change passes through and the resulting indeterminate voltage signal does not pass through can be made. It will be appreciated that some indeterminate voltage level can pass through as long as it is less than the logical the threshold of the XOR gate behind it and the second comparator can quickly restore the voltage level. Another advantage will be considered that the time delay depends on the signal amplitude, the reference signal conversion time, process mismatch, signal reflection, etc.

The fifth concept relates to control logic. Referring to FIG. 15B, control logic circuit 1550 connects a corresponding comparator 1555 to receiver output 1560 and is based on timing generated by • 444

- 32 differential amplifier using SSVTR, /SSVTR and the present output of receiver 1553. Control logic 1550 uses SSVTR, /SSVTR and the present output signal of receiver 1553. As can be seen from FIG. 4, initialization of input signals SOx to SNx at VOH, reference signal /SSVTR at VOH, reference signal SSVTR at VOL and receiver output signals Ξ0 to ΞΝ at VCC connects respective comparators 410 to receiver output 420 before starting the burst. For the signal being converted, control logic 1550 does not make a change because XOR control logic 1565 selects the respective amplified reference signal and the receiver output signal. Since both the amplified reference signal SSVTR and the SNx conversion and delay paths for the amplified reference signal SSVTR and for SNx to XOR 1565 are identical, XOR 1565 does not switch. Alternatively, if the input signal is not converted, the previous comparator 1555 that was connected is disconnected and the second comparator 1555 that was not connected is now connected. The output of the signal receiver does not change and is actively controlled by the connected comparator 1555 to restore the output level if desired. Control logic 1550 is designed to occur during the time delay 1504 between the change in signal 1502 and the no change in signal 1506 as explained above.

The control logic is implemented using an individual EXCLUSIVE-OR locally for each comparator for higher speed, better segmentation time matching, and to improve margins or adjustments for time shifts and mismatches. It would also be possible to have all comparators disconnected from their receiver outputs using SSVTR and /SSVTR timing and a single control signal for all receivers of a single bus channel so that it appears at segmentation time during the time delay to reduce the number of devices in the receivers. This would limit the operating bandwidth because a proper comparator must be connected to the receiver output before the next conversion can be started.

94«

9 « 4 4 · 4 4 4 4 4

944 4 4 4 444

4444 4« *4 >44 «4 44

- 33 When all these elements are combined together, the entire signal system operates with the entire signal SOx through SNx and /SSVTR, starting at VOH, the entire output of the signal receiver is pre-charged to VCC, and SSVTR starts at VOL. Before initiating the signal burst by converting the complementary reference signals, all comparators with differential signals on them (SNx and SSVTR) are connected to the receiver outputs. To convert the signals, the control logic allows the signals to drive the output to the opposite edge of the voltage range. For signals that do not change, the control logic disconnects the signals from the current comparator to another comparator to hold or restore the receiver output. The next conversion is chained to continue with the conversions overlapping with the control logic until the control logic delay limits the bandwidth or time interval to allow the next conversion.

As shown in FIG. 16, the single-signal receiver has differential amplifiers with a gate controlled by a current-drop signal or a receiver-enable signal to turn off the current to the receiver when not in use. In contrast to FIG. 7A, the inverters have been replaced by NAND gates 1610 connected to the current-drop signal or receiver-enable signal. In addition, a pull-up transistor 1615 has been connected to node 708 at its collector, to VCC at its source, and to the current-drop signal or receiver-enable signal at its gate to bias SN to VCC. The NAND gate 1615 after the differential amplifiers also achieves the correct polarity at SN to initiate the burst cycle. The desired initial state is to pre-set SNX high, with SNx pulled up by a termination resistor or pull-up device on the signal line, and to pull SSVTR low and /SSVTR up. The remainder of the receiver operation has already been described. The P-channel device at the common node of the transmission gate output is designed to quickly create a high bias voltage at node 708, if necessary, during • ··· • · ···· · ····«> ·· ···

- 34 current rise or when the EXCLUSIVE-OR outputs have not reached stable levels.

By using devices with very low leakage current losses and a large physical compaction, the bus can be made as short as possible, which in turn allows for short propagation times and high data rates. Transmission lines terminated with controlled impedances, as shown in Figure 12, can operate at signal rates of 1 GHz (Ins) or higher. The performance of transmission lines is greatly affected by the loading caused by integrated circuits, such as RAMs, mounted on the bus. These integrated circuits add one-time capacitances to the line, which reduces the impedance of the line and reduces the transmission rate. In a loaded environment, the bus impedance will likely be on the order of 25 ohms and the propagation rate will be 7.5 cm/ns. For an application requiring fast bus turnaround from read to write and vice versa, as shown in Figure 17, the signal conversion time is chosen to be around 25 to 30% of the signal rate (half the cycle time). Amplification is initiated at the next 25 to 30% of the signal rate. The control circuit is turned off to allow the signals to settle at approximately the next 25 to 30% of the signal rate. It will be considered an advantage that the next cycle, when the signal or data direction is reversed, can be performed without loss of bus efficiency where the devices are close together and the bus settling time is less than half the signal rate.

Fig. 18 shows in a three-dimensional representation the connections from the points of one device to the points of another device. By incorporating the termination resistors internally using grounded gate P-channel devices, very powerful systems can be built connecting the points of one device to the points of another device as shown in Fig. 13B. Internal incorporation of the termination resistors eliminates the need for space to connect external resistors and reduces • «·* ···«·· · · · «»«» a« a· aaa a* aaa

- 35 costs. It is also possible to gate P-channel devices on the transmit side to reduce the current required to discharge the signal lines to the desired voltage. Both the CPU and the memory controller have P-channel end devices whose sizes can be chosen to equal the characteristic impedance of the line when their gates are at ground potential. The gates of the P-channel devices use a signal that is the complement of the receiver enable to disable the receiver end and the transmit end. This switching can be done while the receiver is preset high and before the burst on the signal lines is initiated. Internal resistors can also be used in place of grounded gated P-channel devices. By using multiple buses as described in the next section, the bus width to the memory controller can be reduced to 32 (36) from 64 (72) or the bandwidth can be greatly increased. The back-end buffer-to-cache connections on CPU units can also be sped up, the number of pins on the CPU can be reduced, and PBSRAMs can be changed from X36 to X18, reducing size and cost.

Fig. 19 shows a system 1900 having a group of buses for devices such as SLDRAM, DDR SDRAM or DDR SRAM where signals are received simultaneously. The system clock bus 1920 starts from a clock signal source 1915 at the end opposite the memory controller 1905, is connected to all devices 1910 whose data outputs are connected to the bus 1920 and ends at the memory controller 1905. The load on the clock signal is matched to the load on the data output and the reference signals SSVTR1 and /SSVTR1. It will be appreciated that the clock pulses may be differential (preferably) or single-ended depending on the clock frequency and system requirements. The swing of the clock voltage may be similar to SSVTR and /SSVTR to have a similar receiver. In order to have the same delay, * ·Β·

BBB « Β Β · · *··· BB BB BBB BB BBB

- 36 The route length of the clock bus 1920 is matched to the route length of the reference signals SSVTR1 and /SSVTR1. The clock source 1915 introduces SSVTR1, /SSVTR1 and data from the DDRDRAMs at different times depending on their location on the bus 1920, so that the data, SSVTR1 and /SSVTR1 arrive at the controller 1905 at approximately the same time regardless of which DDRDRAM is driving the data. Each DDRDRAM could optionally use a DLL (Delay Lock Loop) to reduce the delay of the clock 1915 to the data if needed for synchronization at the controller 1905. To eliminate an additional pin in a clocked system where data transmission is predictable, a DLL could be used to create an /SSVTR1 having the same timing and voltage parameters but opposite polarity at the receiver end. The DLL would reproduce the clock in all components (including the controller 1905 and the DDRDRAMs 1910). The controller 1905 would be aware of the cycle in which the data is expected to arrive and the reference signal SSVTR1. After initiating a write cycle with address and command signals, the DDRDRAM should know the cycle in which the input data will arrive.

The DLL will only pass the /SSVTR1 signal when the signal is needed for a particular component. The address and command lines can be grouped with SSVTR0 and /SSVTR0. The address and control bus unidirectionally carries input signals from the memory controller 1905 to the DDRDRAMs 1910. The 10-bit command and address are sent in as a 2-bit command and an 8-bit address. The 2-bit command is executed using /CE and /RAS on one signal on two edges of SSVTR0 and /SSVTR0 and the other signal for /CAS and /WE. The 8-bit address on two edges gives up to 16 bits of row address appearing with /CE and /RAS or up to 16 bits of column and block address appearing with /CE and /CAS for a read cycle. The write cycle is executed with 16 bits of column and block address with /CE, /CAS and /WE. SSVTR0 and /SSVTR0 can be derivatives of the system clock (differential) and operate at the same or a multiple of the system clock frequency. As explained above, DLL r « ť I · I · «1| I. · I ' ti II ti· I * « ·

- 37 can be used to lock the clock frequency in the memory controller 1905 for various internal purposes, to control the command and address signals during a read request, and to control the data input, SSVTR1 and /SSVTR1 for write requests.

The invention further differs from the signal handling of RAMBUS by using different reference signals for data inputs (SSVTR1 and /SSVTR1) and for address and control (SSVTRO and /SSVTRO). In RAMBUS, all signals coming into the RDRAM are sampled based on a single clock, whereas in the present invention, the control and address signals are on a different channel than the data signals. This allows the control and address signal channel to run at a different frequency than the data channel. All unidirectional high-frequency signals (address and control signals) are terminated with their characteristic impedance at the end of the bus away from the controller 1905. Since the controller 1905 is usually the controller and is usually fixed, all bidirectional signals (data signals) are terminated at the end at the controller with an external or internal resistor or an internal grounded gate of the P-channel device. It will be considered advantageous that in order to reduce current, the terminating P-channel device can be turned off during the data write cycle. Termination on the controller side is optionally possible and can be a high resistance of around 10 times the characteristic impedance. Since the number of memory components, i.e. slave devices, is variable, the memory components are preferably terminated with an external resistor at the end of the transmission line. The 18-bit bidirectional data bus preferably operates at the same frequency as the system clock for synchronization and preferably transmits data from a single DDRDRAM in four 18-bit words in two clock cycles (4 ns) or 2.25 gigabytes/s.

Care is taken to adapt the load on SSVTRO and /SSVTRO by adding dummy gates and lines to make it appear comparable to SSVTRl and /SSVTRl. This load adaptation is • ···

- 38 tracking speeds are similar and allow for similar margins for all signals. When higher bandwidth is required, three buses can be used as shown in Figure 20. Two separate channels of DDRDRAMs are used with a single memory controller. This configuration allows for a peak data bandwidth of 4.5 gigabytes/s. Address and command signals can be shared between the two channels on SSVTRO and /SSVTRO. The clock and data are split to have a 36-bit data bus using SSVTR1, /SSVTR1, SSVTR2 & /SSVTR2. This saves pins compared to dual-channel RDRAMs of the prior art.)

Although the invention does not require a synchronous clock for the transmitter or receiver, it can use a synchronous clock to transmit data at a specific time and frequency to facilitate testing and is usable with existing synchronous DRAM and SRAM protocols. It may be desirable to use an on-chip slow clock multiplier or internal oscillator circuit to transmit data at a high frequency without a high-speed clock for synchronization to reduce noise and system current. Those skilled in the art can build various sizes of synchronous or asynchronous wideband systems based on the above information.

The above description of particularly preferred embodiments of the present invention are merely examples and other variations and modifications of the above-described embodiments and methods are possible in light of the above-described spirit of the invention. For example, although the system and method have been described as transmitting SSVTR and /SSVTR from the control unit 205 to the receiving unit 405, it will be apparent to one skilled in the art that only one reference signal may be transmitted and a complementary signal may be generated at the receiving unit 405. Alternatively, this technique may be used with other technologies such as bipolar or gallium arsenide, which have similar switching devices and gates. Components according to • ···

- 39 of the present invention may be implemented using a programmed general purpose digital computer using application specific integrated circuits or using a network of interconnected conventional components and circuits. The embodiments described herein are not intended to be exhaustive or to limit the scope of the subject matter. The present invention is limited only by the following claims.

Claims (12)

PATENT CLAIMS 1. A method of detecting a change between an incoming signal and a previous signal, comprising the steps of obtaining an oscillating reference signal, receiving an input signal, and comparing the oscillating reference signal to the input signal to detect a change in the input signal relative to the previous signal. 2. The method of claim 1, wherein the comparing step includes generating a first result and further includes generating a control signal based on the previous signal for controlling passage of the first result as an output signal. 3. The method of claim 2, wherein the step of generating the control signal comprises comparing the oscillating reference signal and the output signal. 4. The method of claim 3, wherein the first result manipulates the output signal from the previous signal to the first result, and the step of generating the control signal comprises comparing the oscillating reference signal and the output signal while the output signal is still logically equal to the previous signal. 5. The method of claim 3, wherein the first result manipulates the output signal from the previous signal to the first result and the step of generating the control signal comprises comparing the oscillating reference signal and the output signal after the output signal is logically equal to the first result. 6. The method according to claim 1, characterized in that the input signal is a simple signal. 7. The method of claim 1, wherein the oscillating reference signal is synchronous with the input signal. 8. The method of claim 1, wherein the oscillating reference signal provides voltage and time attributes. 9. The method of claim 1, characterized in that the oscillating reference signal is negated. 10. The method of claim 1, further comprising the steps of obtaining an oscillating reference complementary signal and comparing the complementary signal against the current input signal and against a previous signal to detect a change in the input signal relative to the previous signal. 11. The method of claim 1, wherein the oscillating reference signal comprises an oscillating source of synchronous voltage and time reference signal having a tracking rate substantially equal to half the cycle time of the oscillating reference signal. ♦ 999 • 9 • 9 9 9 9 9 9 «99 • 9*9 99 99 9«· 99 99 - 42 12. A system for detecting a transition between an input signal and a previous signal, comprising a first input terminal for receiving an oscillating reference signal and a second input terminal for receiving the input signal, an output terminal providing an output signal logically equal to the previous signal, a first comparator connected to the first and second input terminals for comparing the reference and input signals to produce a first result, and a first control unit connected to the first comparator for connecting the first result to the output terminal based on the previous signal. 13. The system of claim 12, wherein the first control unit compares the oscillating reference signal and the output signal. 14. The system of claim 13, wherein the first result is connected to an output terminal for manipulating the output signal from the previous signal to the first result, and the first control unit is connected to compare the oscillating reference signal and the output signal while the output signal is still logically equal to the previous signal. 15. The system of claim 13, wherein the first result is connected to an output terminal for manipulating the output signal from the previous signal to the first result, and the first control unit is connected to compare the oscillating reference and the output signal after the output signal is logically equal to the first result. + ·«· i ί « · · · 9 9 9«·* · · · ···· 99 9« 999 99 99« 16. The system of claim 12, wherein the input signal is a simple signal. 17. The system of claim 12, wherein the oscillating reference signal is synchronous with the input signal. A system according to claim oscillating reference attributes. 12 characterized by the signal providing voltage and timer System according to claim oscillating reference 12 the signal is negated. with the fact that 20. The system of claim 12, wherein the oscillating reference signal comprises an oscillating source of synchronous voltage and timing reference signals having a tracking rate substantially equal to one-half the cycle time of the oscillating reference signal. 21. The system of claim 12, further comprising a third input terminal for receiving the oscillating reference complementary signal, a second comparator coupled to the second and third input terminals for comparing the complementary signal and the input signal to produce a second result, and a second control unit coupled to the second comparator for coupling the second comparator to the output terminal based on the previous signal. *··· · * i · 4 ’· ····«· 4 4 · ···· ·· «4 444 ·· ·4« 22. A system for detecting a transition between an input signal and a previous signal, comprising: an output terminal providing an output signal logically equal to the previous signal; a first amplifier for amplifying a difference between the input signal and an oscillating reference signal to produce a first result; a second amplifier for amplifying a difference between the signal and a complementary signal of the oscillating reference signal to produce a second result; a first switch connected to the first amplifier for connecting the first result to an output terminal based on a first criterion; a second switch connected to the second amplifier for connecting the second result to an output terminal based on a second criterion; a first control unit for controlling the first criterion based on a comparison of the reference signal and the output signal; and a second control unit for controlling the second criterion based on a comparison of the complementary signal and the output signal. 23. The system of claim 22, wherein the first switch connects the first amplifier to the output terminal to manipulate the output signal from the previous signal to the first result, the input signal is logically opposite to the previous signal, the first control unit is connected to compare the reference signal and the output signal while the output signal is still logically equal to the previous signal, and the second control unit is connected to compare the complementary signal and the output signal while the output signal is still logically equal to the previous signal. • ··· 4 4 4 **· · · · ···· 44 4· ··· ·· ··· 24. The system of claim 22, wherein the first switch connects the first amplifier to the output terminal to manipulate the output signal from the previous signal to the first result, the input signal is logically equal to the previous signal, the first control unit is connected to compare the reference signal and the output signal after the output signal is logically equal to the first result, and the second control unit is connected to compare the complementary signal and the output signal after the output signal is logically equal to the first result. 25. The system of claim 22, wherein the input signal is a simple signal. 26. The system of claim 22, wherein the reference signal is synchronous with the input signal. 27. The system of claim 22, wherein the reference signal provides voltage and timing attributes. 28. The system of claim 22, wherein the reference signal is negated. 29. The system of claim 22, wherein the reference signal comprises an oscillating source of synchronous voltage and timing reference signals having a tracking rate substantially equal to one-half the cycle time of the oscillating reference signal. 30. A communication system characterized by comprising * ··♦ φφφφφφ · φ φ · · φφφ φ φ φφφφ φφ ·♦ ·♦· ·· ·· - 46 a transmitter for transmitting an oscillating source of synchronous voltage and time reference signals and a new signal to a receiver, transmission lines connected to the transmitter for transmitting the reference signal and the new signal to the receiver, and a receiver connected to the transmission lines for obtaining a previous signal for receiving the reference signal and the new signal and for detecting a conversion between the new signal and the previous signal relative to the reference signal. 31. The system of claim 30, wherein the transmitter further transmits a complement of the oscillating reference signal to the receiver, the transmission lines transmit the complement to the receiver, and the receiver detects the transformation based on a comparison of the new signal and the previous signal against the complement. 32. The system of claim 30, wherein the receiver comprises: First and second input terminals for receiving, in the same order, an oscillating reference signal and an input signal, an output terminal providing an output signal logically equal to a previous signal, a first comparator connected to the first and second input terminals for comparing the reference signal and the input signal to produce a first result, and a first control unit connected to the first comparator for connecting the first result to an output terminal based on the previous signal. 33. The system of claim 32, wherein the first control unit compares the oscillating reference signal and the output signal. » ·· 9 9 9 9999 ·* • 9 · • 9 999 34. The system of claim 33, wherein the first result is connected to an output terminal to manipulate the output signal from the previous signal to the first result, and the first control unit is connected to compare the oscillating signal and the output signal while the output signal is still logically equal to the previous signal. 35. The system of claim 33, wherein the first result is connected to an output terminal to manipulate the output signal from the previous signal to the first result, and the first control unit is connected to compare the oscillating reference signal and the output signal after the output signal is logically equal to the first result. 36. The system of claim 32, wherein the input signal is a simple signal. 37. The system of claim 32, wherein the oscillating reference signal is synchronous with the input signal. A system according to claim oscillating reference attributes. 32 characterized by the signal providing voltage and timers 39. The system of claim 32, wherein the oscillating reference signal is negated. by the fact that 32 characterized by a signal is included in that the oscillating source System according to claim oscillating reference • · ·· - 48 synchronous voltage and timing reference signals having a tracking speed substantially equal to one half the cycle time of the oscillating reference signal. 41. The system of claim 32, further comprising a third input terminal for receiving an oscillating reference complementary signal, a second comparator coupled to the second and third input terminals for comparing the complementary signal and the input signal to produce a second result, and a second control unit coupled to the second comparator for coupling the second comparator to an output terminal based on the previous signal. 42. The system of claim 30, wherein the transmitter includes a memory controller and the receiver includes a memory. 43. The system of claim 30, wherein the transmitter comprises a microprocessor and the receiver comprises a system control unit. 44. The system of claim 43, wherein the system controller includes a memory controller. 45. A signal receiver system for detecting a transition from a previous signal to a subsequent signal, comprising an output terminal providing an output signal logically equal to the previous signal, the first receiver comprising • · * t 9 9 9 9 9 9 9 9 9 9 9999 99 99 999 99 999 - 49 a first comparator for comparing the oscillating reference signal against a subsequent signal to produce a first result, a first switch connected to the first comparator for connecting the first result to an output terminal and a first control unit connected to the first switch for comparing the oscillating reference signal against the output signal to produce a control signal for controlling the first switch and a second receiver connected in parallel to the first receiver, comprising a second comparator for comparing the oscillating reference complementary signal against a subsequent signal to produce a second result, a second switch connected to the second comparator for connecting the second result to an output terminal and a second control unit connected to the second switch for comparing the oscillating reference complementary signal against the output signal to produce a control signal for controlling the second switch. 46. The signal receiver system of claim 45, wherein the first result is connected to an output terminal for manipulating the output signal from the previous signal to the first result, the first control unit is connected to compare the oscillating reference signal and the output signal while the output signal is still logically equal to the previous signal, and the second control unit is connected to compare the complementary signal and the output signal while the output signal is still logically equal to the previous signal. * 4·4 * · 4 · · 4 4 · · «»·· «· «4 ··· 44 ··· - 50 47. The system of claim 45, wherein the first result is connected to an output terminal to manipulate the output signal from the previous signal to the first result, the first control unit is connected to compare the oscillating reference signal and the output signal after the output signal is logically equal to the first result, and the second control unit is connected to compare the complementary signal and the output signal after the output signal is logically equal to the first result. 48. A transmission system comprising a generator for producing an oscillating synchronous voltage source and a timing reference having a tracking rate of about one-half the cycle period of the oscillating reference signal, and a transmitter coupled to the generator for transmitting the signal and the oscillating reference signal to a receiver. 49. A method of comparing an incoming signal with a previous signal, comprising the steps of obtaining an oscillating reference signal and its complementary signal, receiving an incoming signal, comparing the oscillating reference signal with the incoming signal in a first comparator to produce a first result, comparing the complementary signal with the incoming signal in a second comparator to produce a second result, using a control signal based on the previous signal to control whether the first result or the second result is passed as an output signal. 50. The method of claim 49, characterized in that ♦ 9 - 51 the previous signal has previously passed as an output signal through the first comparator, the input signal is logically the same as the previous signal and the control signal allows the second result to pass as an output signal. 51. The method of claim 49, wherein the previous signal has previously passed as an output signal through the first comparator, the input signal is logically opposite to the previous signal, and the control signal allows the first result to pass as an output signal. 52. A method of transmitting and receiving a group of small amplitude simple signals, characterized in that it includes transmitting a group of small amplitude simple signals from a source to a receiver, transmitting substantially simultaneously from the source to the receiver a pair of complementary, oscillating reference signals having substantially the same tracking rate when the simple signals are being converted, receiving the group of signals and the oscillating reference signals at the receiver, generating an output by comparing the signals of the oscillating reference signals, connecting the output to an output terminal of the receiver when the signal is being converted and disconnecting the output from the output terminal of the receiver when the signal is not being converted. 53. The method of claim 52, wherein the source is connected to the receiver via a transmission line at • ··· • ••«•· · 9 9 9 · 9 9*9 999 9999 «9 99 999 99 99 - 52 bus, which is terminated at both ends with the characteristic impedance of the transmission line. 54. The method of claim 52, wherein the source is connected to the receiver by a connection from one device to another device that is terminated at both ends internally. 55. The method of claim 52, wherein the source comprises a device block and the receiver comprises another block of the same device with p-channel lift-off terminals within the device. 56. The method of claim 52, wherein the signal has a small amplitude of less than 1 V. 57. The method of claim 52, wherein the signal has a small amplitude of less than 40% of the supply voltage. 58. The method of claim 52, wherein the signal has a tracking rate of less than 110% of the signal rate for signals transmitted above 600 MHz. 59. The method of claim 52, wherein the oscillating reference signals have substantially the same amplitude. 60. The method of claim 52, wherein the oscillating reference signals have substantially the same load. 61. A method of transmitting and receiving a group of low-amplitude simple signals, characterized in that it includes the steps of transmitting a group of low-amplitude simple signals from a source to a receiver comprising two comparators and an output terminal, < Ílí - 53 transmitting substantially simultaneously from a source to a receiver a pair of complementary, oscillating, reference signals having substantially the same tracking rate when the simple signals are converted, receiving the group of signals and the oscillating reference signals at the receiver, connecting only one of the comparators to an output terminal based on an instantaneous logic value at the output terminal and an instantaneous value from one of the oscillating, reference signals, and disconnecting the second comparator. 62. The method of claim 61, wherein the step of connecting comprises connecting only one comparator to the output terminal when the single signal changes. 63. The method of claim 61, wherein the step of connecting comprises disconnecting only one comparator and connecting the other comparator when the simple signal does not change. 64. The method of claim 63, wherein the second comparator provides an output signal that restores the instantaneous logic value at the output terminal. 65. The method of claim 61, wherein the comparators compare simple signals with oscillating reference signals to produce output signals, 66. The method of claim 64, wherein only one comparator senses the simplex signals in differential mode with the same noise immunity as the differential signals when the simplex signals change. • ··· • * - 54 ·· ··· ·· ·· 67. The method of claim 64, wherein the second comparator senses the simplex signals in differential mode with the same noise immunity as the differential signals when the simplex signals do not change. 68. The method of claim 52, wherein the source comprises a device block and the receiver comprises another block with p-channel lift terminals within the device. 69. A system comprising: a control bus having a master end and a slave end, a first reference bus having a master end and a slave end, a first reference signal transmitter connected to the master end of the first reference signal bus for transmitting an oscillating reference signal, a data bus having a master end and a slave end, a second reference signal bus having a master end and a slave end, a second reference signal transmitter connected to the master end of the second reference signal bus for transmitting an oscillating reference signal thereto, a third reference signal transmitter connected to the slave end of the second reference signal bus for transmitting an oscillating reference signal thereto, a control device connected to the master end of the control bus for transmitting a control signal to the control bus connected to the master end of the data bus for transmitting a first data signal associated with the control signal to the data bus, and receiving the second data • ··· - 55 signal in response to a control signal from the data bus and connected to the end at the control device of the second reference signal bus for receiving and using the oscillating reference signal from the transmitter of the third reference signal to detect a change in the second data signal and a slave device connected to the end at the slave device of the control bus for receiving the control signal from the control device, connected to the end at the slave device of the first reference signal bus for receiving and using the oscillating reference signal from the transmitter of the first reference signal to detect a change in the control signal, connected to the end at the slave device of the data bus for receiving a first data signal associated with the control signal from the control device and for transmitting a second data signal corresponding to the control signal to the control device and connected to the end at the slave device of the second reference signal bus for receiving and using the oscillating reference signal from the transmitter of the second reference signal to detect a change in the first data signal. 70. The system of claim 69, wherein the control bus has a first load and the data bus has a second load. 71. The system of claim 70, wherein the first load is equal to the second load. 72. The system of claim 70, wherein the first load is different from the second load. 73. The system of claim 69, further comprising a second data bus for transmitting a third data signal associated with the control signal. B ·· * · - 56 74. The system of claim 69, wherein each control bus, first reference signal bus, data bus, and second reference signal bus has a termination resistor internally at the end at the master device and an external termination resistor at the end at the slave device. 75. The system of claim 69, further comprising a second slave device connected to the control bus for receiving a control signal from the control device, connected to the first reference signal bus for receiving an oscillating reference signal from a first reference signal transmitter, connected to the data bus for receiving data signals from the control device and transmitting data signals to the control device, and connected to the second reference signal bus for receiving an oscillating reference signal from a second reference signal transmitter. 76. The system of claim 75, further comprising a clock bus connecting the first slave device to the second slave device and in turn to the master device, and a clock source for generating a clock signal on the clock bus to enable substantially simultaneous reception of signals from the first and second slave devices to the master device. 77. A method comprising: using a control device to transmit a control signal via a control bus to a first slave device, transmitting a first oscillating reference signal for detecting changes in the control signal via the first reference signal bus to the first slave device, • ··· 9 · 9 9 · 9 9 9 9999 «9 ·· ··· »♦ 999 - 57 using a control device to transmit a first data signal associated with a control signal via a first data signal data bus to a first slave device and transmitting a second oscillating reference signal for detecting changes in the first data signal via a second reference signal bus to the first slave device. 78. The method of claim 77, further comprising applying a first load to the control bus and applying a second load to the first data bus. 79. The method of claim 78, wherein the first load is equal to the second load. 80. The method of claim 78, wherein the first load is different from the second load. 81. The method of claim 77, further comprising using the control device to transmit a second data signal associated with the control signal via the second data signal bus to the first slave device. 82. The method of claim 77, further comprising terminating each of the control buses, i.e., the first reference signal bus, the first data signal bus, and the second reference signal bus, with a termination resistor internally at one end and externally at the other end. 83. The method of claim 77, further comprising providing a second slave device between the master device and the first slave device, • ··· ♦ · ♦ » ·*·* »· ·· ··· ·· ·· - 58 providing a clock bus connected from the first slave device to the second slave device and then back to the master device and generating a clock signal on the clock bus to enable substantially simultaneous reception of signals at the master device from the first and second slave devices. 84. A method comprising receiving a control signal via a control bus from a control device, receiving a first oscillating reference signal for detecting changes in the control signal via the first reference signal bus, receiving a first data signal associated with the control signal via the first data signal bus from the control device, and receiving a second oscillating reference signal for detecting changes in the first data signal via the second reference signal bus. 85. A method comprising: using a control device to transmit a control signal via a control bus to a first slave device, transmitting a first oscillating reference signal for detecting changes in the control signal via a first reference signal bus to the first slave device, using the control device to receive a first data signal corresponding to the control signal via a first data signal bus from the first slave device, and using the control device to receive a second oscillating reference signal for detecting changes in the first data signal. - 59 * ··· ··· ·· • · ·· ·· ··· signal via the second reference signal bus from the first slave device. 86. The method of claim 85, further comprising using a first load for the control bus and using a second load for the first data bus. 87. The method of claim 86, wherein the first load is equal to the second load. 88. The method of claim 86, wherein the first load is different from the second load. 89. The method of claim 85, further comprising receiving a second data signal corresponding to the control signal via a second data signal bus from the first slave device. 90. The method of claim 85, further comprising terminating each of the control bus, the first reference signal bus, the first data signal bus, and the second data signal bus with a termination resistor internally at one end and externally at the other end. 91. The method of claim 85, further comprising providing a second slave device between the master device and the first slave device, providing a clock bus connected from the first slave device to the second slave device and then to the master device, and 4 4 4 4 4« 444 «444 44 ·4 444 44 444 - 60 generating a clock signal on the clock bus to enable substantially simultaneous reception of signals from the first and second slave devices to the master device. 92. A method comprising receiving a control signal via a control bus from a control device, receiving a first oscillating reference signal for detecting changes in the control signal via the first reference signal bus, transmitting a data signal corresponding to the control signal via the data bus to the control device, and transmitting a second oscillating reference signal for detecting changes in the data signal via the second reference signal bus to the control device. 93. A system comprising a control bus port, a first reference signal bus port, a first reference signal transmitter connected to the first reference signal bus port for transmitting an oscillating reference signal, a first data signal bus port, a second reference signal bus port, a second reference signal transmitter connected to the second reference signal bus port for transmitting oscillating reference signals, and a control device connected to the control bus port for transmitting control signals to the control bus port, connected to the first data signal bus port for transmitting a first data signal associated with the control signal to the first data signal bus port and for receiving second data signals corresponding to the control signal from the first data signal bus port and connected to the second reference signal bus port for receiving and using input oscillating reference signals from the second reference signal bus port to detect a change in the second data signal. signal. 94. The system of claim 93, wherein the control bus port has a first load and the data bus port has a second load. 95. The system of claim 94, characterized in that with that, that the first load is equal to the square burden. 96. Claim-based system 94 characterized with that, that the first the load is different from second load. 97. The system of claim 93, further comprising a second data signal bus port coupled to the control device, the control device transmitting a third data signal associated with the control signal to the second data signal bus port and receiving a fourth data signal corresponding to the control signal from the second data signal bus port. 98. The system of claim 93, wherein each of the control bus ports, i.e., the first reference signal bus port, the data bus port, and the second reference signal bus port, has an internal termination resistor. 99. The system of claim 92, further comprising a slave device connected to the control bus port for receiving a control signal from a master device connected to the first reference signal bus port for receiving • 999 9 9 9 9 9 9 9 * · •«99 99 99 999 99 999 - 62 of a first oscillating reference signal from a first reference signal transmitter, connected to a first data signal bus port for receiving a first data signal from, and for transmitting a second data signal to, the control device, and connected to a second reference signal bus port for receiving a second oscillating reference signal from the second reference transmitter. 100. The system of claim 99, further comprising a clock bus port for receiving a clock signal via the clock bus port from a slave device. 101. A system comprising: a control bus port, a first reference signal bus port, a data signal bus port, a second reference signal bus port, a first reference signal transmitter coupled to the second reference signal bus port for transmitting an oscillating reference signal to the second reference signal bus port, and a first slave device coupled to the control bus port for receiving a control signal from the control bus port, coupled to the first reference signal bus port for receiving and using an oscillating reference signal from the first reference signal bus port for detecting a change in the control signal, coupled to a data bus port for receiving a first data signal associated with the control signal from the data bus port and for transmitting a second data signal responsive to the control signal to the data bus port, and coupled to the second reference signal bus port for receiving and using the oscillating • BBB · B B B B * B · B * BBBBBB BB ·· • · - 63 B· · B B B B BBB reference signal from the bus port of the second reference signal to detect a conversion in the data signal. 102. The system of claim 101, wherein the control bus port has a first load and the data bus port has a second load. 103. The system of claim 102, wherein the first load is equal to the second load. 104. The system of claim 102, wherein the first load is different from the second load. 105. The system of claim 101, further comprising a second signal bus port connected to the first slave device for receiving a third data signal associated with the control signal and for transmitting a fourth data signal corresponding to the control signal. 106. The system of claim 101, wherein each of the control bus port, the first reference signal bus port, the data bus port, and the second reference signal bus port has an external resistor at the output. 107. The system of claim 101, further comprising a clock bus port and a clock source for generating a clock signal from the clock bus port to the control device. 108. A system comprising: means for transmitting a control signal via a control bus to a first slave device, • · * · φ · · φφ ·* •Φ·· φ· φ * Φφφ means for transmitting a first oscillating reference signal for detecting changes in the control signal via a first reference signal bus to a first slave device, means for transmitting a first data signal associated with the control signal via a first data bus to a first slave device, and means for transmitting a second oscillating reference signal for detecting changes in the first data signal via a second reference signal bus to a first slave device. 109. A system comprising: means for receiving a control signal via a control bus from a control device, means for receiving a first oscillating reference signal for detecting changes in the control signal via the first reference signal bus, means for receiving a first data signal associated with the control signal via the first data bus from the control device, and means for receiving a second oscillating reference signal for detecting changes in the first data signal via the second reference signal bus. 110. A system comprising: means for transmitting a control signal over a control bus to a first slave device, means for transmitting a first oscillating reference signal for detecting changes in the control signal over a first reference signal bus to the first slave device, A *·· I A « - 65^ means for receiving a first data signal responsive to the control signal via a first data bus from the first slave device and means for receiving a second oscillating reference signal for detecting changes in the first data signal via a second reference signal bus from the first slave device. 111. A system comprising: means for receiving a control signal via a control bus from a control device, means for receiving a first oscillating reference signal for detecting changes in the control signal via the first reference signal bus, means for transmitting a data signal responsive to the control signal via the data bus to the control device, and means for transmitting a second oscillating reference signal for detecting changes in the data signal via the second reference signal bus to the control device.