DD211892A1 - DYNAMIC SEMICONDUCTOR MEMORY CELL - Google Patents

Abstract

The invention relates to a dynamic semiconductor memory cell with two transistors, as used in microelectronic memories. The object of the invention is to configure a memory cell having two transistors in such a way that the read transistor remains blocked in the event of a stored "high" on the storage electrode. According to the invention, this is achieved by a capacitive voltage divider between the word line, the storage electrode and the substrate. The bit line is precharged to a medium potential in the memory state.

Description

Dynamic semiconductor memory cell

Field of application of the invention

The invention relates to a semiconductor memory cell with internal voltage gain for dynamic information storage.

The use of the semiconductor memory cell takes place in a matrix-like arrangement in integrated semiconductor memories.

Characteristic of the known technical solutions

Ss are dynamic semiconductor cells with a transistor according to US-PS 3 38 7 286 known. The stored signal is read out without amplification, whereby only a small voltage swing occurs when reading on the read (bit) line. This with increasing surface area of a memory cell increasingly decreasing voltage swing is a further integration in the way.

Furthermore, a dynamic semiconductor memory cell according to DE-OS 24 58 117 is known, which includes a selection and a read transistor, which are connected to four respective clocked lines.

The disadvantage of four clocked lines partially eliminates the solution described in DE-OS 3 046 376 of FIG. 8.

-3DEL 1932 * 052250

In this embodiment, the two transistors of the cell are connected to three clocked lines.

Object of the invention

The object of the invention is to further reduce the number of clocked lines in a two-transistor dynamic semiconductor memory cell.

Explanation of the essence of the invention

The object of the invention is to reduce the potential on the storage electrode and thus the gate of the read transistor to such an extent in a dynamic semiconductor memory cell with two transistors that the read transistor remains blocked when the high level is stored.

Features of the invention

The dynamic semiconductor memory cell with two transistors has a selection transistor which is connected in a known manner with a source-drain region to a bit line and the gate to a word line · A read transistor is connected to the source with the bit line, wherein the second source-drain Area of the selection transistor is coupled to the gate of the read transistor. The gate forms the storage electrode with the adjacent areas.

According to the invention, the gate of the read transistor is connected via a word line capacitor to the word line and via a second capacitor to areas of constant potential, preferably the substrate. Furthermore, the drain of the read transistor is connected to a voltage supply line.

In an embodiment of the invention, the word line capacitor and the second capacitor have the same or almost equal capacitance values. ,

In an embodiment of the invention, the jj ratio of the selection transistor is smaller than the W ratio

of the read transistor, whereby the reading speed increases ·

In an embodiment of the invention, the second source-drain region of the selection transistor is galvanically coupled to the gate of the read transistor. The operation of the memory cell is as follows: In the operating state "write", the word line carries the potential "high", whereby the selection transistor becomes conductive. The bit line carries the potential which is to be stored on the storage electrode and to which binary information is assigned. At high potential on the bit line and the storage electrode leads high potential.

In the "Save" operating state, the word line leads to low potential. As a result, the selection transistor is disabled so that the charge stored on the storage electrode is maintained for a certain time. In this case, a capacitive voltage division takes place via the word line capacitor and the second capacitor, so that the potential of the storage electrode drops somewhat in the memory state. With appropriate dimensioning of the read transistor is disabled in the operating state "Save" regardless of the memory contents of the storage electrode and the connection between the power supply line and the bit line interrupted.

In the "Read" operating state, the bit line is precharged to a medium potential ".

Thereafter, the potential of the word line gradually increases, that is, at a rate of rise of about 0.1 Y / ns. In this case, the potential of the storage electrode is increased in accordance with the voltage division of the word line capacitor and the second capacitor. With a memory content "high", the read transistor opens and the voltage supply line leading to a high positive potential is connected to the bit line. This increases the potential of the bit line from about 2.5 "7 to about 4 7 and can be amplified and forwarded by means of an evaluation circuit not further described here, but if a" low "level is stored then the read opens The storage electrode is charged to the gate charging potential of the bit line and held at this potential.

When the word line has reached the maximum potential z * B of 5 V, the read operation in the cell is finished, and the old information (Eefresh) or new information may be written.

In an embodiment of the invention, the second source-drain region is capacitively coupled to the gate of the read transistor via a further capacitor. The other elements of the memory cell are designed as in the version with galvanic coupling.

The functions of this version with capacitive coupling are the same as the punctures with galvanic coupling. The advantage is that the doping concentration of the second source-drain region of the selection transistor can be made smaller.

As a result, and by eliminating the contact, the Eefresh behavior of the memory cell improves. The semiconductor memory cell was described using n-channel technology «

With a corresponding sign reversal and a change in the doping, the memory cell can of course also be realized in p-channel technology.

The advantage is that only two clocked lines are led to the semiconductor memory cell. It is furthermore advantageous that the threshold voltage of the read transistor is equal to that of the selection transistor.

embodiment

The invention is explained in more detail with reference to two embodiments and two drawings. Show

Pig · 1: the electrical construction of the semiconductor memory cell according to the first embodiment;

Pig * 2: the lay-out of the first embodiment; Pig · 3 ^J cLea Cross section through Pig. 2 along AA;

Pig. FIG. 4 shows the electrical construction of the semiconductor memory line according to the second embodiment; FIG.

Pig. 3 '· the lay-out of the second embodiment; Pig. 6i is the cross section through Pig. 5 1-BB

The one in Pig. 1 comprises a selection transistor 1 and a read transistor 2. A first source-drain region 3 of a selection transistor is provided with a bit line (BL) 4, the data 3 with a word line (WL) 6 and a second source drain. Area 7 connected to the gate 3 of the read transistor 2. Furthermore, the read transistor 2 with source 9 is connected to the bit line 4 and drain 10 to a voltage supply line (U) 11.

The gate 8 of the read transistor 2 forms, with the adjacent regions, the storage electrode 12 which is connected to the word line 6 via a word line capacitor 13 and to the substrate via a second capacitor 14 as a constant potential region.

In Fig. 2, the lay-out of the first embodiment and in Fig. 3 is a cross-section along the line A - A in Fig. 2 is shown. In this case, an n-Eanal technology has been used with two polycrystalline layers and a Leitbahnebene.

The storage electrode 12 and the gate 8 connected thereto consist of a first layer of polycrystalline silicon. The storage electrode 12 is connected via a contact 16 with the second source-drain region 7 of the selection transistor 1.

The word line capacitor 13 is formed by the overlap 15 of word line 6 and storage electrode 12. The second capacitor 14 is formed by the overlap 17 of the storage electrode 12 over substrate regions and via drain 10 of the read transistor 2 and through the PH transition of the contact 16. The overlap 17 is partially under the overlap 15 »The bit line 4 and the power supply line 11 are made of aluminum. The bit line 4 is connected via a contact 18 to the first source-drain region 3 of the selection transistor 1 and to the source of the read transistor 2. The power supply line 11 is connected to a contact 19 connected to the drain of the read transistor. 4, a second embodiment is shown. In contrast to this, the second source-drain region 7 of the read transistor 1 is connected to the storage electrode 12 via a further capacitor 2: 1.

In Fig. 5, the lay-out of the second embodiment and in Fig. 6 is a cross-section along the line B - B in Fig. 5 is shown. In this case, an n-channel technology with two polycrystalline layers and a Leitbahnebene is also used.

The position of the individual elements is the same-as in Fig. 2 and Fig. 3 in the first embodiment. Only the contact 16 is replaced by the capacitor 21 in that the SiC ^ layer extends everywhere between the storage electrode 12 and the substrate. "

In order to obtain a stable coupling, a flat n-doping 20 is introduced under the storage electrode 12, which extends as a second source-drain region 7 of the selection transistor 1 to slightly below the gate 5 ·

Claims (5)

The invention Λ · A dynamic semiconductor memory cell having a selection transistor which leads with a source-drain region to a bit line and with its gate to a word line, and; a read transistor, which is connected to source with the bit line, wherein the second source-drain region of the selection transistor is coupled to the memory electrode belonging to the gate of the read transistor, characterized in that the gate (8) of the read transistor (2) via a Word line capacitor (13) with the word line (6) and via a second capacitor (14) is connected to areas of constant potential and that the drain (10) of the read transistor (2) is connected to a voltage supply line (11). (1) smaller than the! Ratio of the read transistor (2) is. L 2. A semiconductor memory cell according to item 1, characterized in that the word line capacitor (13) and the capacitor (14) "have the same capacitance values. 3 · semiconductor memory cell Item 1, characterized in that the W ratio of the selection transistor Z- 4. A semiconductor memory cell according to item 1 to 3, characterized in that the second source-drain region (7) of the selection transistor (1) is galvanically coupled to the gate (8) of the read transistor (2). 5. Ealbleiterspeicherzelle after. Points Λ to 3, characterized in that the second source-drain region (7) of the selection transistor (1) to the gate (8) of the read transistor (2) is capacitively coupled via a further capacitor (21). Hierzü _ ^ _ Pages Drawings