DD227580A1 - CIRCUIT ARRANGEMENT FOR DETECTING ANALOG INPUT SIGNALS IN ANALOG / DIGITAL IMPLEMENTATION - Google Patents

Abstract

The invention relates to a circuit arrangement for the detection of analog input signals in analog / digital conversion and can be used as a channel occupancy display in digital transmission systems. The aim of the invention is to provide a simple and reliable circuit arrangement for evaluating analog input signals in analog / digital conversion, which manages with little effort in relation to known analog signal processing circuits. It is the object to provide a circuit arrangement on the digital side that detects analog input signals in all possible Betriebszustaenden. According to the invention, this object is achieved in that, on the output side of the analog / digital converter, a higher-order and a lower-order bit are tapped off and fed to a downstream evaluation circuit in the form of a logical link. The logical link is subsequently assigned a monoflop at the output of which the display of the corresponding state of the analog input signal in the form of display elements or an additional utilization circuit can take place. Fig. 1 {circuit arrangement; Recognition; analog input signal; Analog to digital conversion; Channel allocation indication; digital transmission system; Signal processing; Evaluation; evaluation logic; higher order bit; low-order bit}

Description

Field of application of the invention

The invention relates to a circuit arrangement for detecting analog input signals in analog / digital conversion and can be used as a channel occupancy display in digital transmission systems, wherein analog signals of the entire frequency spectrum, which are converted into digitally coded signals, are detected.

Characteristic of the known technical solutions

There are monitoring circuits of pulse trains are known which indicate deviations from the normal operation immediately or stop the current process immediately. Since it is not certain at the beginning of a pulse train at which signal state the failure occurs, monitoring circuits are required which respond to both signal states (low and high). Such circuits operate on the principle of periodic reloading of a capacitor, the state of charge is constantly monitored by an amplitude discriminator. In this case, two independent discriminators are arranged, whose output signals are linked in a NAND gate, wherein one discriminator indicates the failure after a high / low edge and the other discriminator indicates the failure after a low / high edge. From DD-PS 210377 a further circuit arrangement for monitoring digital pulse trains is known. In this solution is based on the principle of a capacitor connected in parallel to a switch, which is controlled by the pulse train to be monitored and a downstream threshold circuit.

A disadvantage of both circuit arrangements is that they are only suitable for monitoring serial pulse trains and do not permit the recognition of data. It is only possible to recognize specific data groups. If these data groups change, then the corresponding circuit arrangement must also be adapted in particular by appropriate capacitor dimensioning.

Furthermore, from DD-PS 151517 a circuit arrangement for level monitoring, in particular for controlling and monitoring certain limits of currents and voltages known. The hysteresis of the set operating point of an operational amplifier and the influence of the different operational amplifier saturation voltages and the operating voltage fluctuations should be avoided. This is an analog monitoring circuit, wherein, depending on an input voltage to be monitored at an operational amplifier, the exceeding of an upper response point is indicated and a lower response point is determined, when it falls below the input voltage, the operational amplifier switches back to the initial state.

The disadvantage is that even this circuit arrangement only allows a purely analog signal detection, that is, the signals are detected in an analogous way. In addition, analog circuits are relatively expensive to ensure the necessary constancy of switching thresholds

 Signal recognition for analog / digital converted signals is not possible.

Object of the invention

It is an object of the invention to provide a simple and reliable circuit arrangement for evaluating analog input signals in analog / digital conversion, which manages with less effort in relation to known analogue signal processing circuits.

Essence of the invention

The invention has for its object to replace the known analog circuit arrangements for evaluating the input signal in analog / digital conversion by a digital circuitry, with existing digitally coded signals.

According to the invention, this object is achieved in that an analog / digital converter on the input side, a stabilizing circuit for accurately stabilizing the DC component of the analog input signal is connected upstream.

-2- 268

On the output side of the analog / digital converter, the evaluation is carried out such that first a low-order bit and a high-order bit are tapped and a downstream evaluation, in the form of a logic operation, supplied. The logic operation is subsequently assigned a monoflop at the output of which the display of the corresponding state of the analog input signal in the form of display elements (eg LED) or an additional utilization circuit can take place.

The least significant bit is selected after the lowest analog signal amplitude to be displayed such that a small amplitude requires a lower order bit. It is based on the center voltage, which is determined by the stabilization of the DC component. When the analog input signal is deflected, the states of the output-side bits of the analog / digital converter change. In each case a higher-order and a lower-order bit result, linked via a logic circuit, the criterion which is used and displayed for evaluation and statement about the state of the analog input signal. The type of logical connection for the evaluation takes place as a function of the previously defined initial state of the most significant bit.

embodiment

The invention will be explained in more detail in the following embodiment. 1 shows a block diagram of the analog / digital converter circuit with an analog / digital converter in successive approximation or cascaded conversion

Fig. 2: Block diagram of the analog / digital converter circuit with an analog / digital converter in parallel conversion Fig. 3a: Example of the evaluation by NAND gate and display Fig. 3 b: Example of the evaluation by means of NOR gate and display

Referring to FIG. 1, in an analog-to-digital converter operating on the successive approximation or cascaded conversion method, the analog input signal first passes to an accurate stabilization circuit of the DC component and then to the analog-to-digital converter ADU via a sample and hold stage. The analog to digital converter ADU and the sample and hold stage are clocked. The stabilization of the DC component can be done via a known voltage divider. On the output side of the analog / digital converter ADU, a low-order bit (LSB) and a high-order bit (MSB) and the DATA READY output of the analog / digital converter ADU are used for evaluation and display according to FIG. 3a or 3b. The DATA READY output continues to run on clock generation. In analog / digital Urrisetzung with an analog / digital converter in parallel conversion of Figure 2 eliminates the sample & hold stage. The analog input signal passes via a stabilization circuit of the DC component to the analog / digital converter ADU. On the output side of the analog / digital converter ADU, a low-order bit (LSB) and a high-order bit (MSB) are routed to an evaluation and display circuit according to FIG. 3a or 3b.

Depending on the previously defined initial state of the most significant bit (MSB), there are three possibilities for the evaluation:

1. If the output state of the most significant bit (MSB) is defined as HIGH, the evaluation takes place via a NAND or AND gate according to FIG. 3a.

2. If the output state of the most significant bit (MSB) is defined as LOW, the evaluation takes place via a NOR or OR gate according to FIG. 3 b.

3. Combinations of the evaluation logic of NAND / AND and NOR / OR gates.

When constructing the evaluation logic by means of the NAND gate according to FIG. 3 a, a higher-order bit (MSB) and a least significant bit (LSB) are respectively applied on the input side. Depending on the mode of operation of the analog / digital converter ADU, the third input of the NAND gate in an analog / digital converter with parallel conversion with the operating voltage (position a) or in an analog / digital converter with successive approximation with the DATA READY Output of the analog / digital converter (position b) occupied. On the output side of the NAND gate, a monoflop is arranged, with a downstream display. When the evaluation logic is constructed by means of the NOR gate according to FIG. 3 b, a higher-order bit (MSB) and a least significant bit (LSB) are respectively input on the input side. Depending on the mode of operation of the analog / digital converter, the third input of the NOR gate is omitted or it is inverted in an analog / digital converter with parallel conversion with the operating voltage (position a) or in an analog / digital converter with successive approximation is assigned to the DATA READY output of the analog / digital converter (position b). On the output side of the NOR gate, a monoflop is arranged with a downstream display. If the highest-order bit (MSB) is not used when using higher-order bits, a negation must be made between the sampling and the logic operation in the examples shown. It is also possible to use a combination of NAND / AND and NOR / OR gates as evaluation logic. Identically transformed links can still be used. On the other hand, logical links such as inhibition, implication, etc. can also be used.

Claims (5)

-1-268,028 Invention claims: 1. Circuit arrangement for detecting analog input signals in analog / digital conversion consisting of an analog / digital converter with upstream sample & hold stage and associated clock generation, characterized in that the analog input signal is connected to a stabilizing circuit of the DC component, hereinafter referred to the sample and hold stage is routed to the analog-to-digital converter (ADC) and that the output side of the analog-to-digital converter (ADC) is a high-order bit and a low-order bit connected to an evaluation logic and downstream display or utilization circuit. 2. A circuit arrangement for detecting analog input signals in Analog / Digitai implementation according to item 1, characterized in that the low-order bit and the higher-order bit is each guided to an input of a NAND, NOR, AND or OR gate, the third Input is connected either to the DATA READY output of the ADC or the operating voltage and that the output of the NAND or NOR gate is connected to an evaluation circuit and downstream display or utilization circuit. 3. Circuit arrangement for detecting analog input signals in analog / digital conversion with an analog / digital converter without sample & hold stage, characterized in that the analog input signal is connected to a stabilization circuit of the DC component, which is subsequently to the analog / digital Converter (ADC) is guided and that the output side of the analog / digital converter (ADC) is a high-order bit and a low-order bit connected to a Auswertelogik and downstream display or utilization circuit. 4. Circuit arrangement for detecting analog input signals during analog / digital conversion according to point 3, , characterized in that the low-order bit and the higher-order bit are each routed to an input of a NAND, AND, NOR or OR gate and that the output of the NAND, AND, NOR or OR gate with an evaluation circuit and downstream display or utilization circuit is connected. 5. Circuit arrangement for detecting analog input signals in analog / digital conversion according to item 1 or 3, characterized in that the NAND, AND, NOR and / or OR gates logically linked together and an evaluation circuit with a subsequent display or Recycling circuit are connected. For this 2 pages drawings