DE19782017T1 - Zugreifen auf eine Seite des Systemspeichers - Google Patents

Zugreifen auf eine Seite des Systemspeichers

Info

Publication number
DE19782017T1
DE19782017T1 DE19782017T DE19782017T DE19782017T1 DE 19782017 T1 DE19782017 T1 DE 19782017T1 DE 19782017 T DE19782017 T DE 19782017T DE 19782017 T DE19782017 T DE 19782017T DE 19782017 T1 DE19782017 T1 DE 19782017T1
Authority
DE
Germany
Prior art keywords
page
access
system memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19782017T
Other languages
English (en)
Other versions
DE19782017B4 (de
Inventor
Michael N Derr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19782017T1 publication Critical patent/DE19782017T1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
DE19782017T 1996-09-30 1997-07-23 Zugreifen auf eine Seite des Systemspeichers Pending DE19782017T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/724,171 US5893917A (en) 1996-09-30 1996-09-30 Memory controller and method of closing a page of system memory
PCT/US1997/012994 WO1998014875A1 (en) 1996-09-30 1997-07-23 Accessing a page of system memory

Publications (1)

Publication Number Publication Date
DE19782017T1 true DE19782017T1 (de) 1999-08-12

Family

ID=24909327

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19782017A Expired - Fee Related DE19782017B4 (de) 1996-09-30 1997-07-23 Verfahren und Computersystem zur Durchführung einer Burst-Leseoperation eines Bus-Masters aus einem Systemspeicher
DE19782017T Pending DE19782017T1 (de) 1996-09-30 1997-07-23 Zugreifen auf eine Seite des Systemspeichers

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE19782017A Expired - Fee Related DE19782017B4 (de) 1996-09-30 1997-07-23 Verfahren und Computersystem zur Durchführung einer Burst-Leseoperation eines Bus-Masters aus einem Systemspeicher

Country Status (6)

Country Link
US (1) US5893917A (de)
AU (1) AU3812297A (de)
DE (2) DE19782017B4 (de)
GB (1) GB2333170B (de)
TW (1) TW360828B (de)
WO (1) WO1998014875A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10319158A1 (de) * 2003-04-29 2004-11-25 Infineon Technologies Ag Vorrichtung zum flexiblen Deaktivieren von Wortleitungen von dynamischen Speicherbausteinen und Verfahren hierfür

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6341335B1 (en) * 1997-10-29 2002-01-22 Hitachi, Ltd. Information processing system for read ahead buffer memory equipped with register and memory controller
US6199145B1 (en) * 1998-02-27 2001-03-06 Intel Corporation Configurable page closing method and apparatus for multi-port host bridges
US6219764B1 (en) * 1998-08-03 2001-04-17 Micron Technology, Inc. Memory paging control method
US6219765B1 (en) 1998-08-03 2001-04-17 Micron Technology, Inc. Memory paging control apparatus
US20020056027A1 (en) * 1998-10-29 2002-05-09 Hiroki Kanai Information processing system
US6374323B1 (en) * 1998-11-16 2002-04-16 Infineon Technologies Ag Computer memory conflict avoidance using page registers
JP2000330965A (ja) * 1999-03-17 2000-11-30 Hitachi Ltd マルチプロセッサシステム及びそのメモリアクセストランザクションの転送方法
US6859413B2 (en) * 2002-09-27 2005-02-22 International Business Machines Corporation Method and apparatus for DLL lock latency detection
US6981088B2 (en) * 2003-03-26 2005-12-27 Lsi Logic Corporation System and method of transferring data words between master and slave devices
US7538762B2 (en) 2003-09-30 2009-05-26 Intel Corporation Switching display update properties upon detecting a power management event

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69129252T2 (de) * 1990-08-06 1998-12-17 Ncr International, Inc., Dayton, Ohio Verfahren zum Betrieb eines Rechnerspeichers und Anordnung
IT1241318B (it) * 1990-11-19 1994-01-10 Olivetti & Co Spa Dispositivo di indirizzamento di memoria
US5664153A (en) * 1993-04-21 1997-09-02 Intel Corporation Page open/close scheme based on high order address bit and likelihood of page access
EP0692764B1 (de) * 1994-06-17 2000-08-09 Advanced Micro Devices, Inc. Speicherübertragungsgeschwindigkeitsbegrenzung für PCI-Meister

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10319158A1 (de) * 2003-04-29 2004-11-25 Infineon Technologies Ag Vorrichtung zum flexiblen Deaktivieren von Wortleitungen von dynamischen Speicherbausteinen und Verfahren hierfür
US6973008B2 (en) 2003-04-29 2005-12-06 Infineon Technologies Ag Apparatus for flexible deactivation of word lines of dynamic memory modules and method therefor

Also Published As

Publication number Publication date
DE19782017B4 (de) 2009-08-27
GB2333170A (en) 1999-07-14
US5893917A (en) 1999-04-13
AU3812297A (en) 1998-04-24
TW360828B (en) 1999-06-11
GB2333170B (en) 2001-02-07
GB9906745D0 (en) 1999-05-19
HK1021421A1 (en) 2000-06-09
WO1998014875A1 (en) 1998-04-09

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