DE202017007724U1 - Display device having conductive patterns with reduced display element overlap - Google Patents

Abstract

Display device, characterized by:
a substrate (SUB) including a pixel area (PXA) and a peripheral area (PPA);
a plurality of pixels (PXL) arranged in the pixel area (PXA) of the substrate (SUB), each of the plurality of pixels (PXL) including a light-emitting element;
Data lines and scan lines electrically connected to each of the plurality of pixels (PXL); and
a power line arrangement (PL) configured to supply power to the plurality of pixels (PXL), the power line arrangement being characterized by a second conductive layer (PL2),
wherein the second conductive layer (PL2) of the power line arrangement is characterized by:
a plurality of first conductive lines (CL1); and
a plurality of second conductive lines (CL2) intersecting the plurality of first conductive lines (CL1), wherein the plurality of second conductive lines (CL2) are each arranged in a region between adjacent light-emitting elements of the plurality of pixels (PXL) without overlapping anodes of the light-emitting elements, and
wherein at least some portions of the plurality of second conductive lines extend in a direction oblique to an extending direction of the data lines or the scanning lines;
wherein the first conductive lines (CL1) and the second conductive lines (CL2) are electrically connected to each other,
wherein the second conductive layer (PL2) has a network pattern and
characterized in that
the plurality of first conductive lines (CL1) extend in a direction parallel to the extension direction of the data lines; or
the plurality of first conductive lines (CL1) and the plurality of second conductive lines (CL2) extend in a direction oblique to an extension direction of the data lines or an extension direction of the scanning lines.

Description

An embodiment of the present invention relates to a display device and, more particularly, to a display device having conductive patterns with reduced display element overlap.

A display device includes a plurality of pixels, each including a display element. Each of the pixels includes wiring lines and at least one transistor connected to the wiring lines to operate the display device.

The transistor is electrically connected to the display element and the transistor can drive the display element using signals supplied from the wiring lines.

At least some of these wiring lines may overlap the display elements responsible for displaying an image. Although the wiring lines may be located behind the display element, wiring lines located behind the display element may form a step difference below the display element. The step difference causes surface non-uniformity of the display element. The surface non-uniformity of the display element may create a white angle dependency (WAD) according to a viewing angle of the display device.

A display device includes a substrate including a pixel region and a peripheral region. A plurality of pixels are arranged in the pixel region of the substrate. Each of the plurality of pixels includes a light-emitting element. Data lines and scan lines are connected to each of the plurality of pixels. A power line is configured to supply power to the plurality of pixels. The power line includes a plurality of first conductive lines and a plurality of second conductive lines intersecting the plurality of first conductive lines. The plurality of second conductive lines are arranged in a region between adjacent light-emitting elements of the plurality of pixels. At least some of the plurality of second conductive lines extend in a direction oblique to an extending direction of the data lines or the scan lines.

A display device includes a substrate having a pixel region and a peripheral region. A plurality of pixels are arranged in the pixel region of the substrate, and each of the plurality of pixels includes at least one transistor and a light-emitting element connected to the transistor. Data lines and scan lines are connected to the plurality of pixels. A power line is configured to supply power to the plurality of pixels. The transistor includes an active pattern arranged on the substrate, and a source electrode and a drain electrode connected to the active pattern. The gate electrode is arranged on the active pattern with a gate insulating layer positioned therebetween. An interlayer insulating layer covers the gate electrode and includes a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer laminated sequentially. The power line includes a first conductive layer extending parallel to the data lines and disposed on the second interlayer insulating layer, and a second conductive layer disposed on the third interlayer insulating layer and connected to the first conductive layer through a contact hole passing through the third interlayer insulating layer. The second conductive layer includes first conductive lines extending in a first direction and second conductive lines intersecting the first conductive lines, which are disposed in a region between adjacent light-emitting elements of the plurality of pixels. At least a portion of the light-emitting elements of the plurality of pixels extends in a direction oblique to an extending direction of the data lines or the scanning lines.

A display device includes a substrate having a pixel region and a peripheral region. A plurality of pixels are arranged in the pixel region of the substrate, and each of the plurality of pixels includes a light-emitting element. Data lines and scan lines are connected to the plurality of pixels. A first power line is electrically connected to a first electrode of the light-emitting element of the plurality of pixels. A second power line is connected to a second electrode of the light-emitting element of the plurality of pixels. The first power line includes first conductive lines extending in one direction and second conductive lines crossing the first conductive lines and arranged in a region between adjacent light-emitting elements of the plurality of pixels. At least one of the plurality of second conductive lines extends in a direction oblique to an extending direction of the data lines or the scan lines.

According to one aspect of the invention, there is provided a display device comprising: a substrate having a pixel region and a peri peripheral region; a plurality of pixels arranged in the pixel region of the substrate, each of the plurality of pixels including a light-emitting element; data lines and scan lines connected to each of the plurality of pixels; and a power line configured to supply power to the plurality of pixels, the power line comprising: a plurality of first conductive lines; and a plurality of second conductive lines intersecting the plurality of first conductive lines, the plurality of second conductive lines being arranged in a region between adjacent light-emitting elements of the plurality of pixels, at least some of the plurality of second conductive lines extending in a direction oblique to an extending direction of the data lines or the scan lines.

In some embodiments, each of the plurality of first conductive lines extends in a direction parallel to the extending direction of the data lines or the scan lines.

In some embodiments, the plurality of second conductive lines comprises a plurality of units of conductive patterns connected to each other.

In some embodiments, the plurality of units of conductive patterns includes: a first conductive pattern intersecting one of the plurality of first conductive lines; a second conductive pattern extending in a direction oblique to an extending direction of the plurality of first conductive lines and having one end connected to one end of the first conductive pattern; a third conductive pattern having one end connected to the other end of the second conductive pattern; and a fourth conductive pattern having one end connected to the other end of the third conductive pattern and the other end connected to the other end of a first conductive pattern of an adjacent unit of conductive patterns.

In some embodiments, the third conductive pattern extends parallel to the first conductive pattern.

In some embodiments, the fourth conductive pattern extends in a direction that intersects the plurality of first conductive lines, the first conductive pattern, the second conductive pattern, and the third conductive pattern.

In some embodiments, the plurality of first conductive lines and the plurality of second conductive lines extend in a direction oblique to an extending direction of the data lines or an extending direction of the scan lines.

In some embodiments, the plurality of first conductive lines and the plurality of second conductive lines are arranged in a region between the adjacent light-emitting elements of the plurality of pixels, and wherein the light-emitting elements of the plurality of pixels are arranged in a region formed by the plurality of first conductive lines and the plurality of second conductive lines.

In some embodiments, at least two light-emitting elements of the plurality of pixels are arranged in a region formed by the plurality of first conductive lines and the plurality of second conductive lines.

In some embodiments, edges of at least some of the light-emitting elements of the plurality of pixels overlap the plurality of first conductive lines or the plurality of second conductive lines.

In some embodiments, each of the plurality of pixels includes at least one transistor, and the transistor includes: an active pattern disposed on the substrate; a source electrode and a drain electrode connected to the active pattern; a gate electrode disposed on the active pattern with a gate insulating layer positioned therebetween; and an interlayer insulating layer covering the gate electrode and including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer laminated sequentially.

In some embodiments, each of the plurality of pixels further comprises a storage capacitor, and the storage capacitor comprises a lower electrode disposed in a same layer as the gate electrode and an upper electrode disposed on the first interlayer insulating layer.

In some embodiments, the display device further comprises a conductive layer extending parallel to the data line and disposed on the second intermediate insulating layer,
wherein the current line is arranged on the third interlayer insulating layer and is connected to the conductive layer through a contact hole passing through the third interlayer insulating layer.

In some embodiments, the light-emitting elements of the plurality of pixels each comprise a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode, and wherein the power line is electrically connected to the first electrode and supplies a voltage to the first electrode that is higher than a voltage supplied to the second electrode.

According to one aspect of the invention, there is provided a display device comprising: a substrate including a pixel region and a peripheral region; a plurality of pixels arranged in the pixel region of the substrate, each of the plurality of pixels including at least one transistor and a light-emitting element connected to the transistor; data lines and scan lines connected to the plurality of pixels; and a power line configured to supply power to the plurality of pixels, the transistor comprising: an active pattern arranged on the substrate; a source electrode and a drain electrode connected to the active pattern, with a gate insulating layer positioned therebetween; and an interlayer covering the gate electrode and including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer laminated one after the other, the power line comprising: a first conductive layer extending parallel to the data lines and arranged on the second interlayer insulating layer; and a second conductive layer disposed on the third interlayer insulating layer and connected to the first conductive layer through a contact hole passing through the third interlayer insulating layer, and wherein the second conductive layer comprises: first conductive lines extending in a first direction; and second conductive lines intersecting the first conductive lines arranged in a region between adjacent light-emitting elements of the plurality of pixels, wherein at least some of the light-emitting elements of the plurality of pixels extend in a direction oblique to an extending direction of the data lines or the scanning lines.

In some embodiments, each of the plurality of pixels further comprises a storage capacitor, and wherein the storage capacitor comprises a lower electrode disposed in a same layer as the gate electrode and an upper electrode disposed on the first interlayer insulating layer.

In some embodiments, the first conductive lines extend in a direction parallel to an extension direction of the data lines or the scan lines.

In some embodiments, the second conductive lines comprise a plurality of units of conductive patterns connected to each other, each of the plurality of units of conductive patterns comprising: a first conductive pattern intersecting one of the first conductive lines; a second conductive pattern extending in a direction oblique to an extending direction of the first conductive line and having one end thereof connected to one end of the first conductive pattern; a third conductive pattern having one end thereof connected to the other end of the second conductive pattern; and a fourth conductive pattern having one end connected to the other end of the third conductive pattern and the other end thereof connected to the other end of a first conductive pattern of an adjacent unit of conductive patterns of the plurality of units of conductive patterns.

In some embodiments, the third conductive pattern extends parallel to the first conductive pattern, and the fourth conductive pattern extends in a direction that intersects the first conductive line, the first conductive pattern, the second conductive pattern, and the third conductive pattern.

In some embodiments, the first conductive lines and the second conductive lines extend in a direction oblique to an extending direction of the data lines or the scan lines.

In some embodiments, the first conductive lines and the second conductive lines are arranged in a region between the adjacent light-emitting elements, and wherein the light-emitting elements are arranged in a region formed by the first conductive lines and the second conductive lines.

In some embodiments, at least two light-emitting elements of the plurality of pixels are arranged in a region formed by the first conductive lines and the second conductive lines.

In some embodiments, edges of at least a portion of the light-emitting elements of the plurality of pixels overlap the plurality of first conductive lines or the plurality of second conductive lines.

According to one aspect of the invention, there is provided a display device comprising: a substrate including a pixel region and a peripheral region; a plurality of pixels arranged in the pixel region of the substrate, each of the plurality of pixels including a light-emitting element; data lines and scanning lines connected to the plurality of pixels; a first power line electrically connected to a first electrode of the light-emitting element of the plurality of pixels; and a second power line connected to a second electrode of the light-emitting element of the plurality of pixels, the first power line comprising: first conductive lines extending in one direction; and second conductive lines crossing the first conductive lines and arranged in a region between adjacent light-emitting elements of the plurality of pixels, wherein at least one of the second conductive lines extends in a direction oblique to an extending direction of the data lines or the scanning lines.

In some embodiments, the first conductive lines extend parallel to the extending direction of the data lines or the scanning lines, and the second conductive lines comprise a plurality of units of conductive patterns connected to each other, and the plurality of units of conductive patterns comprise: a first conductive pattern intersecting one of the first conductive lines; a second conductive pattern extending in a direction oblique to an extending direction of the first conductive line and having one end thereof connected to one end of the first conductive pattern; a third conductive pattern having one end thereof connected to the other end of the second conductive pattern; and a fourth conductive pattern having one end connected to the other end of the third conductive pattern and the other end thereof connected to the other end of a first conductive pattern of an adjacent unit of conductive patterns.

In some embodiments, the third conductive pattern extends parallel to the first conductive pattern, and wherein the fourth conductive pattern extends in a direction that intersects an extending direction of the first conductive line, the first conductive pattern, the second conductive pattern, and the third conductive pattern.

In some embodiments, the first conductive lines and the second conductive lines extend in a direction oblique to an extending direction of the data lines or the scan lines.

In some embodiments, the first conductive lines and the second conductive lines are arranged in a region between the adjacent light-emitting elements and extend in a direction oblique to an extending direction of the data lines or the scanning lines.

In some embodiments, at least two light-emitting elements are arranged in a region formed by the first conductive lines and the second conductive lines.

In some embodiments, edges of at least a portion of the light-emitting elements of the plurality of pixels overlap the plurality of first conductive lines or the plurality of second conductive lines.

In some embodiments, each of the plurality of pixels includes at least one transistor, and the transistor includes: an active pattern disposed on the substrate; a source electrode and a drain electrode connected to the active pattern; a gate electrode disposed on the active pattern with a gate insulating layer positioned therebetween; and an interlayer insulating layer covering the gate electrode and including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer laminated sequentially.

In some embodiments, the display device further comprises a conductive layer extending parallel to the data line and disposed on the second interlayer insulating layer, wherein the power line is disposed on the third interlayer insulating layer and is connected to the conductive layer by a contact hole passing through the third interlayer insulating layer.

In some embodiments, the first power line supplies a first current, the second power line supplies a second current, and a voltage of the first current is greater than a voltage of the second current.

According to one aspect of the invention, there is provided a display device as set out in claim 1. Preferred features are set out in claims 2 to 6.

According to one aspect of the invention, there is provided a display device as set out in claim 7. Preferred features are set out in claims 8 to 11.

According to one aspect of the invention, there is provided a display device as set out in claim 12. Preferred features are set out in claims 13 to 16.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. However, the embodiments may be embodied in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of applicability of the embodiments to those skilled in the art.

• 1 ist eine Draufsicht, die eine Darstellungsvorrichtung gemäß einem Ausführungsbeispiel der vorliegenden Erfindung veranschaulicht;
• 2 ist ein Blockdiagramm, das Pixel und einen Treiber gemäß einem Ausführungsbeispiel der vorliegenden Erfindung veranschaulicht;
• 3 ist ein äquivalentes Schaltkreisdiagramm, das eine Ausführungsform des Pixels von 2 veranschaulicht;
• 4 ist eine Draufsicht, die speziell das Pixel aus 3 veranschaulicht;
• 5 ist eine Querschnittsansicht entlang der Leitung I-I' von 4;
• 6 ist eine Querschnittsansicht entlang der Leitung II-II' von 4;
• 7 ist eine Draufsicht auf die Wirkmuster von 2 bis 6;
• 8 ist eine Draufsicht, die die Abtastleitungen, die Emissionssteuerleitungen und die untere Elektrode des Speicherkondensators von 2 bis 6 veranschaulicht;
• 9 ist eine Draufsicht, die die Initialisierungsstromleitung und die obere Elektrode des Speicherkondensators von 2 bis 6 veranschaulicht;
• 10 ist eine Draufsicht, die die Datenleitungen, die Verbindungsleitung, die Hilfsverbindungsleitung und die erste leitfähige Schicht und das erste Brückenmuster der Stromleitung von 2 bis 6 veranschaulicht;
• 11 ist eine Draufsicht, die die zweite leitfähige Schicht und das zweite Brückenmuster der Stromleitung von. 2 bis 6 veranschaulicht; und
• 12 ist eine Draufsicht, die die organische lichtemittierende Diode (organic light emitting diode - OLED) von 2 bis 6 veranschaulicht;
• 13 ist eine Draufsicht, die die zweite leitfähige Schicht und das zweite Brückenmuster der Stromleitung und der OLED von 11 und 12 veranschaulicht;
• 14 ist eine Draufsicht, die eine zweite Stromleitung, ein zweites Brückenmuster und eine OLED einer Darstellungsvorrichtung gemäß einem Ausführungsbeispiel der vorliegenden Erfindung veranschaulicht;
• 15 ist eine Draufsicht, die eine zweite Stromleitung, ein zweites Brückenmuster und eine OLED einer Darstellungsvorrichtung gemäß einem Ausführungsbeispiel der vorliegenden Erfindung veranschaulicht; und
• 16 ist eine Draufsicht, die eine zweite Stromleitung, ein zweites Brückenmuster und eine OLED einer Darstellungsvorrichtung gemäß einem Ausführungsbeispiel der vorliegenden Erfindung veranschaulicht.

In the drawing figures, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or there may be one or more intermediate elements. Like reference numerals refer to like elements throughout the application and the figures.

• 1 is a plan view illustrating a display device according to an embodiment of the present invention;
• 2 is a block diagram illustrating pixels and a driver according to an embodiment of the present invention;
• 3 is an equivalent circuit diagram showing an embodiment of the pixel of 2 illustrated;
• 4 is a top view that specifically shows the pixel from 3 illustrated;
• 5 is a cross-sectional view along line II' of 4 ;
• 6 is a cross-sectional view along line II-II' of 4 ;
• 7 is a top view of the patterns of action of 2 to 6 ;
• 8 is a plan view showing the scanning lines, the emission control lines and the lower electrode of the storage capacitor of 2 to 6 illustrated;
• 9 is a plan view showing the initialization current line and the upper electrode of the storage capacitor of 2 to 6 illustrated;
• 10 is a plan view showing the data lines, the connection line, the auxiliary connection line and the first conductive layer and the first bridge pattern of the power line of 2 to 6 illustrated;
• 11 is a plan view showing the second conductive layer and the second bridge pattern of the power line of. 2 to 6 illustrated; and
• 12 is a top view showing the organic light emitting diode (OLED) of 2 to 6 illustrated;
• 13 is a plan view showing the second conductive layer and the second bridge pattern of the power line and the OLED of 11 and 12 illustrated;
• 14 is a plan view illustrating a second power line, a second bridge pattern, and an OLED of a display device according to an embodiment of the present invention;
• 15 is a plan view illustrating a second power line, a second bridge pattern, and an OLED of a display device according to an embodiment of the present invention; and
• 16 is a plan view illustrating a second power line, a second bridge pattern, and an OLED of a display device according to an embodiment of the present invention.

The present invention is susceptible of various modifications and various embodiments, specific examples of which are illustrated in the drawings and described in detail. It should be understood, however, that the present invention is not limited to any particular form disclosed, but includes all modifications, equivalents, and substitutions without departing from the scope and spirit of the disclosure.

In descriptive drawings, like numerals refer to like elements. To clarify the present invention, the dimensions of structures may be exaggerated in the accompanying drawings. While terms such as "first" and "second," etc., may be used to describe various components, such components should not be construed as limited to the above terms. The above terms are used to distinguish one component from another.

It is understood that when an element, such as a layer, film, region, or substrate, is referred to as being “on” another element, it is directly on the another element or there may be elements in between.

Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

1 is a plan view illustrating a display device according to an embodiment of the present invention.

Referring to 1 the display device may include a substrate (substrate - SUB), pixels PXL arranged on the substrate SUB, a driver arranged on the substrate SUB for driving the pixels PXL, and a wiring line unit for connecting the pixels PXL and the driver.

The substrate SUB may include a pixel region (PXA) and a peripheral region (PPA). The pixels PXL displaying an image are provided in the pixel region PXA. The pixels PXL will be described later. The pixels PXL are not arranged in the peripheral region PPA. Therefore, the image is not displayed on the peripheral region PPA. The driver for driving the pixels PXL and a part of a wiring line for connecting the pixels PXL and the driver may be arranged in the peripheral region PPA. The peripheral region PPA may correspond to a bezel in the final display device. A width of the bezel may be determined according to a width of the peripheral region PPA.

The pixel area PXA can have various shapes. For example, the pixel area PXA can be a closed polygon, such as a square or rectangle, a circle or ellipse, a semicircle or a semi-ellipse. The pixel area PXA can have any closed shape that has straight and/or curved sides. If the pixel area PXA includes a plurality of areas, each of the areas can also be a closed polygon, such as a square or rectangle, a circle or ellipse, a semicircle or a semi-ellipse, or another closed shape that includes straight and/or curved sides. In addition, areas of the plurality of areas can be the same or different from one another.

According to this approach, the pixel area PXA is illustrated as a square area containing even sides.

The peripheral region PPA may be arranged on at least one side of the pixel region PXA. According to one embodiment of the present invention, the peripheral region PPA may surround the pixel region PXA. According to one embodiment of the present invention, the peripheral region PPA may include horizontal units extending in a width direction and vertical units extending in a length direction. Two vertical units separated from each other in the width direction may be arranged in the peripheral region PPA.

The pixels PXL may be arranged in the pixel region PXA formed on the substrate SUB. Each of the plurality of pixels PXL may be a minimal unit representing an image. The pixels PXL may include organic light-emitting diodes (OLEDs) that emit white light components and/or color light components. Each of the pixels PXL may emit red light, green light, or blue light. However, the present invention is not limited thereto. For example, the pixel PXL may emit cyan light, magenta light, yellow light, or white light.

The plurality of pixels PXL may be arranged in a matrix having rows extending in a first direction (first direction - DR1) and columns extending in a second direction (second direction - DR2) that crosses the first direction. However, the arrangement of the pixels PXL is not limited to this. The pixels PXL may be arranged in various shapes. For example, some of the pixels PXL may be arranged such that the first direction DR1 is a row direction. However, other pixels PXL may be arranged such that a direction other than the first direction DR1, for example, the row direction, may be a direction oblique to the first direction DR1, and the column direction may be a direction that intersects the row direction. Here, the column direction may be oblique to both the first direction DR1 and the second direction DR2.

The driver provides signals to the PXL pixels through the wiring line unit to operate the PXL pixels. 1 For clarity, the wiring line unit is not shown. The wiring line unit will be described later.

The driver may include a scan driver (SDV) for providing scan signals to the PXL pixels through scan lines, an emission driver (EDV) for providing emission control signals to the PXL pixels through emission control lines, a data driver (DDV) for providing data signals to the PXL pixels through data lines, and include a timing controller (TC). The timing controller can control the scan driver SDV, the emission driver EDV, and the data driver DDV.

The scanning driver SDV may be arranged in the vertical unit of the peripheral region PPA. Since the vertical units of the peripheral region PPA form a pair separated from each other in the width direction of the pixel region PXA, the scanning driver SDV may be arranged in at least one of the vertical units of the peripheral region PPA. The scanning driver SDV may extend in the longitudinal direction of the peripheral region PPA.

According to an embodiment of the present invention, the scan driver SDV may be directly mounted on the substrate SUB. When the scan driver SDV is directly mounted on the substrate SUB, the scan driver SDV may be formed in a process of forming the pixels PXL. However, a position of the scan driver SDV and a method of forming the scan driver SDV are not limited thereto. The scan driver SDV may be formed in a separate chip and arranged on the substrate SUB in a chip-on-glass (COG) process. Additionally, the scan driver SDV may be mounted on a printed circuit board (PCB) to be connected to the substrate SUB through a connector.

The emission driver EDV, like the scanning driver SDV, can also be arranged in the vertical unit of the peripheral area PPA. The emission driver EDV can be arranged on at least one side of the vertical unit of the peripheral area PPA. The emission driver EDV can extend in the longitudinal direction of the peripheral area PPA.

According to an embodiment of the present invention, the emission driver EDV may be directly mounted on the substrate SUB. When the emission driver EDV is directly mounted on the substrate SUB, the emission driver EDV may be formed during a process of forming the pixels PXL. However, a position of the emission driver EDV and a method of forming the emission driver EDV are not limited thereto. The emission driver EDV may be formed in a separate chip and arranged on the substrate SUB in the COG process. In addition, the emission driver EDV may be mounted on the PCB to be connected to the substrate SUB through the connecting member.

According to one embodiment of the present invention, the scanning driver SDV and the emission driver EDV are illustrated as being adjacent to each other and formed on one side of the pair of vertical units of the peripheral area PPA. However, the present invention is not limited thereto. The scanning driver SDV and the emission driver EDV may be arranged according to various configurations. For example, the scanning driver SDV may be arranged on one side of the vertical units of the peripheral area PPA, and the emission driver EDV may be arranged on the other side of the vertical units of the peripheral area PPA. Alternatively, the scanning driver SDV may be arranged on both of the vertical units of the peripheral area PPA, and the emission driver EDV may be arranged on only one side of the vertical units of the peripheral area PPA.

The data driver DDV may be arranged in the peripheral area PPA. For example, the data driver DDV may be arranged in the horizontal unit of the peripheral area PPA. The data driver DDV may extend in the width direction of the peripheral area PPA.

According to an embodiment of the present invention, positions/a position of the scanning driver SDV, the emission driver EDV and/or the data driver DDV can be changed arbitrarily.

The timing controller can be connected to the scanning driver SDV, the emission driver EDV, and the data driver DDV through wiring lines by various methods. A position of the timing controller is not limited to the configuration shown. For example, the timing controller is mounted on the PCB and can be connected to the scanning driver SDV, the emission driver EDV, and the data driver DDV through the PCB. The PCB can be arranged in various positions, for example, on a side of the substrate SUB or on a back surface of the substrate SUB.

2 is a block diagram illustrating pixels and a driver according to an embodiment of the present invention.

Referring to 2 the display device may include the pixels PXL, the driver and the wiring line unit.

The plurality of pixels PXL may be arranged. The driver may include the scanning driver SDV, the exhaust driver EDV, the data driver DDV, and the timing controller TC. 2 The positions of the scanning driver SDV, the emission driver EDV, the data driver DDV and the timing control TC are set as examples. The device according to embodiments of the present invention may alternatively be implemented in other ways. For example, the scanning driver SDV, the emission driver EDV, the data driver DDV, and the timing controller TC may be arranged at other positions in the display device.

The wiring line unit provides signals from the driver to the pixels PXL and may include scan lines, data lines, emission control lines, a power line (PL), and a first initializing power line (Vint1). The scan lines include a plurality of scan lines (S1 to Sn), and the emission control lines may include a plurality of emission control lines (E1 to En). The data lines (D1 to Dm) and the power line PL may be connected to the pixels PXL.

The pixels PXL may be arranged in the pixel area PXA. The pixels PXL may be connected to the scanning lines S1 to Sn, the emission control lines E1 to En, the data lines D1 to Dm, and the power line PL. The pixels PXL may receive the data signals from the data lines D1 to Dm when the scanning signals are supplied from the scanning lines S1 to Sn.

Additionally, the PXL pixels can receive a first current ELVDD, a second current ELVSS, and an initialization current Vint from an external source. The first current ELVDD can be supplied via the power line PL.

Each of the pixels PXL may include a driver transistor and an OLED. In response to the data signal, the driver transistor may control a current flowing through the OLED from the first current ELVDD to the second current ELVSS. For example, before applying the data signal, a gate electrode of the driver transistor may be initialized by a voltage of the initialization current Vint.

For this purpose, the initialization current Vint can be set to a lower voltage than the data signal.

The scan driver SDV can supply the scan signals to the scan lines S1 through Sn in response to a first gate control signal (GCS1) supplied from the timing controller TC. For example, the scan driver SDV can supply the scan signals sequentially to the scan lines S1 through Sn. When the scan signals are supplied sequentially to the scan lines S1 through Sn, the pixels PXL can be selected sequentially in units of horizontal lines.

The emission driver EDV may supply the emission control signals to the emission control lines E1 through En in response to a second gate control signal GCS2 provided by the timing controller TC. For example, the emission driver EDV may supply the emission control signals sequentially to the emission control lines E1 through En.

The emission control signals can be set to have greater widths than the scanning signals. For example, the emission control signal supplied to an i-th (where I is a positive integer) emission control line Ei can overlap the scanning signal supplied to an (i-1)th scanning line Si-1 and the scanning signal supplied to an i-th scanning line Si for at least a partial period.

Additionally, the emission control signals are set to have gate-off voltages (e.g., relatively high voltages) so that the transistors included in the PXL pixels can be turned off. The scanning signals can be set to have gate-on voltages (e.g., relatively low voltages) so that the transistors included in the PXL pixels can be turned on.

The data driver DDV can supply the data signals to the data lines D1 to Dm in response to a data control signal (DCS). The data signals supplied to the data lines D1 to Dm can be supplied to the pixels PXL selected by the scanning signals.

The timing controller TC supplies the gate control signals GCS1 and GCS2 generated on the basis of externally supplied timing signals to the scanning driver SDV and the emission driver EDV and can supply the data control signal DCS to the data driver DDV.

A start pulse and clock signals may be included in each of the gate control signals GCS1 and GCS2. The start pulse may control the timing of a first sensing signal or a first emission control signal. The clock signals may be used to shift the start pulse.

A source start pulse and clock signals may be included in the data control signal DCS. The source start pulse may control a start time of data acquisition. The clock signals may be used to control a data acquisition process.

3 is an equivalent circuit diagram showing an embodiment of the pixel of 2 illustrated. In 3 For clarity, a pixel connected to a j-th data line Dj and an i-th first scanning line Si is illustrated.

According to 2 and 3 the pixel PXL may comprise an OLED “OLED”, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst (storage capacitor - Cst).

An anode of the OLED "OLED" is connected to the first transistor T1 via the sixth transistor T6, and a cathode thereof may be connected to the second current ELVSS. The OLED "OLED" may generate light of predetermined brightness in response to a current supplied by the first transistor T1.

The first current ELVDD can be set to have a higher voltage than the second current ELVSS so that current can flow to the OLED “OLED”.

The seventh transistor T7 may be connected between the initialization current source Vint and the anode of the OLED. A gate electrode of the seventh transistor T7 may be connected to the i-th first scanning line Si. The seventh transistor T7 is turned on when a scanning signal is supplied to the i-th first scanning line Si and may supply the voltage of the initialization current Vint to the anode of the OLED. The initialization current Vint may be set to have a lower voltage than a data signal.

The sixth transistor T6 may be connected between the first transistor T1 and the OLED "OLED." A gate electrode of the sixth transistor T6 may be connected to an i-th emission control line Ei. The sixth transistor T6 is turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on otherwise.

The fifth transistor T5 may be connected between the first current ELVDD and the first transistor T1. A gate electrode of the fifth transistor T5 may be connected to an i-th emission control line Ei. The fifth transistor T5 is turned off when the emission control signal is supplied to the i-th emission control line Ei, and may be turned on otherwise.

A first electrode of the first transistor T1 (e.g., the driver transistor) is connected to the first current ELVDD via the fifth transistor T5, and a second electrode thereof may be connected to the anode of the OLED "OLED" via the sixth transistor T6. A gate electrode of the first transistor T1 may be connected to a first node N1. The first transistor T1 may control a current intensity flowing from the first current ELVDD to the second current ELVSS via the OLED "OLED" in response to a voltage of the first node N1. For example, the first current ELVDD may be electrically connected to the anode of the OLED "OLED" through the first transistor T1.

The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. A gate electrode of the third transistor T3 may be connected to the i-th first scan line Si. The third transistor T3 is turned on when the scan signal is supplied to the i-th first scan line Si and may electrically connect the second electrode of the first transistor T1 and the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be diode-connected.

The fourth transistor T4 may be connected between the first node N1 and the initialization current Vint. A gate electrode of the fourth transistor T4 may be connected to an (i-1)th first scan line Si-1. The fourth transistor T4 is turned on when a scan signal is supplied to the (i-1)th first scan line Si-1 and may supply the voltage of the initialization current Vint to the first node N1.

The second transistor T2 may be connected between the j-th data line Dj and the first electrode of the first transistor T1. A gate electrode of the second transistor T2 may be connected to the i-th first scanning line Si. The second transistor T2 is turned on when the scanning signal is supplied to the i-th first scanning line Si and may electrically connect the j-th data line Dj and the first electrode of the first transistor T1.

The storage capacitor Cst may be connected between the first current ELVDD and the first node N1. The storage capacitor Cst may store the data signal and a voltage corresponding to a threshold voltage of the first transistor T1.

According to an embodiment of the present invention, the extension directions of the scanning lines and the emission control lines may vary. For example, the scanning lines and the emission control lines do not extend in the first direction DR1, which is the width direction, but the scanning lines and the emission control lines may extend in the second direction DR2, which is the length direction.

4 is a top view that specifically shows the pixel from 3 illustrated. 5 is a cross-sectional view along line II' of 4 . 6 is a cross-sectional view along line II-II' of 4 .

In 4 to 6 Based on a pixel PXL arranged in an i-th row and a j-th column in the pixel area PXA, the two scanning lines Si-1 and Si, the emission control line Ei, the power line PL, and the data line Dj connected to the pixel PXL are illustrated. In 4 to 6 For convenience, a scan line in an (i-1)th row is referred to as “the (i-1)th scan line Si-1”, a scan line in the i-th row is referred to as “the i-th scan line Si”, an emission control line in the i-th row is referred to as “the emission control line Ei”, a data line in the j-th column is referred to as “the data line Dj”, and a j-th power line is referred to as “the power line PL”.

Referring to 2 to 6 the display device may include the substrate SUB, the wiring line unit and the pixels PXL.

The substrate SUB contains a transparent insulating material and can transmit light. The substrate SUB can be a rigid substrate. For example, the substrate SUB can be a glass substrate, a quartz substrate, a glass-ceramic substrate, or a crystalline glass substrate.

Additionally, the substrate SUB can be a flexible substrate. The substrate SUB can be a film substrate or a plastic substrate containing a high-molecular-weight organic material. For example, the substrate SUB can include polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate, cellulose, and/or cellulose acetate propionate. The material from which the substrate SUB is formed can vary and can include fiber-reinforced plastic (FRP).

The wiring line unit provides signals to the pixels PXL and may include the scanning lines Si-1 and Si, the data line Dj, the emission control line Ei, the power line PL, and an initialization power line IPL.

The scan lines Si-1 and Si may extend in the first direction DR1. The scan lines Si-1 and Si may include the (i-1)th scan line Si-1 and the i-th scan line Si arranged sequentially in the second direction DR2. The scan lines Si-1 and Si may receive scan signals. For example, the (i-1)th scan line Si-1 may receive an (i-1)th scan signal. On the (i-1)th scan line Si-1, pixels PXL in the i-th row may be initialized by the (i-1)th scan signal. The i-th scan line Si may receive an i-th scan signal. The i-th scan line Si is divided and may be connected to different transistors.

The emission control line Ei may extend in the first direction DR1. The emission control line Ei is arranged between the divided i-th scanning lines Si so as to be separated from the i-th scanning lines Si. The emission control line Ei may receive the emission control signal.

The data line Dj can extend in the second direction DR2. The data line Dj can receive a data signal.

The power line PL may extend in the second direction DR2. The power line PL may be arranged such that it is separated from the data line Dj. The power line PL may receive the first current (cf. ELVDD of 2 and 3 ).

The initialization current line IPL may extend in the first direction DR1. The initialization current line IPL may be arranged between the pixels PXL in the i-th row and the pixels PXL in an (i+1)th row. The initialization current line IPL may receive the initialization current Vint.

Each of the pixels PXL may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst and an OLED “OLED”.

The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source electrode SE1, a first drain electrode DE1 and a connection line CNL.

The first gate electrode GE1 can be connected to a third drain electrode DE3 of the third transistor T3 and a fourth drain electrode DE4 of the fourth transistor T4. The connecting line CNL can connect the first gate electrode GE1, the third drain electrode DE3 and the fourth drain electrode rode DE4. One end of the connecting line CNL is connected to the first gate electrode GE1 through a first contact hole CH1, and the other end of the connecting line CNL can be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through a second contact hole CH2.

According to one embodiment of the present invention, the first active pattern ACT1, the first source electrode SE1, and the first drain electrode DE1 may each be formed from semiconductor layers that are not doped with impurities or that are doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 are formed from a semiconductor layer doped with impurities, and the first active pattern ACT1 may be formed from a semiconductor layer that is not doped with impurities.

The first active pattern ACT1 may be rod-shaped, may extend in a predetermined direction, and may be bent a plurality of times in a longitudinal direction in which the first active pattern ACT1 extends. The first active pattern ACT1 may overlap the first gate electrode GE1 when viewed from a plane. Since the first active pattern ACT1 extends longitudinally, a channel region of the first transistor T1 may also extend longitudinally. Therefore, an operating range of a gate voltage supplied to the first transistor T1 can be expanded. Therefore, the gray level of the light emitted by the OLED "OLED" can be minutely controlled.

The first source electrode SE1 may be connected to one end of the first active pattern ACT1. The first source electrode SE1 may be connected to a second drain electrode DE2 of the second transistor T2 and a fifth drain electrode DE5 of the fifth transistor T5. The first drain electrode DE1 may be connected to the other end of the first active pattern ACT1. The first drain electrode DE1 may be connected to a third source electrode SE3 of the third transistor T3 and a sixth source electrode SE6 of the sixth transistor T6.

The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source electrode SE2 and a second drain electrode DE2.

The second gate electrode GE2 may be connected to the i-th scan line Si. The second gate electrode GE2 is arranged as a part of the i-th scan line Si or may be arranged to protrude from the i-th scan line Si. According to an embodiment of the present invention, the second active pattern ACT2, the second source electrode SE2, and the second drain electrode DE2 may each be formed from semiconductor layers that are not doped with impurities or that are doped with impurities. For example, the second source electrode SE2 and the second drain electrode DE2 are formed from a semiconductor layer doped with impurities, and the second active pattern ACT2 may be formed from a semiconductor layer not doped with impurities. The second active pattern ACT2 may overlap the second gate electrode GE2. One end of the second source electrode SE2 may be connected to the second active pattern ACT2. The other end of the second source electrode SE2 may be connected to the data line Dj through a sixth contact hole CH6. One end of the second drain electrode DE2 may be connected to the second active pattern ACT2. The other end of the second drain electrode DE2 may be connected to a first source electrode SE1 of the first transistor T1 and the fifth drain electrode DE5 of the fifth transistor T5.

The third transistor T3 may have a double-gate design that prevents leakage current. For example, the third transistor T3 may include a 3a-th transistor T3a and a 3b-th transistor T3b. The 3a-th transistor T3a may include a 3a-th gate electrode GE3a, a 3a-th active pattern ACT3a, a 3a-th source electrode SE3a, and a 3a-th drain electrode DE3a. The 3b-th transistor T3b may include a 3b-th gate electrode GE3b, a 3b-th active pattern ACT3b, a 3b-th source electrode SE3b, and a 3b-th drain electrode DE3b. Hereinafter, the 3a-th gate electrode GE3a and the 3b-th gate electrode GE3b are referred to as the third gate electrode GE3, the 3a-th active pattern ACT3a and the 3b-th active pattern ACT3b are referred to as the third active pattern ACT3, the 3a-th source electrode SE3a and the 3b-th source electrode SE3b are referred to as the third source electrode SE3, and the 3a-th drain electrode DE3a and the 3b-th drain electrode DE3b are referred to as the third drain electrode DE3.

The third gate electrode GE3 may be connected to the i-th scan line Si. The third gate electrode GE3 is arranged as a part of the i-th scan line Si or may be arranged to protrude from the i-th scan line Si. For example, the 3a-th gate electrode GE3a is arranged to protrude from the i-th scan line Si, and the 3b-th gate electrode GE3b may be arranged as a part of the i-th scan line Si.

The third active pattern ACT3, the third source electrode SE3 and the third drain electrode DE3 can each be formed from semiconductor layers that are not doped with impurities or that are doped with impurities. For example, the third source electrode SE3 and the third drain electrode DE3 are formed from a semiconductor layer doped with impurities, and the third active pattern ACT3 may be formed from a semiconductor layer not doped with impurities. The third active pattern ACT3 may overlap the third gate electrode GE3. One end of the third source electrode SE3 may be connected to the third active pattern ACT3. The other end of the third source electrode SE3 may be connected to the first drain electrode DE1 of the first transistor T1 and a sixth source electrode SE6 of the sixth transistor T6. One end of the third drain electrode DE3 may be connected to the second third active pattern ACT3. The other end of the third drain electrode DE3 may be connected to the fourth drain electrode DE4 of the fourth transistor T4. In addition, the third drain electrode DE3 may be connected to the first gate electrode GE1 of the first transistor T1 through the connecting line CNL, the second contact hole CH2 and the first contact hole CH1.

The fourth transistor T4 may have a double-gate structure that prevents leakage current. For example, the fourth transistor T4 may include a 4a-th transistor T4a and a 4b-th transistor T4b. The 4a-th transistor T4a may include a 4a-th gate electrode GE4a, a 4a-th active pattern ACT4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a. The 4b-th transistor T4b may include a 4b-th gate electrode GE4b, a 4b-th active pattern ACT4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b. Hereinafter, the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b are referred to as the fourth gate electrode GE4. The 4a-th active pattern ACT4a and the 4b-th active pattern ACT4b are denoted as the fourth active pattern ACT4. The 4a-th source electrode SE4a and the 4b-th source electrode SE4b are denoted as the fourth source electrode SE4. The 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b are denoted as the fourth drain electrode DE4.

The fourth gate electrode GE4 may be connected to the (i-1)th scan line Si-1. The fourth gate electrode GE4 is arranged as a part of the (i-1)th scan line Si-1 or may be arranged to protrude from the (i-1)th scan line Si-1. For example, the 4a-th gate electrode GE4a may be arranged as a part of the (i-1)th scan line Si-1, and the 4b-th gate electrode GE4b may be arranged to protrude from the (i-1)th scan line Si-1.

The fourth active pattern ACT4, the fourth source electrode SE4, and the fourth drain electrode DE4 may each be formed from semiconductor layers that are not doped with impurities or that are doped with impurities. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 are formed from a semiconductor layer doped with impurities, and the fourth active pattern ACT4 may be formed from a semiconductor layer not doped with impurities. The fourth active pattern ACT4 may overlap the fourth gate electrode GE4.

One end of the fourth source electrode SE4 may be connected to the fourth active pattern ACT4. The other end of the fourth source electrode SE4 may be connected to the initialization current line IPL of the pixel PXL in the (i-1)th row and a seventh drain electrode DE7 of the seventh transistor T7 of the pixel PXL in the (i-1)th row. An auxiliary connection line AUX may be arranged between the fourth source electrode SE4 and the initialization current line IPL. One end of the auxiliary connection line AUX may be connected to the fourth source electrode SE4 through a ninth contact hole CH9. The other end of the auxiliary connection line AUX may be connected to the initialization current line IPL in the (i-1)th row through an eighth contact hole CH8 of the pixel PXL in the (i-1)th row. One end of the fourth drain electrode DE4 may be connected to the fourth active pattern ACT4. The other end of the fourth drain electrode DE4 may be connected to the third drain electrode DE3 of the third transistor T3. Additionally, the fourth drain electrode DE4 may be connected to the first gate electrode GE1 of the first transistor T1 through the connecting line CNL, the second contact hole CH2, and the first contact hole CH1.

The fifth transistor T5 may include a fifth gate electrode GE5, a fifth active pattern ACT5, a fifth source electrode SE5, and a fifth drain electrode DE5.

The fifth gate electrode GE5 may be connected to the emission control line Ei. The fifth gate electrode GE5 is arranged as a part of the i-th emission control line Ei or may be arranged to protrude from the i-th emission control line Ei. The fifth active pattern ACT5, the fifth source electrode SE5, and the fifth drain electrode DE5 may each be formed from semiconductor layers that are not doped with impurities or that are doped with impurities. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 are formed from a semiconductor layer doped with impurities, and the fifth active pattern ACT5 may be formed from a semiconductor layer not doped with impurities. layer may be formed. The fifth active pattern ACT5 may overlap the fifth gate electrode GE5. One end of the fifth source electrode SE5 may be connected to the fifth active pattern ACT5. The other end of the fifth source electrode SE5 may be connected to the power line PL through a fifth contact hole CH5. One end of the fifth drain electrode DE5 may be connected to the fifth active pattern ACT5.

The other end of the fifth drain electrode DE5 may be connected to a first source electrode SE1 of the first transistor T1 and the second drain electrode DE2 of the second transistor T2.

The sixth transistor T6 may include a sixth gate electrode GE6, a sixth active pattern ACT6, a sixth source electrode SE6, and a sixth drain electrode DE6.

The sixth gate electrode GE6 may be connected to the emission control line Ei. The sixth gate electrode GE6 is arranged as a part of the i-th emission control line Ei or may be arranged to protrude from the i-th emission control line Ei. The sixth active pattern ACT6, the sixth source electrode SE6, and the sixth drain electrode DE6 may each be formed from semiconductor layers that are not doped with impurities or that are doped with impurities. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 are formed from a semiconductor layer doped with impurities, and the sixth active pattern ACT6 may be formed from a semiconductor layer not doped with impurities. The sixth active pattern ACT6 may overlap the sixth gate electrode GE6. One end of the sixth source electrode SE6 may be connected to the sixth active pattern ACT6. The other end of the sixth source electrode SE6 may be connected to the first drain electrode DE1 of the first transistor T1 and the third source electrode SE3 of the third transistor T3. One end of the sixth drain electrode DE6 may be connected to the sixth active pattern ACT6. The other end of the sixth drain electrode DE6 may be connected to a seventh source electrode SE7 of the seventh transistor T7.

The seventh transistor T7 may include a seventh gate electrode GE7, a seventh active pattern ACT7, a seventh source electrode SE7, and a seventh drain electrode DE7.

The seventh gate electrode GE7 may be connected to the i-th scan line Si. The seventh gate electrode GE7 is arranged as a part of the i-th scan line Si or may be arranged to protrude from the i-th scan line Si. The seventh active pattern ACT7, the seventh source electrode SE7, and the seventh drain electrode DE7 may each be formed from semiconductor layers that are not doped with impurities or that are doped with impurities. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 are formed from a semiconductor layer doped with impurities, and the seventh active pattern ACT7 may be formed from a semiconductor layer not doped with impurities. The seventh active pattern ACT7 may overlap the seventh gate electrode GE7. One end of the seventh source electrode SE7 may be connected to the seventh active pattern ACT7. The other end of the seventh source electrode SE7 may be connected to a sixth drain electrode DE6 of the sixth transistor T6. One end of the seventh drain electrode DE7 may be connected to the seventh active pattern ACT7. The other end of the seventh drain electrode DE7 may be connected to the initialization current line IPL. Additionally, the seventh drain electrode DE7 may be connected to the fourth source electrode SE4 of the fourth transistor T4 of the pixel PXL in the (i+1)th row. The seventh drain electrode DE7 and the fourth source electrode SE4 of the fourth transistor T4 of the pixel PXL in the (i+1)th row may be connected through the auxiliary line AUX, the eighth contact hole CH8, and the ninth contact hole CH9.

The storage capacitor Cst may include a lower electrode LE and an upper electrode UE. The lower electrode LE may be formed from the first gate electrode GE1 of the first transistor T1.

The upper electrode UE overlaps the first gate electrode GE1 and may cover the lower electrode LE as viewed from a plane. The capacitance of the storage capacitor Cst may be increased by increasing an overlap area between the upper electrode UE and the lower electrode LE. The upper electrode UE may extend in the first direction DR1. According to an embodiment of the present invention, a voltage of the same magnitude as the first current ELVDD may be supplied to the upper electrode UE. The upper electrode UE may have an opening OPN in a region where the first gate electrode GE1 and the connection line CNL touch and where the first contact hole CH1 is formed.

The OLED “OLED” may include a first electrode AD, a second electrode CD and an emission layer EML disposed between the first electrode AD and the second electrode CD.

The first electrode AD may be arranged in an emission region corresponding to each pixel PXL. The first electrode AD may be connected between the seventh source electrode SE7 of the seventh transistor T7 and the sixth drain electrode DE6 of the sixth transistor T6 through the seventh contact hole CH7, a tenth contact hole CH10, and a twelfth contact hole CH12. A first bridge pattern BRP1 may be arranged between the seventh contact hole CH7 and the tenth contact hole CH10, and a second bridge pattern BRP2 may be arranged between the tenth contact hole CH10 and the twelfth contact hole CH12.

The first electrode AD is electrically connected to the power line PL and can receive the first power (cf. ELVDD of 2 and 3 ). The second electrode CD can be connected to the second current (cf. ELVSS of 2 and 3 ).

The first bridge pattern BRP1 and the second bridge pattern BRP2 can connect the sixth drain electrode DE6, the seventh source electrode SE7 and the first electrode AD.

The following refers to 4 to 6 a construction of the display device according to an embodiment of the present invention is described in an order in which elements are laminated.

The active patterns ACT1 to ACT7 (hereinafter referred to as ACT) may be arranged on the substrate SUB. The active patterns ACT may include the first to seventh active patterns ACT1 to ACT7. The first to seventh active patterns ACT1 to ACT7 may include a semiconductor material.

A buffer layer may be arranged between the substrate SUB and the first to seventh active patterns ACT1 to ACT7.

A gate insulating layer G1 may be disposed on the substrate SUB on which the active patterns ACT are formed.

The (i-1)th scan line Si-1, the i-th scan line Si, the emission control line Ei, and the first to seventh gate electrodes GE1 to GE7 may be arranged on the gate insulating layer GI. The first gate electrode GE1 may be the lower electrode LE of the storage capacitor Cst. The second gate electrode GE2 and the third gate electrode GE3 may be integrated into the i-th scan line Si. The fourth gate electrode GE4 may be integrated into the (i-1)th scan line Si-1. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be integrated into the i-th emission control line Ei. The seventh gate electrode GE7 may be integrated into the i-th scan line Si.

A first interlayer insulating layer IL1 may be disposed on the substrate SUB on which the (i-1)th scanning line Si-1 is formed.

The upper electrode UE of the storage capacitor Cst and the initialization current line IPL can be arranged on the first interlayer insulating layer IL1. The upper electrode UE can cover the lower electrode LE. The upper electrode UE, together with the lower electrode LE, can form the storage capacitor Cst, with the first interlayer insulating layer IL1 being positioned between the upper electrode UE and the lower electrode LE.

A second intermediate insulating layer IL2 may be arranged on the substrate SUB on which the upper electrode UE and the initialization current line IPL are arranged.

The data line Dj, the connection line CNL, the auxiliary connection line AUX, the first bridge pattern BRP1 and the first conductive layer PL1 of the power line PL may be arranged on the second intermediate layer IL2.

The data line Dj may be connected to the second source electrode SE2 through the sixth contact hole CH6 passing through the first intermediate layer IL1, the second intermediate layer IL2 and the gate insulating layer GI.

The interconnection line CNL may be connected to the first gate electrode GE1 through the first contact hole CH1, which passes through the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. Additionally, the interconnection line CNL may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through the second contact hole CH2, which passes through the gate insulating layer GI, the first interlayer IL1, and the second interlayer insulating layer IL2.

The auxiliary connection line AUX may be connected to the initialization current line IPL through the eighth contact hole CH8 passing through the second interlayer insulating layer IL2. Additionally, the auxiliary connection line AUX may be connected to the fourth source electrode SE4 and the seventh drain electrode DE7 of the pixel PXL in the (i-1)th row through the ninth contact hole CH9 passing through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

The first bridge pattern BRP1 may be arranged between the sixth drain electrode DE6 and the first electrode AD as a medium for connecting the sixth drain electrode DE6 and the first electrode AD. The first bridge pattern BRP1 may be connected to the sixth drain electrode DE6 and the first source electrode SE1 through the seventh contact hole CH7, which passes through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

The first conductive layer PL1 may be connected to the upper electrode UE of the storage capacitor Cst through the third contact hole CH3 and the fourth contact hole CH4, which pass through the second interlayer insulating layer IL2. The first conductive layer PL1 may be connected to the fifth source electrode SE5 through the fifth contact hole CH5, which passes through the first interlayer insulating layer IL1, the second interlayer insulating layer IL2, and the gate insulating layer GI.

A third interlayer insulating layer IL3 may be disposed on the substrate SUB on which the j-th scanning line Dj is formed.

A second conductive layer PL2 of the power line PL and the second bridge pattern BRP2 may be disposed on the third insulating layer IL3. The second bridge pattern BRP2 may be connected to the first bridge pattern BRP1 through the tenth contact hole CH10.

The second conductive layer PL2 overlaps the first conductive layer PL1 and can be connected to the first conductive layer PL1 through an 11th contact hole CH11 passing through the third insulating layer IL3. By including the first conductive layer PL1 and the second conductive layer PL2 in the power line PL, and electrically connecting the first conductive layer PL1 and the second conductive layer PL2, it is possible to prevent a voltage drop of a current supplied through the power line PL, for example, the first current ELVDD.

A protective layer PSV may be arranged on the third insulating layer IL3 on which the second conductive layer PL2 and the second bridge pattern BRP2 are arranged.

The OLED "OLED" may be disposed on the protective layer PSV. The OLED "OLED" may include the first electrode AD, the second electrode CD, and the emission layer EML disposed between the first electrode AD and the second electrode CD.

The first electrode AD may be disposed on the protective layer PSV. The first electrode AD may be connected to the second bridge pattern BRP2 through the 12th contact hole CH12 passing through the protective layer PSV. Therefore, the first electrode AD may be electrically connected to the first bridge pattern BRP1. Since the first bridge pattern BRP1 is connected to the sixth drain electrode DE6 and the seventh source electrode SE7 through the seventh contact hole CH7, the first electrode AD may be electrically connected to the sixth drain electrode DE6 and the seventh source electrode SE7.

A pixel-defining layer PDL that divides an emission region to correspond to the respective pixels PXL may be disposed on the substrate SUB on which the first electrode AD is formed. The pixel-defining layer PDL may protrude from the substrate SUB along a periphery of the pixel PXL while exposing an upper surface of the first electrode AD.

The emission layer EML is arranged in the emission region surrounded by the pixel-defining layer PDL, and the second electrode CD can be arranged on the emission layer EML. An encapsulation layer SLM can be arranged on the second electrode CD, covering the second electrode CD.

One of the first electrode AD and the second electrode CD may be an anode electrode, and the other may be a cathode electrode. For example, the first electrode AD may be an anode electrode, and the second electrode CD may be a cathode electrode.

Additionally, at least one of the first electrode AD and the second electrode CD may be a transmitting electrode. For example, if the OLED is a back-emission type OLED, the first electrode AD is a transmitting electrode and the second electrode CD may be a reflective electrode. For example, if the OLED is a front-emission type OLED, the first electrode AD is a reflective electrode and the second electrode CD may be a transmitting electrode. For example, if the OLED is a double-emission type OLED, both the first electrode AD and the second electrode CD may be transmitting electrodes. According to one embodiment of the present invention, it is illustrated that the OLED is a front-emission type OLED and the first electrode AD is an anode electrode.

The first electrode AD may include a reflective layer for reflecting light and a transparent conductive layer disposed on or below the reflective layer. At least one of the transparent conductive layer and the reflective layer may be connected to the seventh source electrode SE7.

The reflective layer may include a material capable of reflecting light, for example, the reflective layer may include one or more of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and/or an alloy of Al, Ag, Cr, Mo, Pt, and Ni.

The transparent conductive layer may include a transparent conductive oxide. For example, the transparent conductive layer may include at least one transparent conductive oxide, such as an indium tin oxide (ITO), an indium zinc oxide (IZO), an aluminum zinc oxide (AZO), a gallium-doped zinc oxide (GZO), a zinc tin oxide (ZTO), a gallium tin oxide (GTO), and/or a fluorine-doped tin oxide (FTO).

The pixel-defining layer (PDL) may include an organic insulating material. For example, the pixel-defining layer (PDL) may include polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylether (PAE), heterocyclic polymer, parylene, epoxy, benzocyclobutene (BCB), siloxane-based resin, and/or silane-based resin.

The emission layer EML may be disposed on an exposed surface of the first electrode AD. The emission layer EML may have a multilayer thin-film construction including at least one light-generating layer LGL. For example, the emission layer EML may include a hole-injection layer HIL, a hole-transport layer HTL, a light-generating layer, a hole-blocking layer HBL, an electron-transport layer ETL, and/or an electron-injecting layer EIL. The HIL injects holes. The hole-transport layer HTL has a high hole-transport capability to prevent electrons not combined in the emission layer from moving and increase the recombination probability of holes and electrons. The light-generating layer emits light through recombination of injected electrons and holes. The hole-blocking layer HBL prevents holes not combined in the light-generating layer from moving. The electron-transport layer ETL smoothly transports electrons to the light-generating layer. The electron-injecting layer EIL injects electrons. In addition, in the emission layer EML, the hole injection layer HIL, the hole transport layer HTL, the hole blocking layer HBL, the electron transport layer ETL and the electron injection layer EIL may be common layers arranged together in adjacent pixels PXL.

A light color generated by the emission layer may be one of red, green, blue, and white. However, the present invention is not limited thereto. For example, a light color generated by the emission layer may be one of magenta, cyan, and yellow.

The second electrode CD can be a semi-transmissive reflective layer. For example, the second electrode CD can be a thin metal layer with a thickness capable of transmitting light emitted by the emission layer EML. The second electrode CD transmits a portion of the light generated by the emission layer EML and can reflect the remaining light generated by the emission layer EML.

The second electrode CD may include a material with a lower work function than the transparent conductive layer. For example, the second electrode CD may include Mo, tungsten (W), Ag, magnesium (Mg), Al, Pt, palladium (Pd), gold (Au), Ni, neodymium (Nd), iridium (Ir), Cr, lithium (Li), calcium (Ca), and an alloy of Mo, W, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, and/or Ca.

Part of the light emitted by the emission layer (EML) does not pass through the second electrode (CD), and the light reflected by the second electrode (CD) may be reflected again by the reflective layer. For example, the light emitted by the emission layer (EML) may resonate between the reflective layer and the second electrode (CD). Due to the resonance of the light, the light extraction efficiency of the OLED (OLED) may increase.

The distance between the reflective layer and the second electrode CD can vary according to the color of the light emitted from the emission layer EML. For example, the distance between the reflective layer and the second electrode CD can be controlled according to the color of the light emitted from the emission layer EML to be suitable for resonance removal.

An encapsulation layer SLM can prevent external moisture and oxygen from penetrating the OLED. The encapsulation layer SLM can contain a variety of inorganic layers and a variety of organic layers. For example, the encapsulation layer SLM may include a plurality of unit encapsulation layers, each including an inorganic layer and an organic layer disposed on the inorganic layer. Additionally, the inorganic layer may be disposed in the uppermost portion of the encapsulation layer SLM. The inorganic layer may include a silicon oxide, a silicon nitride, a silicon oxynitride, an aluminum oxide, a titanium oxide, a zirconium oxide, and/or a tin oxide.

7 is a top view showing the active patterns of 2 to 6 illustrate. 8 is a plan view showing the scanning lines, the emission control lines and the lower electrode of the storage capacitor of 2 to 6 illustrated. 9 is a plan view showing the initialization current line and the upper electrode of the storage capacitor of 2 to 6 illustrated. 10 is a plan view showing the data lines, the connection line, the auxiliary connection line and the first conductive layer and the first bridge pattern of the power line of 2 to 6 illustrated. 11 is a plan view showing the second conductive layer and the second bridge pattern of the power line of 2 to 6 illustrated. 12 is a top view showing the organic light-emitting diode (OLED) of 2 to 6 illustrated. 13 is a plan view showing the second conductive layer and the second bridge pattern of the power line and the OLED of 11 and 12 . illustrated. In 7 to 12 For the sake of clarity, elements of the pixels in the i-th row and the (i+1)th row are illustrated in the following figures.

According to 2 to 13 The first to seventh active patterns ACT1 to ACT7 may be arranged on the substrate SUB. The first to seventh active patterns ACT1 to ACT7 are arranged in the same layer and may be formed by the same process.

One end of the first active pattern ACT1 is connected to the first source electrode SE1 and the other end is connected to the first drain electrode DE1. One end of the second active pattern ACT2 is connected to the second source electrode SE2 and the other end is connected to the second drain electrode DE2. One end of the third active pattern ACT3 is connected to the third source electrode SE3 and the other end is connected to the third drain electrode DE3. One end of the fourth active pattern ACT4 is connected to the fourth source electrode SE4 and the other end is connected to the fourth drain electrode DE4. One end of the fifth active pattern ACT5 is connected to the first source electrode SE5 and the other end is connected to the fifth drain electrode DE5. One end of the sixth active pattern ACT6 is connected to the sixth source electrode SE6 and the other end is connected to the sixth drain electrode DE6. One end of the seventh active pattern ACT7 is connected to the seventh source electrode SE7 and the other end is connected to the seventh drain electrode DE7.

The scan lines Si-1, Si, and Si+1, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst may be arranged on the gate insulating layer GI formed on the first to seventh active patterns ACT1 to ACT7. The scan lines Si-1, Si, and Si+1, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst are arranged in the same layer and may be formed by the same process.

The scan lines Si-1, Si and Si+1 may include the (i-1)th scan line Si-1, the i-th scan line Si and the (i+1)th scan line Si+1.

In the i-th row, the first gate electrode GE1 is arranged on the lower electrode LE, and the fourth gate electrode GE4 is arranged on the (i-1)th scan line Si-1. The second gate electrode GE2, the third gate electrode GE3, and the seventh gate electrode GE7 may be arranged on the i-th scan line Si. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be arranged on the emission control line Ei.

In the (i+1)th row, the first gate electrode GE1 is arranged on the lower electrode LE, and the fourth gate electrode GE4 is arranged on the i-th scan line Si. The second gate electrode GE2, the third gate electrode GE3, and the seventh gate electrode GE7 may be arranged on the (i+1)th scan line Si+1. The fifth gate electrode GE5 and the sixth gate electrode GE6 may be arranged on the emission control line Ei+1.

The initialization current line IPL and the upper electrode UE of the storage capacitor Cst may be arranged on the first interlayer insulating layer IL1 formed on the scanning lines Si-1, Si, and Si+1, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst. The initialization current line IPL and the upper electrode UE of the storage capacitor Cst are arranged in the same layer and may be formed by the same process.

Data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4, the first conductive layer PL1 of the power line PL, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1 may be disposed on the second interlayer insulating layer IL2 formed on the initialization power line IPL and the upper electrode UE of the storage capacitor Cst. The data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4, the first conductive layer PL1 of the power line PL, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1 are disposed in the same layer and may be formed by the same process.

The data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4 may be connected to the second source electrode SE2 through the sixth contact hole CH6 passing through the gate insulating layer GI, the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2.

The first conductive layer PL1 may extend parallel to at least one of the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1, for example, the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4. The first conductive layer PL1 may be connected to the upper electrode UE through the third contact hole CH3 and the fourth contact hole CH4, which pass through the first conductive layer PL1 and the second interlayer insulating layer IL2. In addition, the first conductive layer PL1 may be connected to the fifth source electrode SE5 through the fifth contact hole CH5, which passes through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

The interconnection line CNL may be connected to the first gate electrode GE1 through the first contact hole CH1, which passes through the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2. Additionally, the interconnection line CNL may be connected to the third drain electrode DE3 and the fourth drain electrode DE4 through the second contact hole CH2.

The auxiliary connection line AUX may be connected to the initialization current line IPL through the eighth contact hole CH8, which passes through the second interlayer insulating layer IL2. Additionally, the auxiliary connection line AUX may be connected to the seventh drain electrode DE7 through the ninth contact hole CH9, which passes through the gate insulating layer GI, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2.

The first bridge pattern BRP1 may be connected to the seventh drain electrode DE7 and the seventh source electrode SE7 through the seventh contact hole CH7 passing through the gate insulating layer GI, the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2.

The second bridge pattern BRP2 and the second conductive layer PL2 may be disposed on a third interlayer insulating layer IL3 formed on the data line Dj, the power line PL, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1. The second bridge pattern BRP2 and the second conductive layer PL2 are disposed in the same layer and may be formed by the same process.

The second bridge pattern BRP2 may be connected to the first bridge pattern BRP1 through the tenth contact hole CH10.

The second conductive layer PL2 may include a plurality of first conductive lines CL1 and a plurality of second conductive lines CL2 intersecting the first conductive lines CL1.

One of the first conductive lines CL1 and the second conductive lines CL2, for example, the first conductive lines CL1, may be parallel to one of the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1. The first conductive lines CL1 overlap the first conductive layer PL1 in parallel and may be connected to the first conductive layer PL1 through the 11th contact hole CH11 passing through the third insulating layer IL3. By including the first conductive layer PL1 and the second conductive layer PL2 in the power line PL, and electrically connecting the first conductive layer PL1 and the second conductive layer PL2, it is possible to prevent a voltage drop of a current supplied through the power line PL, for example, the first current ELVDD.

At least some of the first conductive lines CL1 and the second conductive lines CL2 may extend in a direction oblique to at least one of the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1. For example, the second conductive lines CL2 may be arranged in a zigzag pattern in a direction intersecting the first conductive lines CL1. Because the second conductive lines CL2 are arranged in a zigzag pattern, the second conductive lines CL2 may not overlap the OLEDs "OLED." For example, the second conductive lines CL2 may be arranged in a region between adjacent OLEDs "OLED."

For example, the second conductive lines CL2 may include a plurality of interconnected conductive pattern units. The conductive pattern units may include a first conductive pattern CP1, a second conductive pattern CP2, a third conductive pattern CP3, and a fourth conductive pattern CP4.

One end of the first conductive pattern CP1 may be connected to the second conductive pattern CP2. Additionally, at least a portion of the first conductive pattern CP1 may intersect one of the first conductive lines CL1.

One end of the second conductive pattern CP2 is connected to one end of the first conductive pattern CP1 and may extend in a direction oblique to the first conductive lines CL1.

The third conductive pattern CP3 may extend parallel to the first conductive pattern CP1. One end of the third conductive pattern CP3 is connected to the other end of the second conductive pattern CP2, and the other end of the third conductive pattern CP3 may be connected to one end of the fourth conductive pattern CP4. Additionally, at least a portion of the third conductive pattern CP3 may intersect another of the first conductive lines CL1.

The other end of the fourth conductive pattern CP4 may be connected to the other end of the first conductive pattern CP1 of an adjacent conductive pattern unit. The fourth conductive pattern CP4 may extend in a direction intersecting the first conductive line CL1, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3.

When the first conductive lines CL1 and the second conductive lines CL2 of the second conductive layer PL2 overlap the OLEDs, step differences may be generated by the second conductive layer PL2 among the OLEDs. Due to the step differences, surfaces of the OLEDs are not uniform, and concave-convex parts may be formed in partial areas of the OLEDs. For example, when surfaces from which light components are emitted have concave-convex parts due to the step differences in the OLEDs, since the light components are not emitted uniformly from the OLEDs, a color difference may be generated according to a viewing angle of the display device including the OLEDs.

According to an embodiment of the present invention, a part of the second conductive layer PL2, for example, the second conductive lines CL2, can be arranged in a region between the OLEDs "OLED" without overlapping the OLEDs "OLED". Therefore, an overlap area between the second conductive layer PL2 and the OLEDs "OLED" can be reduced. By reducing the overlap area between the second conductive layer PL2 and the OLEDs "OLED", the step differences among the OLEDs "OLED" can be reduced. By reducing the step differences, the concavo-convex parts of the surfaces from which the light components are emitted in the OLEDs "OLED" can be reduced. Therefore, the light components "OLED" generated by the OLEDs "OLED" can be emitted uniformly according to a viewing direction. Therefore, the color difference according to the viewing angle of the display device including the OLEDs "OLED" can be reduced.

The OLEDs "OLED" may be arranged on a protective layer PSV formed on the second conductive layer PL2 and the second bridge pattern BRP2. Each of the OLEDs "OLED" may include a first electrode AD formed on the protective layer PSV, an emission layer EML formed on the first electrode AD, and a second electrode CD formed on the emission layer EML.

The first electrode AD can be connected to the second bridge pattern BRP2 through the 12th contact hole CH12 passing through the protective layer PSV.

Below, with reference to 14 to 16 , display devices according to embodiments of the present invention are described. Referring to 14 to 16 the same elements as those of 1 to 13 denoted by the same reference numerals and a brief description thereof is given. In addition, the description given herein focuses on 14 to 16 mainly on elements other than those of 1 to 13 and it is understood that elements not described herein may be assumed to be similar to those described above.

14 is a plan view illustrating a second power line, a second bridge pattern, and an OLED of a display device according to an embodiment of the present invention.

Referring to 2 to 10 and 14 The first to seventh active patterns ACT1 to ACT7 can be arranged on the substrate SUB. The first to seventh active pattern ACT1 to ACT7 is arranged in the same layer and can be formed by the same process.

The scan lines Si-1, Si, and Si+1, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst may be arranged on the gate insulating layer GI formed on the first to seventh active patterns ACT1 to ACT7. The scan lines Si-1, Si, and Si+1, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst are arranged in the same layer and may be formed by the same process.

The initialization current line IPL and the upper electrode UE of the storage capacitor Cst may be arranged on the first interlayer insulating layer IL1 formed on the scanning lines Si-1, Si, and Si+1, the emission control lines Ei and Ei+1, and the lower electrode LE of the storage capacitor Cst. The initialization current line IPL and the upper electrode UE of the storage capacitor Cst are arranged in the same layer and may be formed by the same process.

The data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4, the first conductive layer PL1 of the power line PL, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1 may be arranged on the second interlayer insulating layer IL2 formed on the initialization power line IPL and the upper electrode UE of the storage capacitor Cst. The data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4, the first conductive layer PL1, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1 are arranged in the same layer and may be formed by the same process.

The second bridge pattern BRP2 and the second conductive layer PL2 may be disposed on the third interlayer insulating layer IL3 formed on the data line Dj, the power line PL, the auxiliary connection line AUX, the connection line CNL, and the first bridge pattern BRP1. The second bridge pattern BRP2 and the second conductive layer PL2 are disposed in the same layer and may be formed by the same process.

The second bridge pattern BRP2 may be connected to the first bridge pattern BRP1 through the tenth contact hole CH10.

The second conductive layer PL2 may be connected to the first conductive layer PL1 through the 11th contact hole CH11 passing through the third insulating layer IL3. By including the first conductive layer PL1 and the second conductive layer PL2 in the power line PL, and electrically connecting the first conductive layer PL1 and the second conductive layer PL2, it is possible to prevent a voltage drop in the current supplied through the power line PL, for example, the first current ELVDD.

The second conductive layer PL2 may include the plurality of first conductive lines CL1 extending in one direction and the plurality of second conductive lines CL2 extending in a direction intersecting the first conductive lines CL1.

The first conductive lines CL1 and the second conductive lines CL2 may extend in a direction oblique to the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1. The first conductive lines CL1 and the second conductive lines CL2 intersect each other and may form a plurality of regions. The OLEDs "OLED" may be respectively arranged in the regions formed by intersecting the first conductive lines CL1 and the second conductive lines CL2. For example, the first conductive lines CL1 and the second conductive lines CL2 do not overlap the OLEDs "OLED" and may be arranged in a region between adjacent OLEDs "OLED".

Since the first conductive lines CL1 and the second conductive lines CL2 are arranged in the region between the adjacent OLEDs, the step differences among the OLEDs from the power line PL can be reduced. When the step differences among the OLEDs are reduced, the concave-convex parts of the surfaces from which the light components are emitted in the OLEDs can be reduced. When the concave-convex parts of the surfaces from which the light components are emitted in the OLEDs are reduced, the light components generated by the OLEDs can be emitted uniformly in one direction. Therefore, the color difference according to the viewing angle of the display device including the OLEDs can be reduced.

The OLEDs "OLED" may be arranged on the protective layer PSV formed on the second conductive layer PL2 and the second bridge pattern BRP2. Each of the OLEDs "OLED" may have the first electrode AD formed on the protective layer PSV, the emission layer EML formed on the first electrode AD, and the second Electrode CD formed on the emission layer EML.

The first electrode AD can be connected to the second bridge pattern BRP2 through the 12th contact hole CH12 passing through the protective layer PSV.

15 is a plan view illustrating a second power line, a second bridge pattern, and an OLED of a display device according to an embodiment of the present invention.

Referring to 2 to 10 and 15 The first to seventh active patterns ACT1 to ACT7 may be arranged on the substrate SUB. The first to seventh active patterns ACT1 to ACT7 are arranged in the same layer and may be formed by the same process.

The scanning lines Si-1, Si and Si+1, the emission control lines Ei and Ei+1 and the lower electrode LE of the storage capacitor Cst may be arranged on the gate insulating layer GI formed on the first to seventh active patterns ACT1 to ACT7.

The initialization current line IPL and the upper electrode UE of the storage capacitor Cst may be arranged on the first interlayer insulating layer IL1 formed on the scanning lines Si-1, Si and Si+1, the emission control lines Ei and Ei+1 and the lower electrode LE of the storage capacitor Cst.

The data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4, the first conductive layer PL1 of the power line PL, the auxiliary connection line AUX, the connection line CNL and the first bridge pattern BRP1 may be arranged on the second interlayer insulating layer IL2 formed on the initialization power line IPL and the upper electrode UE of the storage capacitor Cst.

The second bridge pattern BRP2 and the second conductive layer PL2 may be arranged on the third interlayer insulating layer IL3 formed on the data line Dj, the power line PL, the auxiliary connection line AUX, the connection line CNL and the first bridge pattern BRP1.

The second conductive layer PL2 may be connected to the first conductive layer PL1 through the 11th contact hole CH11 passing through the third insulating layer IL3.

The second conductive layer PL2 may include the plurality of first conductive lines CL1 extending in one direction and the plurality of second conductive lines CL2 extending in a direction intersecting the first conductive lines CL1.

The first conductive lines CL1 and the second conductive lines CL2 may extend in a direction oblique to the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1. The first conductive lines CL1 and the second conductive lines CL2 intersect each other and may form a plurality of regions.

The OLEDs "OLED" may be arranged in the regions formed by intersecting the first conductive lines CL1 and the second conductive lines CL2, respectively. At least some of the OLEDs "OLED" may overlap at least one of the first conductive lines CL1 and the second conductive lines CL2.

For example, the majority of the OLEDs "OLED" do not overlap the first conductive lines CL1 and the second conductive lines CL2. However, some of the OLEDs "OLED" may overlap at least one of the first conductive lines CL1 and the second conductive lines CL2. For example, at least some edges of the partial OLEDs "OLED" may overlap at least one of the first conductive lines CL1 and the second conductive lines CL2.

An area where some of the edges of the OLEDs overlap the first conductive lines CL1 and the second conductive lines CL2 may be smaller than an overlap area in a case where the first conductive lines CL1 and the second conductive lines CL2 pass through the OLEDs. Therefore, the step differences among the OLEDs can be reduced by the current line PL. When the step differences among the OLEDs are reduced, the concave-convex parts of the surfaces from which the light components are emitted can be reduced in the OLEDs. When the concave-convex parts of the surfaces from which the light components are emitted in the OLEDs are reduced, the light components generated by the OLEDs can be emitted uniformly according to one direction. Therefore, the color difference can be reduced according to the viewing angle of the display device incorporating the OLEDs “OLED”.

The OLEDs "OLED" may be arranged on the protective layer PSV formed on the second conductive layer PL2 and the second bridge pattern BRP2. Each of the OLEDs "OLED" may have the first electrode AD formed on the protective layer PSV is formed, the emission layer EML formed on the first electrode AD, and the second electrode CD formed on the emission layer EML.

Some of the edges of the partial OLEDs "OLED" overlap at least one of the first conductive lines CL1 and the second conductive lines CL2 to prevent the first conductive lines CL1 and the second conductive lines CL2 from being arranged adjacent to the second bridge pattern BRP2. When the first conductive lines CL1 and the second conductive lines CL2 are arranged adjacent to the second bridge pattern BRP2, the first conductive lines CL1 and the second conductive lines CL2 may be short-circuited by the second bridge pattern BRP2.

16 is a plan view illustrating a second power line, a second bridge pattern, and an OLED of a display device according to an embodiment of the present invention.

Referring to 2 to 10 and 16 The first to seventh active patterns ACT1 to ACT7 may be arranged on the substrate SUB. The first to seventh active patterns ACT1 to ACT7 are arranged in the same layer and may be formed by the same process.

The scanning lines Si-1, Si and Si+1, the emission control lines Ei and Ei+1 and the lower electrode LE of the storage capacitor Cst may be arranged on the gate insulating layer GI formed on the first to seventh active patterns ACT1 to ACT7.

The initialization current line IPL and the upper electrode UE of the storage capacitor Cst may be arranged on the first interlayer insulating layer IL1 formed on the scanning lines Si-1, Si and Si+1, the emission control lines Ei and Ei+1 and the lower electrode LE of the storage capacitor Cst.

The data lines Dj, Dj+1, Dj+2, Dj+3 and Dj+4, the first conductive layer PL1 of the power line PL, the auxiliary connection line AUX, the connection line CNL and the first bridge pattern BRP1 may be arranged on the second interlayer insulating layer IL2 formed on the initialization power line IPL and the upper electrode UE of the storage capacitor Cst.

The second bridge pattern BRP2 and the second conductive layer PL2 may be arranged on the third interlayer insulating layer IL3 formed on the data line Dj, the power line PL, the auxiliary connection line AUX, the connection line CNL and the first bridge pattern BRP1.

The second conductive layer PL2 may be connected to the first conductive layer PL1 through the 11th contact hole CH11 passing through the third insulating layer IL3.

The second conductive layer PL2 may include the plurality of first conductive lines CL1 extending in one direction and the plurality of second conductive lines CL2 extending in a direction intersecting the first conductive lines CL1.

The first conductive lines CL1 and the second conductive lines CL2 may extend in a direction oblique to the data lines Dj, Dj+1, Dj+2, Dj+3, and Dj+4 and the scan lines Si-1, Si, and Si+1. The first conductive lines CL1 and the second conductive lines CL2 intersect each other and may form a plurality of regions. The OLEDs "OLED" may be arranged in the regions formed by intersecting the first conductive lines CL1 and the second conductive lines CL2. For example, the first conductive lines CL1 and the second conductive lines CL2 do not overlap the OLEDs "OLED" and may be arranged in the region between the adjacent OLEDs "OLED".

One or more of the first conductive lines CL1 or the second conductive lines CL2 are removed so that at least two OLEDs “OLED” can be arranged in the regions formed by cutting the first conductive lines CL1 and the second conductive lines CL2.

The OLEDs "OLED" may be arranged on the protective layer PSV formed on the second conductive layer PL2 and the second bridge pattern BRP2. Each of the OLEDs "OLED" may include the first electrode AD formed on the protective layer PSV, the emission layer EML formed on the first electrode AD, and the second electrode CD formed on the emission layer EML.

Embodiments of the invention may provide a display device comprising: a substrate including a pixel region and a peripheral region; a plurality of pixels arranged in the pixel region of the substrate, each of the plurality of pixels including a light-emitting element; data lines and scanning lines connected to each the plurality of pixels; and a power line arrangement configured to supply power to the plurality of pixels, the power line arrangement comprising: a plurality of first conductive lines; and a plurality of second conductive lines intersecting the plurality of first conductive lines, the plurality of second conductive lines each being arranged in a region between adjacent light-emitting elements of the plurality of pixels, with at least some portions of the plurality of second conductive lines extending in a direction oblique to an extension direction of the data lines or the scan lines. Thus, in some embodiments, the plurality of second conductive lines may extend in a direction oblique to an extension direction of the data lines, and in other embodiments, the plurality of second conductive lines may extend in a direction oblique to an extension direction of the scan lines.

The first conductive lines and the second conductive lines may be arranged in one layer of the power line arrangement. The power line arrangement may include other conductive line portions on another layer. For example, the power line arrangement may include a first conductive layer and a second conductive layer (e.g., comprising the first conductive lines and the second conductive lines) separated by an insulating layer and connected by one or more vias in the insulating layer.

The light-emitting elements of the plurality of pixels may each include a first electrode, a second electrode, and an emission layer disposed between the first electrode and the second electrode. The current conduction arrangement may be arranged to supply current to the first electrode of each pixel.

The second conductive lines may be arranged to surround portions of the emission layer. The emission layer of each pixel may be arranged in a region surrounded by intersecting first conductive lines and second conductive lines.

The plurality of first conductive lines and the plurality of second conductive lines may extend in a direction oblique to an extension direction of the data lines or an extension direction of the scanning lines. The plurality of first conductive lines and the plurality of second conductive lines may be arranged in a region between the adjacent light-emitting elements of the plurality of pixels, and the light-emitting elements of the plurality of pixels may be arranged in a region formed by the plurality of first conductive lines and the plurality of second conductive lines. Thus, the light-emitting elements may be arranged between the plurality of first conductive lines and the plurality of second conductive lines.

In some embodiments, at least two light-emitting elements of the plurality of pixels are arranged in a region formed by the plurality of first conductive lines and the plurality of second conductive lines.

Thus, at least two light-emitting elements may be arranged in a pair between the plurality of first conductive lines and the plurality of second conductive lines.

In some embodiments, edges of at least some of the light-emitting elements of the plurality of pixels are arranged to overlap the plurality of first conductive lines or the plurality of second conductive lines.

Embodiments of the present invention have been described herein, and it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present invention.

Claims (12)

A display device, characterized by : a substrate (SUB) including a pixel region (PXA) and a peripheral region (PPA); a plurality of pixels (PXL) arranged in the pixel region (PXA) of the substrate (SUB), each of the plurality of pixels (PXL) including a light-emitting element; data lines and scanning lines electrically connected to each of the plurality of pixels (PXL); and a power line arrangement (PL) configured to supply power to the plurality of pixels (PXL), the power line arrangement being characterized by a second conductive layer (PL2), the second conductive layer (PL2) of the power line arrangement being characterized by: a plurality of first conductive lines (CL1); and a plurality of second conductive lines (CL2) intersecting the plurality of first conductive lines (CL1), wherein the plurality of second conductive lines (CL2) are each arranged in a region between adjacent light-emitting elements of the plurality of pixels (PXL) without overlapping anodes of the light-emitting elements, and wherein at least some portions of the plurality of second conductive lines extend in a direction oblique to an extending direction of the data lines or the scanning lines; wherein the first conductive lines (CL1) and the second conductive lines (CL2) are electrically connected to each other, wherein the second conductive layer (PL2) has a network pattern, and characterized in that the plurality of first conductive lines (CL1) extend in a direction parallel to the extending direction of the data lines; or the plurality of first conductive lines (CL1) and the plurality of second conductive lines (CL2) extend in a direction oblique to an extending direction of the data lines or an extending direction of the scanning lines. Display device according to Protection claim 1 , wherein the power line arrangement is further characterized by a first conductive layer (PL1) overlapping the second conductive layer (PL2). Display device according to Protection claim 1 , wherein the plurality of first conductive lines (CL1) extend in the direction parallel to the extending direction of the data lines; and wherein the plurality of second conductive lines (CL2) are each characterized by a plurality of units of conductive patterns connected to each other. Display device according to Protection claim 3 , wherein the plurality of units of conductive patterns are each characterized by: a first conductive pattern intersecting one of the plurality of first conductive lines (CL1); a second conductive pattern extending in a direction oblique to an extending direction of the plurality of first conductive lines (CL1) and having one end thereof connected to one end of the first conductive pattern; a third conductive pattern having one end thereof connected to the other end of the second conductive pattern; and a fourth conductive pattern having one end connected to the other end of the third conductive pattern and the other end thereof connected to the other end of a first conductive pattern of an adjacent unit of conductive patterns; optionally, the third conductive pattern extending parallel to the first conductive pattern; wherein optionally the fourth conductive pattern extends in a direction intersecting the plurality of first conductive lines (CL1), the first conductive pattern, the second conductive pattern and the third conductive pattern. Display device according to Protection claim 2 , wherein the plurality of first conductive lines (CL1) and the plurality of second conductive lines (CL2) extend in the direction oblique to an extension direction of the data lines or an extension direction of the scanning lines; wherein the plurality of first conductive lines (CL1) and the plurality of second conductive lines (CL2) are arranged in a region between the adjacent light-emitting elements of the plurality of pixels (PXL), and wherein the light-emitting elements of the plurality of pixels (PXL) are arranged in a region formed by the plurality of first conductive lines (CL1) and the plurality of second conductive lines (CL2); optionally, at least two light-emitting elements of the plurality of pixels (PXL) are arranged in a region formed by the plurality of first conductive lines (CL1) and the plurality of second conductive lines (CL2); wherein optionally the edges of at least some of the light-emitting elements of the plurality of pixels (PXL) are arranged to overlap the plurality of first conductive lines (CL1) or the plurality of second conductive lines (CL2). Display device according to one of the Claims 1 until 5 , wherein each of the plurality of pixels (PXL) is characterized by at least one transistor, and wherein the transistor is characterized by the following: an active pattern arranged on the substrate (SUB); a source electrode and a drain electrode connected to the active pattern; a gate electrode arranged on the active pattern with a gate insulating layer positioned therebetween; and an interlayer insulating layer covering the gate electrode and including a first interlayer insulating layer (IL1), a second interlayer insulating layer (IL2), and a third interlayer insulating layer (IL3) laminated one after the other; optionally, each of the plurality of pixels (PXL) is further characterized by a storage capacitor, and wherein the storage capacitor characterized by a lower electrode arranged in the same layer as the gate electrode and an upper electrode arranged on the first interlayer insulating layer (IL1); optionally further characterized by a conductive layer extending parallel to the data line and arranged on the second interlayer insulating layer (IL2), wherein the current line arrangement is arranged on the third interlayer insulating layer (IL3) and is connected to the conductive layer by a contact hole passing through the third interlayer insulating layer (IL3). Display device according to one of the Claims 1 until 6 , wherein the light-emitting elements of the plurality of pixels (PXL) are each characterized by a first electrode, a second electrode and an emission layer arranged between the first electrode and the second electrode, and wherein the current line arrangement is electrically connected to the first electrode, and wherein the display device is configured to supply a voltage to the first electrode that is higher than a voltage supplied to the second electrode. Display device according to Protection claim 2 , wherein the plurality of first conductive lines (CL1) extend in the direction parallel to the extension direction of the data lines, wherein each of the plurality of pixels (PXL) includes at least one transistor and a light-emitting element connected to the transistor; wherein the transistor is characterized by: an active pattern arranged on the substrate (SUB); a source electrode and a drain electrode connected to the active pattern; the gate electrode arranged on the active pattern with a gate insulating layer positioned therebetween; and an interlayer insulating layer covering the gate electrode and including a first interlayer insulating layer (IL1), a second interlayer insulating layer (IL2), and a third interlayer insulating layer (IL3) laminated one after the other, wherein the first conductive layer (PL1) extends parallel to the data lines and is arranged on the second interlayer insulating layer (IL2); and wherein the second conductive layer (PL2) is arranged on the third interlayer insulating layer (IL3) and is connected to the first conductive layer (PL1) through a contact hole passing through the third interlayer insulating layer (IL3), wherein the second conductive lines (CL2) extend in a direction perpendicular to the extending direction of the data lines and include a zigzag pattern, and wherein at least one of the plurality of second conductive lines (CL2) extends in a direction oblique to an extending direction of the data lines or the scanning lines. Display device according to Protection claim 8 wherein each of the plurality of pixels (PXL) is further characterized by a storage capacitor, and wherein the storage capacitor is characterized by a lower electrode arranged in a same layer as the gate electrode and an upper electrode arranged on the first interlayer insulating layer (IL1). Display device according to Protection claim 9 , wherein the first conductive lines (CL1) extend in a direction parallel to an extension direction of the data lines or the scanning lines. Display device according to Protection claim 10 , wherein the second conductive lines are characterized by a plurality of interconnected units of conductive patterns, each of the plurality of units of conductive patterns being characterized by: a first conductive pattern intersecting one of the first conductive lines (CL1); a second conductive pattern extending in a direction oblique to an extending direction of the first conductive line and having one end thereof connected to one end of the first conductive pattern; a third conductive pattern having one end thereof connected to the other end of the second conductive pattern; and a fourth conductive pattern having one end connected to the other end of the third conductive pattern and the other end thereof connected to the other end of a first conductive pattern of an adjacent unit of conductive patterns of the plurality of conductive patterns; wherein optionally the third conductive pattern extends parallel to the first conductive pattern, and wherein the fourth conductive pattern extends in a direction intersecting the first conductive line, the first conductive pattern, the second conductive pattern, and the third conductive pattern. Display device according to Protection claim 9 , wherein the first conductive lines and the second conductive lines extend in a direction oblique to an extension direction of the data lines or the scanning lines. wherein optionally the first conductive lines (CL1) and the second conductive lines (CL2) are arranged in a region between the adjacent light-emitting elements, and wherein the light-emitting elements are arranged in a region formed by the first conductive lines (CL1) and the second conductive lines (CL2); wherein optionally at least two light-emitting elements of the plurality of pixels (PXL) are arranged in a region formed by the first conductive lines (CL1) and the second conductive lines (CL2); wherein optionally edges of at least some of the light-emitting elements of the plurality of pixels (PXL) are arranged such that they overlap the first conductive lines (CL1).

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